KR890001224B1 - Reset and data protecting circuit - Google Patents

Abstract

The circuit for resetting only at on/off times of the system power and providing battery power to memory at off time of the system power comprises a low voltage detector (10) with hysterisis characteristics, a single stable multivibrator (20) for providing reset pulse when receiving the output from (10), a latch cct. (30) for latching the output of (20) at the edge triger position, a buffer (40) for driving the reset pulse, a CPU (50), a writing protector (60) for protecting the writing function in abnormal state, a memory selector (70) for selecting memory chip (80) with address signal of (50), and OR gate (90) for receiving signals of (30) and (70).

Description

Reset and Data Protection Circuits in Microprocessor-Based Systems

1 is a conventional microprocessor reset circuit.

2 is a block diagram according to the present invention.

3 is an output waveform diagram of the low voltage detector 10 of FIG.

4 is a detailed circuit diagram of FIG. 2 in accordance with the present invention.

5 is an angle waveform according to the operation of FIG.

6 is an equivalent circuit diagram of a low voltage detection unit when the power supply voltage is off.

7 is another exemplary embodiment of FIG. 4 at the time of expanding the memory capacity according to the present invention.

* Explanation of symbols for main parts of the drawings

10: low voltage detection unit 20: monostable multivibrator circuit

30: latch circuit 40: buffer circuit

50: microprocessor 60: write protection circuit

70: memory selection circuit 80: memory

90: gate circuit 61,71: address signal input terminal

100: address and data bus R ₁ , R _11- R ₁₇ : resistance

OP ₁₁ : Operational Amplifiers DF ₁ -DF ₂ : Deflip-Flop

MMV: Monostable Multivibrator DEC: Decode

BUF: Buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit in a system using a microprocessor. In particular, when a reset voltage is released, that is, when a low voltage is supplied rather than being turned off due to a power voltage change during use The present invention relates to a reset and data protection circuit in a system using a microprocessor that detects this and resets the system to prevent a malfunction and maintain data stored in the memory in case of power failure or power off.

In general, the reset circuit is configured to automatically set the initial state of the system at the same time the system is powered by the microprocessor. Also, when the user wants to initialize the keyboard, Pressing the reset key could do this.

In addition, a circuit has been installed so that the battery power is automatically supplied at the same time the power is turned off in order to prevent the loss of programs and data currently executed by the user when an unexpected power failure occurs due to a power failure.

1 is a conventional microprocessor (hereinafter referred to as CPU) reset circuit diagram. In FIG. 1, D ₁ is a diode, R ₁ is a resistor, C ₁ is a capacitor, N ₁ -N ₂ is an inverter, and SW ₁ is a reset. The switch CPU is a microprocessor.

Therefore, in the reset operation, when the power is turned on, the applied voltage V _cc begins to be charged to the capacitor C ₁ through the resistor R ₁ , where the inverters N ₁ -N _{2 are} connected to the capacitor C. ₁ ) Set the microprocessor (CPU) to reset for a short period of time until the charging voltage state, that is, the input voltage value "high" state, the charge voltage of the capacitor (C ₁ ) is higher than the "high" state The reset is released from the time when it becomes large, that is, after a predetermined time elapses by the charging of the capacitor C ₁ . Here, the reset release time is determined by the RC time constant of the resistor R ₁ and the capacitor C ₁ , and the diode D ₁ quickly discharges the capacitor C ₁ when the power is turned off or when the CPU is reset. If you do not have to install it for this purpose, the entire system is initialized and the initial state is automatically made. Also, if the user presses the reset switch (SW ₁ ) without turning off the power when necessary during operation, the capacitor (C ₁ ) The reset signal is initialized as the reset signal is applied to the microprocessor (CPU) while the charged voltage is discharged.

The above-described conventional function has only the function reset by the reset switch SW ₁ initially or when necessary. After the reset is released, if a sudden low voltage is applied in which the power supply voltage falls below the required power supply voltage of the CPU or memory due to a change in the power supply voltage, the capacitor C ₁ remains charged and thus the microprocessor (CPU) is not reset, causing malfunction, and also has the disadvantage of losing all the work data.

Accordingly, an object of the present invention is to provide a circuit for detecting a change in power supply voltage and stabilizing a system reset function such that a reset operation occurs only at an accurate on / off time point.

It is still another object of the present invention to provide a circuit in which battery power is supplied so that memory data is preserved even when the input power supply voltage is turned off.

Therefore, in the present invention, a low voltage detector for detecting an input voltage compared to a hysteresis characteristic so that the power is switched only at on and off points even when the power supply voltage changes, and a pulse having a constant pulse width is generated whenever there is an output of the low voltage detection circuit. A monostable multivibrator circuit, a latch circuit for latching the output, a buffer circuit for driving the output signal of the latch circuit to reset the microprocessor, and a drive signal of the buffer circuit to initialize the command. It executes a program to process data, outputs control and address signals to control other systems and each memory device, and receives / writes a chip selector address signal from the CPU during normal operation. Memory is accessed according to call and data writing in case of abnormal operation The write prevention circuit for preventing the memory from being selected, the memory selection circuit for selecting the memory area of the storage device according to the chip selector address signal of the CPU, and selecting the memory chip at the time of expansion of the memory; Therefore, the memory device comprises a gate circuit for generating chip selection logic of the memory and a memory of the storage device.

Hereinafter, with reference to the drawings of the present invention will be described in detail.

FIG. 2 is a block diagram according to the present invention, in which FIG. 10 is a low voltage detector, 20 is a monostable multivibrator circuit, 30 is a latch circuit, 40 is a buffer circuit, 50 is a CPU, 60 is a write protection circuit, and 70 is a A memory selection circuit, 80 is a memory, 90 is a gate circuit, 100 is an address and data bus, 61 and 71 are chip selector address signal terminals received from the CPU 50, and FIG. 3 is a low voltage detector 10 in the block diagram of FIG. As an output waveform diagram, the waveform of (A) in FIG. 3 is an exemplary diagram of fluctuations in power supply voltage, and (B) is an output waveform of the low voltage detection unit 10 according to the input of (A).

Therefore, the hysteresis characteristics are shown to ensure accurate conversion output at the point where the voltage is turned on (V _ON ) and the voltage is turned off (V _OFF ) even when the voltage is low as shown in (b). If applied, the reset circuit is not affected unless the voltage is below _OFF (V _OFF ), so the steady state is maintained.

When the power is turned on, the output of the low voltage detection unit 10 resets the latch circuit 30, and is applied to the monostable multivibrator 20 to generate a pulse having a constant pulse width to the latch circuit 30. Is entered. At this time, the output converted by the latch circuit 30 disables the buffer arc 40 so that the reset state is maintained until the buffer circuit 40 is disabled until the CPU 50 is powered on. While releasing this state, the chip selector address signal is sent from the CPU 50 to the decode input terminal 61 and the memory selection circuit input terminal 71 and input to the write prevention circuit 60 or the memory selection circuit 70. When a function of writing data into the memory 80 and / or write protection is selected according to the output of the write protection circuit 60, the memory 80 is output by the memory selection circuit 70 and the output of the latch circuit 30. Chip is selected to make memory 80 available.

When the low voltage is applied due to the input voltage variation, the low voltage sensing unit 10 is in the normal state so that the operation change does not occur unless the input power reaches the V _OFF point as described above in FIG. 3.

However, when the power supply voltage is below the power off (V _OFF ), the output of the low voltage detection unit 10 is changed so that the signal is applied to the monostable multivibration circuit circuit 20 and the latch circuit 30 so that the latch circuit ( The output of 30 is changed and a signal is applied to the write prevention circuit 60 so that the latch circuit 30 and the gate circuit 90 are stopped even if the writing is interrupted and the power is turned off regardless of the CPU 50. The battery power is automatically supplied to the memory 80, and the internal data is retained even after the power is turned off. In addition, when the user pushes the reset switch, it is applied to the low voltage detection unit 10 to put the CPU 50 in the reset state and prevent the data from being written into the memory 80 by the write prevention circuit 60.

4 is a circuit diagram illustrating the block diagram of FIG. 2, in which R ₁₁ -R ₁₇ is a resistor, OP ₁₁ is an operational amplifier, ZD is a zener diode, MMV is a monostable multivibrator, and DF ₁ -DF ₂ is Delay Flip Flop, DEC is a decoder, MSE is a memory selector, SRAM is a memory, CPU is a microprocessor, BUF is a buffer, NA ₁₁ is a NAND gate, SW ₁ is The reset switch, N _21, is an inverting gate, and a portion consisting of the resistors R _11- R ₁₆ , the zener diode ZD ₁ , the operational amplifier OP ₁₁ , and the switch SW ₁ includes a low voltage sensing unit ( 10), a portion composed of a monostable multivibrator (MMV), a resistor (R ₁₇ ), and a capacitor (C ₁₂ ) corresponds to the monostable multivibrator circuit (20), and an inverted gate (N ₂₁ ), the D flip-flop (DF ₁₎ a portion corresponding to the latch circuit 30 is configured, and a buffer (BUF) corresponds to the buffer circuit (40), a microprocessor CPU 50, Response and decoding (DEC), D flip-flop (DF ₂₎ as corresponding to a write protection circuit 60, a portion configured, and a memory selector (MSE) is corresponding to the memory selection circuit (70), SRAM memory (80 NAND gate NA ₁₁ corresponds to the gate circuit 90 with an OR gate function, and the bus BUS corresponds to the address and data bus 100.

(A)-(g) waveforms of FIG. 5 are the operational waveform diagrams of the parts shown in FIG. 4, and FIG. 6 is an equivalent circuit diagram of the low voltage sensing unit 10 block of FIG. ) and the R ₁₃ -R ₁₆ are as shown in the resistance (Y) configuration of claim 4 is also the same as described above in the low-voltage detector (10) (X) compared to turn the output voltage (OP ₁₁₎ is shown to be "high." The equivalent circuit (Y) is the equivalent circuit shown when the comparative output voltage OP ₁₁ is " low ".

Therefore, when in conjunction with the drawings described above an embodiment of the present invention will be described in detail FIG. 5 (a) the input power source voltage as shown in waveform input via a resistor (R ₁₃₎ and a resistance (R ₁₁₎ of resistors (R ₁₃ ) And the power divided by the resistor (R ₁₅ ) are input to the non-inverting end of the operational amplifier (OP ₁₁ ), and the zener diode (ZD ₁ ) calculates the zener voltage (V _Z ) lower than the power supply voltage (V _CC ). amplifier is input to the (OP ₁₁₎ makin is compared in the operational amplifier (OP ₁₁₎ the first be powered-on in ㉮ area as 3 help (a) the voltage rises to from a ground (GND) power supply voltage (V _CC) to be a comparison output voltage is "high" in the term-inverting input voltage (V ^-) is the non-inverting input voltage (V ⁺⁾ than higher because the power supply voltage (Von) to satisfy this requirement is a low voltage when the sixth-degree power supply voltage off detection unit As shown in (X)

)은 “하이”에서 “로우”로 제5도의 (e)와 (f)의 파형과 같이 출력된다.It is determined as shown in the above formula and becomes “high” and is output to the operational amplifier (OP ₁₁ ) output terminal as shown in (b) of FIG. 5, and this signal resets the reset terminal R of the flip-flop DF ₁ . In addition, the pulse width T _S is determined by the resistor R ₁₇ and the capacitor C ₁₂ to be applied to the monostable multi-vibrator MMV, so that a pulse as shown in FIG. Is generated. When the generated pulse signal is inverted as shown in (d) of FIG. 5 at the inverting gate N ₂₁ and input to the clock terminal CK of the flip-flop DF ₁ , the rising edge of this clock is depressed at the rising edge. The output (Q) of the flip-flop (DF ₁ ) is latched from "low" to "high" in the initial state, and the output (of the flip-flop (DF ₁ )

) Is output from "high" to "low" as shown in the waveforms of (e) and (f) in FIG.

단자에 독출 (

)신호를 “로우”로 할때 CPU의 프로그램 제어에 따라 어드레스신호를 메모리 선택 회로(MSE)입력하여 이 출력을 낸드게이트(NA₁₁)에 디플립플롭(DF₁)의 출력(

)과 같이 입력시켜 “로우”가 되면 독출신호(

)에 따라 내부의 데이타가 읽혀져 데이타버스를 통해 출력되며, 메모리(SRAM)내의 데이타를 쓰고자 할때도 CPU으로부터 칩실렉터 어드레스신호가 디코드 입력단자(61)를 통해 디코드(DEC)에 인가되면 “로우”가 출력되고 이 디코드(DEC)출력의 “로우”가 디플립플롭(DF₂)의 D 단자에 입력되어 디플립플롭(DF₂)의 클릭(CK) 입력단으로 입력되는 기입신호(

)에 의해“하이”에서 “로우”로 래치되면서 디플립플롭(DF₂)의 출력(Q)는“로우”가 되면서 메모리(SRAM)에 데이타를 쓸수 있는 상태로 만들어주며 여기서 메모리(SRAM)의 어드레스(칩실렉터)는 그 영역이 다르므로 메모리 선택회로(MSE)에서 칩선택신호는 출력되지 않는다.The deflip-flop output (Q) is then supplied “high” to the buffer BUF to disable it, so the output of the buffer BUF goes from “low” to “high” so that the microprocessor (CPU) is powered on. The reset state is maintained for the time T _S of FIG. 5C, and the reset state is released as the waveform of (g) of FIG. 5, and the system is initialized and the address of the microprocessor (CPU) is The chip selector address signal of the address is sent to the decode input terminal 61 and the memory selection circuit 71 through the bus to output “low” as an output, respectively, to select data to be written and read in the memory (SRAM), and then to the memory (SRAM). The selection logic of writing and reading the data in the

Read to terminal (

When the signal is set to "low", the output signal of the flip-flop (DF ₁ ) is input to the NAND gate (NA ₁₁ ) by inputting the address signal into the memory select circuit (MSE) according to the CPU program control.

) And enter “Low” when the readout signal (

The internal data is read and output through the data bus, and when the chip selector address signal is applied from the CPU to the decode (DEC) through the decode input terminal 61, even when trying to write the data in the memory (SRAM), it is “low”. "is output to the decoding (DEC) output of the" write input to a low, "the D flip-flop is input to a D terminal of the (DF ₂₎ D flip-flops click (CK) input terminal of the (DF ₂₎ signal (

), The output (Q) of the flip-flop (DF ₂ ) becomes "low" and the data can be written to the memory (SRAM), which is latched from "high" to "low". Since the address (chip selector) has a different area, the chip select signal is not output from the memory select circuit MSE.

In this state, when data is written to the memory (SRAM) address area, the flip-flop (DF ₂ ) remains “low” while writing data to the memory (SRAM), so the data is written to the memory (SRAM). When the data is written to the memory, the DEC is not set in the address area for writing, so it is output as “high” and when the data is changed from “low” to “high” of the clock pulse of the write signal WR, the flip-flop (DF ₂₎ Output Q is "high" to prevent data from being written into the memory (SRAM).

The system of and any or demand reset switch (SW ₁₎ reset the fifth degree (b) low-voltage detection circuit 10 in the T _SW (reset contact) region as a waveform when using the abnormal behavior The output of the operational amplifier OP ₁₁ is in the “low” state and the comparative output voltage at the time when the power supply (V _CC ) falls to the ground (GND) from the waveform of FIG. 3 (A) to (c). the "low" non-inverting input voltage (V ^-) to become a power supply voltage (V _OFF) to satisfy this requirement because it must be <inverting input voltage (V ⁺⁾ is, as shown in Figure 6 (Y)

)은 “하이” 로 되며 이어서 디플립플롭(DF₁)의 래치출력(Q)에 의해 버퍼(BUF)은 인에이블되어 마이크로프로세서 (CPU)를 리세트 상태로 하고 또한 디플립플롭(DF₁)의 출력(Q) “로우”가 디플립플롭(DF₂)의 세트단자(S)에 입력되어 디플립플롭(DF₂)에 래치출력(Q)를 “하이” 상태로 만들어 메모리(SRAM)내의 데이타가 기입되지 못하게 되며, 디플립플롭(DF₁)의 출력(

)는 오아게이트(OR₁₁)로 입력되는데 이 오아게이트(OR₁₁)는 어느한쪽 입력단자에 “하이”가 입력되면 출력은 “하이”가 되어 메모리(SRAM)에 입력되므로 CPU 에 관계없이 억세스(Access)할수없다. 그리고 디플립플롭(DF₁)의 출력(

)의 “하이”가 오아게이트(OR₁₁)에 입력되지만, 또한 다른 부분에 “하이”를 공급하여 메모리데이타보존 및 다른 목적으로 사용될수도 있다. 또한 리세트 스위치(SW₁)의 접점이 오프될시에는 단안정 멀티바이브레터 (MMV)의 리세트단자(R)에 연산증폭기 (OP₁₁)의 비교출력이 “로우”에서“하이”로되어 저항(R₁₇), 캐패시터(C₁₂)의 시정수에 의해 제5도의 (C)파형의 펄스폭(T_S2)의 클럭을 발생시키므로 T_S2시간만큼 시스템에 필요한 리세트 타임을 공급하게 되고 단안정 멀티바이브레터(MMV)의 출력(Q)이 “하이”에서“로우”로 되는 순간부터 CPU의 리세트 상태가 해제된다.Is obtained by. When the reset switch SW ₁ is turned ON, the comparison output of the operational amplifier OP ₁₁ is set to “high” as shown in the waveform T _{SW of} FIG. the output of the reset output (Q) is "low", (DF ₁₎ of the terminal (R) is applied to the D flip-flop (DF ₁₎ of the DF ₁₎ (

) Becomes “high” followed by the latch output (Q) of the deflip-flop (DF ₁ ) to enable the buffer BUF to reset the microprocessor (CPU) and also to the def-flop (DF ₁ ). in the output (Q) "low" the D flip-flop is input to a set terminal (S) of (DF ₂₎ D flip-flops made of memory (SRAM) the latch output (Q) to "high" state to (DF ₂₎ Data will not be written, and the output of the deflip-flop (DF ₁ )

) Is the Iowa gate is input to the Iowa gate (OR ₁₁₎ (OR ₁₁₎ is when the "High" is input to either the input terminal output becomes "High" is input to the memory (SRAM) access, regardless of the CPU ( Access) And the output of the deflip-flop (DF ₁ )

) Is input to the OA gate (OR ₁₁ ), but can also be used for memory data preservation and other purposes by supplying "high" to other parts. When the contact of the reset switch SW ₁ is turned off, the comparison output of the operational amplifier OP ₁₁ goes from "low" to "high" at the reset terminal R of the monostable multivibrator (MMV). Since the clock of pulse width T _S2 of waveform (C) of FIG. 5 is generated by the time constant of the resistor R ₁₇ and the capacitor C ₁₂ , the required reset time is supplied to the system for the time T _S2. The reset state of the CPU is released from the moment when the output Q of the stable multivibrator (MMV) goes from "high" to "low".

)은 “하이”가 되며 이어서 낸드게이트(NA₁₁)에 인가되어 결국 “하이”가 메모리(SRAM)에 인가되고 디플립플롭(DF₁)의 출력(Q)은“로우”가 되어 디플립플롭(DF₂)의 세트단자(S)에 인가되므로 디플립플롭 (DF₂)의 출력(Q)이 “하이”가 되어 메모리(SRAM)의 기입을 방지함과 동시에 정전대비용 밧데리로부터 디플립플롭(DF₁-DF₂)과 오아게이트(OR₁₁) 및 메모리(SRAM)에 밧데리 전원(V_Bat)이 공급되므로 메모리(SRAM)내에 데이타가 보존된다.When the power is turned off, that is, when the waveform is the same as the waveform (a) of FIG. ₅ , the comparison output of the operational amplifier OP ₁₁ becomes V ⁺ V ⁻ as described above from the time of the waveform (a) of FIG. Low ”and this signal is applied to the reset terminal R of the deflip-flop (DF ₁ ), so that the output (Q) of the deflip-flop (DF ₁ ) is“ low ”and the output (

) Becomes “high” and is then applied to NAND gate (NA ₁₁ ) so that “high” is applied to memory (SRAM) and output (Q ₁ ) of deflip-flop (DF ₁ ) becomes “low” (DF ₂₎ the set terminal (S) is applied, because D flip-flop (DF ₂₎ output (Q) is "high" is a memory (SRAM) prevents the address and at the same time D flip-flop from the power failure for cost battery of the Since the battery power supply (V _Bat ) is supplied to the (DF ₁ -DF ₂ ), the oragate (OR ₁₁ ), and the memory (SRAM), data is stored in the memory (SRAM).

FIG. 7 illustrates an embodiment using a plurality of memories such as a dotted line when the capacity of the memory (SRAM) is expanded, and corresponds to the PT indicated by the dotted line of FIG. 4. In FIG. 7, N ₃₁ represents an inverted gate, DEC, SRAM, MSE and DF ₂ correspond to those described above in FIG.

Therefore, when the chip selector address signals of the CPU are input to the decode DEC and the memory selection circuit MSE through the terminals 61 and 71, the outputs are output as "low", respectively.

)은 “로우”가 되어 디플립플롭(DF₂)의 세트단자(S)에 “하이”가 입력되고, 반전게이트(N₃₁)에 “로우”가 입력되며 이 반전게이트(N₃₁)에 “로우”가 입력되며 이 반전게이트(N₃₁)를 통해 반전될때 독출신호(

)가 “로우”에서 메모리 선택회로 (MSE) 출력에 따라 독출되며, 디코드 (DEC) 출력에 따라 디플립플롭(DF₂)의 출력(Q)이 “하이”에서 “로우”로 될때 기입된다. 그리고 리세트 혹은 전원오프시는 디플립플롭(DF₁)의 출력(Q)은 “로우”이고, 출력(

)은 “하이”가 되므로 디플립플롭(DF₂)의 (Q)의 출력이 “하이”가 되며, 디플립플롭(DF₁)의 출력(

)의“하이”에 의해 반전게이트(N₃₁)의 출력이 “로우”가 되므로 기입이 방지되며 동시에 정전용 밧데리 전원(V_BAT)이 디플립플롭(DF₂), 반전게이트(N₃₁), 메모리(SRAM)에 공급되어 메모리(SRAM)의 데이타가 보존되며, 사용목적에 따라 메모리(SRAM)을 확장할 경우 점선으로 도시한 예와같이 메모리 선택회로(SRAM)에 확장 메모리를 조합하여 CPU에서 주어지는 어드레스 실렉터 신호에 의해 메모리 선택회로(MSE)에서 칩선택 논리를 발생시켜 원하는 메모리 영역을 선택할수 있다.In the normal state, the output (Q) of the deflip-flop (DF ₁ ) is “high” and the other output (

) Is the "Low" D flip-flop (DF ₂₎ is "high" to the set terminal (S) is input, the "low" input, and the inverting gate (N ₃₁₎ to the inverting gate (N _31). " Low ”is inputted and read signal (when inverted through the inverted gate N ₃₁ ).

) Is read according to the memory select circuit (MSE) output at "low", and is written when the output (Q) of the flip-flop (DF ₂ ) goes from "high" to "low" according to the decode (DEC) output. When the reset or power-off, the output Q of the flip-flop DF ₁ is “low” and the output (

) Is the output of and the "High", so the output D is "high" in the (Q) of the flip-flop (DF _2), D flip-flop (DF ₁₎ (

) "High", the output of the inverting gate (N ₃₁₎ is prevented and the writing, so the "low" by the same time constant only battery power supply (V _BAT), a D flip-flop (DF _2), inverting gate (N ₃₁ a), It is supplied to the memory (SRAM) to preserve the data of the memory (SRAM), and when the memory (SRAM) is expanded according to the purpose of use, the expansion memory is combined with the memory selection circuit (SRAM) as shown in the dotted line. Given the address selector signal, the chip select logic can be generated in the memory selection circuit MSE to select a desired memory area.

Therefore, as described above, when a low voltage below a certain voltage due to fluctuation of the power supply voltage is applied or needs to be reset, the microprocessor is automatically reset and the data in the memory necessary for program execution is protected. Therefore, there is an advantage that can easily configure the system to prevent the malfunction of the system and increase the reliability.

Claims (3)

In the system constituted of the CPU 50 and the memory 80, the low voltage detector 10 and the low voltage detector 10 which are compared by the hysteresis characteristics so that the output is converted only at the on and off points even when the power supply voltage varies. Monostable multivibrator circuit 20 and monostable multivibrator circuit which are reset by the low voltage sensing unit 10 and the low voltage sensing unit 10 are generated. A latch circuit 30 for latching the output pulse of 20 at an edge trigger; a buffer circuit 40 for driving a reset signal to reset the CPU 50 in accordance with the output of the latch circuit 30; The write prevention circuit 60 which receives and decodes the chip selector signal among the address signals of the CPU 50 and controls the writing of the memory 80 according to the normal / abnormal power supply, and receives the chip selector address signal of the CPU 50 to receive the memory ( 80) Select Chip In addition, the memory selection circuit 70 selects the chip memory 80 according to the memory area and the output of the latch circuit 30 and the output of the memory selection circuit 70 are ORed so as to select the chip. A reset and data protection circuit in a system using a microprocessor, characterized in that it comprises a gate circuit (90). In the low voltage sensing unit 10 of claim 1, the resistors R ₁₃ -R ₁₆ are provided as non-inverting input terminals of the operational amplifier OP ₁₁ , the resistors R _11- R _{12 are used} as inverting inputs, and the zener diode ZD is provided. And a reset switch (SW ₁ ) configured at the output terminal to have hysteresis characteristics so that the inverting input (V ⁻ ) voltage and the non-inverting input (V ⁺ ) voltage are compared to convert the zener voltage of the zener diode (ZD) to the power supply voltage (V). Resetting and data protection circuit in a system using a microprocessor, characterized in that the low voltage is sensed to lower than _CC ). Of paragraph 1 write protection in the circuit 60, a set terminal (S) output at the time of receiving a chip selector address signal from the CPU (50) to the decoder input terminal 61, a reset or a power-off D flip-flop (DF ₂₎ A reset and data protection circuit in a system using a microprocessor, characterized in that a decoder (DEC) and a deflip-flop (DF ₂ ) are configured to prevent data writing.

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