JPH05274217A - Eeprom/eprom detecting system - Google Patents

Abstract

PURPOSE:To detect erroneous mounting when switching connection is different from a mounted device by performing specified device detection flow. CONSTITUTION:First of all, a CPU (C) performs EEPROM setting by impressing signals at an 'L' level to a selector SC. In this case, inputs B1, and B2, of the selector SC are connected to outputs Y1 and Y2. At such a time, data X are read from an address 4000(H), data Y are read from an address 0000(H), it is judged whether both of data X and Y are coincident or not, when they are not coincident, EEPROM mounting is judged and when they are coincident, the CPU switches the select signal to an 'H' level. In this case, inputs A1 and A2 of the selector SC are connected to the outputs Y1 and Y2. At such a time, the data X are read from the address 4000(H), the data Y are read from the address 0000(H), it is judged whether both of data X and Y are coincident or not, when they are not coincident, EPROM mounting is judged and when they are coincident, unmounting is judged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EEPROM / EPROM detection system used as a user program memory of a programmable controller memory.

[0002]

2. Description of the Related Art FIG. 4 shows a circuit configuration using a conventional example system, which is a 256 Kbit EEPROM or EPRO.
The IC socket (A) that can connect and replace M is equipped with 28 connection pins. In the figure, the connection pins 1 to 8 correspond to the data terminals of data D _{0 to} D ₇ ,
The 9th connecting pin corresponds to the ground terminal, the 10th to 23rd connecting pins correspond to the addresses A _{0 to} A ₁₃ , and the 24th connecting pin corresponds to the address A ₁₄ terminal in the EPROM. In addition, the EERROM corresponds to the read / write control terminals, and the 25th connection pin is EPR.
For OM, it is connected to Vpp terminal, and for EEPROM, address A ₁₄
No. 26 and No. 27 connecting pins are CS
Corresponds to terminals and OE terminals, and the 28th connection pin is Vc
Corresponding to the c terminal, the connection pins 1 to 8 are connected to the CPU (C) via the data bus (DB), and the connection pins 10 to 23 are the direct address bus (AB). connecting pins of the CPU (C), also the 24th through is connected to the common terminal C ₁ of the change-over switch (SW _1), the control lines for reading and writing CPU by switching (C) (MWR) or address a ₁₄ Are switched and connected to the address bus (AB) corresponding to. In addition, the connection pin No. 25 is connected to the common terminal C ₂ of the changeover switch (SW ₂ ) interlocking with the changeover switch (SW ₁ ) and connected to the address bus (AB) corresponding to the address A ₁₄ or the power supply Vpp. It has become.

As described above, since the corresponding terminals are different depending on whether the one connected to the IC socket (A) is EERROM or EPROM, in the conventional circuit, the changeover switches (SW ₁ ) and (SW ₂ ) are changed. It was made to correspond to the device used.

[0004]

By the way, in the above-mentioned conventional example, there is a problem that the following inconvenience occurs when the switching connection which does not correspond to the mounted device is made. That is, when the EPROM is connected while the switching connection corresponding to the EEPROM is being performed, when the data is read from the CPU (C), the control line (MWR) becomes "H", so that the address A _{14 of} the EPROM is It becomes "H", so that only the latter half of 16KB can be read.

If the EEPROM is connected while the switching connection corresponding to the EPROM is being made, the CPU
By selecting the chip from (C), the CS terminal is shown in FIG.
As shown in FIG. 5A, when the chip is selected as “L” and the address for calling address 0 is set, the terminals corresponding to the addresses A _{1 to} A ₁₃ are connected to the terminals shown in FIG.
As shown in FIG. 5, given address data is given, but the terminal corresponding to the address A ₁₄ is hung up by the power supply Vcc to become “H” as shown in FIG. 5C, and the terminal corresponding to the WR terminal is As shown in FIG. 5 (e), it becomes "L", so that the EEPROM is in a state in which the out enable signal is applied from the CPU (C) to the OE terminal as shown in FIG. 5 (d). There is a problem in that writing may occur and incorrect writing may occur.

The invention according to claim 1 is made in view of the above problems, and the purpose thereof is to detect this erroneous mounting when the switching connection and the mounting device are different. Another object of the present invention is to provide an EEPROM / EPROM detection method which can be done and which does not destroy the contents stored in the EEPROM. An object of the present invention is to provide an EEPROM / EPROM detection system capable of detecting the erroneous mounting when the switching connection and the mounting device are different and automatically performing the correct switching connection. To provide.

[0007]

The invention according to claim 1 is
A terminal to which a read / write control signal is connected corresponds to an address terminal corresponding to the most significant bit in an address terminal of an EPROM having the same storage capacity and the same number of pins, and the terminal of the most significant bit in the address terminal is the EPROM. Corresponding to the terminals other than the address terminals, and the remaining address terminals are EPR
A system in which an EEPROM having the same position as the remaining address terminals of the OM and a data terminal at the same position and the EPROM are exchangeably mounted in the same IC socket and the connection between the CPU and the IC socket is switched according to the mounting device. The EEPROM used and the first bit represented by a binary number of a predetermined number of bits in which the logical value of the most significant bit of the EPROM is "1" and the logical value of the remaining bits is "0".
Data is written in advance to the second address and data different from the above data is written in advance to the second address represented by the binary number of the above predetermined number of bits in which the logical values of all bits are "0". The CPU sequentially reads the data at the first address, the second address, and the first address while the EEPROM or any one of the EPROM devices is mounted in the IC socket, and first reads the data from the first address. If the read data and the data read from the first address for the second time do not match, the data read from the first address first is stored as write-back data, and the EEPROM is mounted for the switching connection to the EPROM. Data is read from the first address and the first address is read second time. Data read from the match and and first data and the second read from the first address
If the data read from the address of the same matches the EPROM for the switching connection to the EEPROM.
The data read from the first address is the same as the data read from the first address for the second time, and the data read from the first address and the second address If the read data does not match, it is determined that the correct device is installed for connection switching, and if the write-back data is stored, write-back data is written to the mounted EEPROM. Is a feature.

According to a second aspect of the invention, a terminal to which a read / write control signal is connected corresponds to an address terminal corresponding to the most significant bit among the address terminals of EPROMs having the same storage capacity and the same number of pins, and The most significant bit of the address terminals corresponds to a terminal other than the address terminal of the EPROM, the remaining address terminals are at the same position as the remaining address terminals of the EPROM, and the data terminals are also at the same position; Are mounted in the same IC socket interchangeably, and the CPU and I
It is used in a system that switches the connection of the C socket, and uses a selector that switches the connection between the CPU and the IC socket according to the mounting device by a selection signal from the CPU.
The EEPROM to be used and the first address in which the logical value of the most significant bit of the EPROM is “1” and the logical value of the remaining bits is “0” are written in advance, and the logical values of all bits are Data different from the above data is written in advance to the second address which is "0",
While either the EEPROM or the EPROM is mounted, the CPU first provides the selector with a selection signal for switching connection corresponding to the EEPROM, and in the CPU, the data of the first address and the second address is also supplied. Are sequentially read, and if the data read from the first address and the data read from the second address do not match, it is determined that the mounting device is compatible with switching connection, and if they match, the above selector is selected. On the other hand, a selection signal for switching connection corresponding to the EPROM is given from the CPU, and the CPU sequentially reads the data of the first address and the second address, and the data read from the first address and the second address. If the data read from the device does not match, the attached device switches and connects. Determined to be response to the determining means determines that the device is not mounted when the match.

[0009]

According to the first aspect of the invention, even if a wrong device is attached, it can be detected.
Even if the EEPROM is mistakenly mounted in the state where the switching connection corresponding to the PROM is made, it is possible to rewrite the stored content of the EEPROM to the original correct content by changing the switching connection after the detection. Memory contents are not destroyed.

According to the second aspect of the present invention, it is possible to automatically detect whether the mounted device is the EEPROM or the EPROM, and the switching connection according to the device is automatically performed. The system can be constructed without being aware of the device to be mounted, and since it is not necessary to switch the switch manually, there is no trouble that the switch connection is erroneously made during operation to cause a malfunction.

[0011]

EXAMPLES The present invention will be described below with reference to examples. (Embodiment 1) The constitution of this embodiment is the same as that of the conventional example shown in FIG. 2, but data other than FF _(H) is written in advance to the address of 4000 _(H) of the 256 Kibit EEPROM and EPROM to be used. _(H) above 4000
Write data different from the data written in _(H) .
In other words, pay attention to the address A ₁₄ where the connection pin of the IC socket (A) differs depending on the device, and its logical value is "
4000 _(H) which is the address that becomes 1 ”(“ H ”),
0, which is the address whose logical value is "0"("L")
Different data is written to 000 _(H) .

Then, the CPU (C) performs the read determination as shown in FIG. 1 to detect the mounted device. That is, when the device detection flow shown in the drawing is started, the CPU (C) first reads the data X from the address of 4000 _(H) , then reads the data Y from the address of 0000 _(H) , and again the address of 4000 _(H) . The data Z is read from and it is judged whether the data X read first and the data Z read again are the same. If they are different, it is judged that the contents were rewritten when the data was read from the address of 0000 _(H). And data X
Is stored as write-back data and EPROM
When it is determined that the EEPROM has been mounted, the error is notified. When this error notification is issued, the user resets the changeover switch (SW ₁ ) (SW ₂ ) to the EEPROM side.

On the other hand, when the data X and the data Z match, it is judged whether or not the data X and the data Y are not equal. If they match, the EEPROM is set by E.
The PROM is installed, the address A ₁₄ is connected to the control line MWR of the CPU (C) and is "H"("1"), and even when the data at the address of 0000 _(H) is called, it is actually The data X at the address of 4000 _(H) is read out, and the above judgment result coincides. Therefore, in this case, the CPU (C) gives an error notification. In this case, the user may reset the switching setting of the changeover switches (SW ₁ ) (SW ₂ ) according to the mounting device.

If the read data X and Y do not match after the above processing, it is further judged whether or not the write-back data X is stored, and if not, the final result is obtained. It is determined that the setting and the attached device match. If the write-back data X is stored, it is determined that an error was detected in the previous device detection and the EEPROM is installed with the correct switching setting this time, and the stored write-back data X is stored. 4000
_The data is corrected by writing to the address _(H) .

(Second Embodiment) The first embodiment has the same hardware configuration as that of the conventional example, and a device detection flow program of the CPU (C) is set to perform device detection by software. However, in this embodiment, instead of the changeover switches (SW ₁ ) and (SW ₂ ), the selection signal SEL is output from the CPU (C) as shown in FIG. A selector (SC) having two pairs of 2-input 1-output selector circuits capable of switching the connection between the terminals and the input terminals is provided, and the CPU (C) executes the device detection flow shown in FIG. In addition, the device used and 40 of that device
Data to be written at the address of 00 _(H) and 0000 _{(H )}
The data to be written to the address is in accordance with the first embodiment.

First, the CPU (C) gives the selection signal SEL of "L" to the selector (SC) to set the EEPROM. In this case, the B ₁ and B ₂ inputs of the selector (SC) are connected to the Y ₁ and Y ₂ outputs. 4000 _(H) here
Read data X from the address of
Data Y is read from the address of _(H) and both data X,
It is determined whether or not Y matches, and if they do not match, it is determined that the EEPROM is mounted. If they do not match, C
PU (C) switches the selection signal SEL to "H". In this case, the A ₁ and A ₂ inputs of the selector (SC) are connected to the Y ₁ and Y ₂ outputs. Here, the data X is read from the address of 4000 _(H), the data Y is read from the address of 0000 _{(H )} , and it is determined whether or not both the data X and Y match. If they do not match, EPROM mounting If not, it is determined that the device is not attached.

[0017]

According to the invention described in claim 1, even if a wrong device is attached, it can be detected.
Even if the EEPROM is mistakenly installed while the switching connection corresponding to the ROM is made, by changing the switching connection after detection, the stored content of the EEPROM can be rewritten to the original correct content. There is an effect that a highly reliable system can be constructed without the memory contents being destroyed.

According to the second aspect of the present invention, it is possible to automatically detect whether the mounted device is the EEPROM or the EPROM, and the switching connection according to the device is automatically performed. The system can be constructed without the user's awareness, and since it is not necessary to switch the switch manually, the trouble of accidentally connecting the switch during operation and causing a malfunction does not occur, and reliability is improved. The effect is that a high-quality system can be constructed.

[Brief description of drawings]

FIG. 1 is an operation flowchart of an embodiment of the invention described in claim 1.

FIG. 2 is a circuit configuration diagram of an embodiment of the invention according to claim 2;

FIG. 3 is an operation flowchart of an embodiment of the invention described in claim 3;

FIG. 4 is a circuit configuration diagram applied to a conventional example and an embodiment of the invention described in claim 1;

FIG. 5 is a timing chart for explaining the operation of the conventional example.

Claims (2)

[Claims] 1. An EPRO having the same storage capacity and the same number of pins.
A terminal to which a read / write control signal is connected corresponds to the address terminal corresponding to the most significant bit of the M address terminals, and the terminal of the most significant bit of the address terminals is the EPR.
An EEPROM in which the remaining address terminals are in the same position as the remaining address terminals of the EPROM and the data terminals are also in the same position corresponding to terminals other than the address terminals of the OM, and the above EPROM are exchangeably mounted in the same IC socket. ,
EEPROM used in a system that switches the connection between the CPU and the IC socket according to the mounting device
And writing predetermined data to a first address represented by a binary number of a predetermined number of bits in which the logical value of the most significant bit of the EPROM is “1” and the logical value of the remaining bits is “0”, Data different from the above data is written in advance to the second address represented by the binary number of the predetermined number of bits in which the logical values of all the bits are "0", and one of these EEPROM or EPROM devices I
The CPU sequentially reads the data of the first address, the second address, and the first address while being mounted in the C socket, and first reads the data read from the first address and the second address from the first address. If the read data does not match, the data read from the first address is stored as write-back data and the EPR is performed.
It is determined that the EEPROM is mounted for the switching connection to the OM, the data read from the first address at the first time matches the data read from the first address at the second time, and the first address is read first. If the data read from the data and the data read from the second address match, it is determined that the EPROM is mounted for the switching connection to the EEPROM, and the first
Connection when the data read from the address of No. 2 and the data read from the first address for the second time match and the data read from the first address first and the data read from the second address do not match. It is determined that the correct device is installed for switching, and if the write-back data is stored, the installed EE
An EEPROM / EPROM detection method characterized by writing write-back data to PROM. 2. An EPRO having the same storage capacity and the same number of pins.
A terminal to which a read / write control signal is connected corresponds to the address terminal corresponding to the most significant bit of the M address terminals, and the terminal of the most significant bit of the address terminals is the EPR.
An EEPROM in which the remaining address terminals are in the same position as the remaining address terminals of the EPROM and the data terminals are also in the same position corresponding to terminals other than the address terminals of the OM, and the above EPROM are exchangeably mounted in the same IC socket. ,
It is used in a system that switches the connection between the CPU and the IC socket according to the mounting device.
An EEPROM that uses a selector that uses a selection signal from the CPU to switch the connection between the PU and the IC socket
Then, predetermined data is written in advance to the first address in which the logical value of the most significant bit of the EPROM is "1" and the logical value of the remaining bits is "0", and the logical values of all bits are "0". In advance, data different from the above data is written to the second address, and a selection signal for performing switching connection corresponding to the EEPROM is first sent to the selector in a state where any of these EEPROM or EPROM is mounted. In addition to being given by the CPU, the CPU sequentially reads the data at the first address and the second address, and reads the data read from the first address and the second data.
If the data read from the address does not match, it is determined that the mounting device is compatible with the switching connection, and if they match, the CPU gives the selector a selection signal for performing the switching connection corresponding to the EPROM. At the same time, the CPU sequentially reads the data at the first address and the data at the second address, and if the data read from the first address and the data read from the second address do not match, the mounting device switches and connects. An EEPROM / EPROM detection method characterized in that it is determined that they correspond, and if they match, it is determined that the device is not attached.