JPS6349382B2 - - Google Patents
Info
- Publication number
- JPS6349382B2 JPS6349382B2 JP58042890A JP4289083A JPS6349382B2 JP S6349382 B2 JPS6349382 B2 JP S6349382B2 JP 58042890 A JP58042890 A JP 58042890A JP 4289083 A JP4289083 A JP 4289083A JP S6349382 B2 JPS6349382 B2 JP S6349382B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- plating
- lead frame
- alloy
- properties
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/85464—Palladium (Pd) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58042890A JPS59168659A (ja) | 1983-03-15 | 1983-03-15 | 集積回路用リ−ドフレ−ム |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58042890A JPS59168659A (ja) | 1983-03-15 | 1983-03-15 | 集積回路用リ−ドフレ−ム |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59168659A JPS59168659A (ja) | 1984-09-22 |
JPS6349382B2 true JPS6349382B2 (enrdf_load_stackoverflow) | 1988-10-04 |
Family
ID=12648623
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58042890A Granted JPS59168659A (ja) | 1983-03-15 | 1983-03-15 | 集積回路用リ−ドフレ−ム |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59168659A (enrdf_load_stackoverflow) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005057067A (ja) * | 2003-08-05 | 2005-03-03 | Renesas Technology Corp | 半導体装置およびその製造方法 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0250146A1 (en) * | 1986-06-16 | 1987-12-23 | Texas Instruments Incorporated | Palladium plated lead frame for integrated circuit |
EP0335608B1 (en) * | 1988-03-28 | 1995-06-14 | Texas Instruments Incorporated | Lead frame with reduced corrosion |
JP2570911B2 (ja) * | 1990-02-26 | 1997-01-16 | 株式会社日立製作所 | 半導体パッケージ及びそれに用いるリードフレーム |
DE4431847C5 (de) * | 1994-09-07 | 2011-01-27 | Atotech Deutschland Gmbh | Substrat mit bondfähiger Beschichtung |
US5675177A (en) * | 1995-06-26 | 1997-10-07 | Lucent Technologies Inc. | Ultra-thin noble metal coatings for electronic packaging |
US6521358B1 (en) * | 1997-03-04 | 2003-02-18 | Matsushita Electric Industrial Co., Ltd. | Lead frame for semiconductor device and method of producing same |
JP4217925B2 (ja) | 1997-10-24 | 2009-02-04 | ソニー株式会社 | 平面型レンズの製造方法 |
JPH11204713A (ja) * | 1998-01-09 | 1999-07-30 | Sony Corp | 半導体装置用リードフレーム及び半導体装置 |
JP4543460B2 (ja) * | 1999-11-22 | 2010-09-15 | 住友ベークライト株式会社 | 導電性樹脂ペースト及びこれを用いた半導体装置 |
KR100819800B1 (ko) | 2005-04-15 | 2008-04-07 | 삼성테크윈 주식회사 | 반도체 패키지용 리드 프레임 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5219076A (en) * | 1975-08-05 | 1977-01-14 | Fujitsu Ltd | Production method of semiconductor package |
-
1983
- 1983-03-15 JP JP58042890A patent/JPS59168659A/ja active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005057067A (ja) * | 2003-08-05 | 2005-03-03 | Renesas Technology Corp | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JPS59168659A (ja) | 1984-09-22 |
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