JPS6336533B2 - - Google Patents

Info

Publication number
JPS6336533B2
JPS6336533B2 JP58212008A JP21200883A JPS6336533B2 JP S6336533 B2 JPS6336533 B2 JP S6336533B2 JP 58212008 A JP58212008 A JP 58212008A JP 21200883 A JP21200883 A JP 21200883A JP S6336533 B2 JPS6336533 B2 JP S6336533B2
Authority
JP
Japan
Prior art keywords
bus
bus module
master
slave
microprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58212008A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60105057A (ja
Inventor
Hidefusa Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58212008A priority Critical patent/JPS60105057A/ja
Publication of JPS60105057A publication Critical patent/JPS60105057A/ja
Publication of JPS6336533B2 publication Critical patent/JPS6336533B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP58212008A 1983-11-11 1983-11-11 試験方式 Granted JPS60105057A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58212008A JPS60105057A (ja) 1983-11-11 1983-11-11 試験方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58212008A JPS60105057A (ja) 1983-11-11 1983-11-11 試験方式

Publications (2)

Publication Number Publication Date
JPS60105057A JPS60105057A (ja) 1985-06-10
JPS6336533B2 true JPS6336533B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1988-07-20

Family

ID=16615353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58212008A Granted JPS60105057A (ja) 1983-11-11 1983-11-11 試験方式

Country Status (1)

Country Link
JP (1) JPS60105057A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4311883A1 (de) * 1993-04-10 1994-10-13 Tehalit Gmbh EIB-Modul

Also Published As

Publication number Publication date
JPS60105057A (ja) 1985-06-10

Similar Documents

Publication Publication Date Title
US4684885A (en) Arrangement for on-line diagnostic testing of an off-line standby processor in a duplicated processor configuration
US4979108A (en) Task synchronization arrangement and method for remote duplex processors
US5754865A (en) Logical address bus architecture for multiple processor systems
JPS6336533B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH0793236A (ja) バス制御装置
JPS60194647A (ja) デ−タ伝送システム
JPH0675887A (ja) ポーリング間隔決定方式
JP2002032326A (ja) 拡張スロットホットプラグ制御装置
RU2665225C1 (ru) Блок обработки информации
JPS608966A (ja) シリアルインタフエイス制御装置
JPH0318958A (ja) マルチプロセッサシステム
GB2146810A (en) Achieving redundancy in a distributed process control system
JPH03246743A (ja) プロセッサ間通信方式
JPS63310031A (ja) エラ−検出方式
JPS6270958A (ja) 入出力処理装置の試験方式
JPS60246149A (ja) デ−タ伝送装置
JPH023858A (ja) 二重化データ処理装置構成方式
JPH0240755A (ja) データ処理装置
JPS63194445A (ja) マルチポイント通信方式
JPS59135566A (ja) プロセツサ間通信方式
JPH04100168A (ja) マルチプロセッサシステム
JPS636652A (ja) 情報処理システム
JPS61204757A (ja) プロセツサ間通信方式
JPS63163949A (ja) マルチプロセツサシステム
JPS63296428A (ja) 入出力バス制御方式