JPS6335109B2 - - Google Patents
Info
- Publication number
- JPS6335109B2 JPS6335109B2 JP56072502A JP7250281A JPS6335109B2 JP S6335109 B2 JPS6335109 B2 JP S6335109B2 JP 56072502 A JP56072502 A JP 56072502A JP 7250281 A JP7250281 A JP 7250281A JP S6335109 B2 JPS6335109 B2 JP S6335109B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- polysilicon film
- silicon
- polysilicon
- barrier diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 43
- 229920005591 polysilicon Polymers 0.000 claims description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 30
- 229910021332 silicide Inorganic materials 0.000 claims description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 18
- 235000012239 silicon dioxide Nutrition 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims 1
- 238000002844 melting Methods 0.000 description 5
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910021339 platinum silicide Inorganic materials 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- -1 arsenic ions Chemical class 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 206010024769 Local reaction Diseases 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0761—Vertical bipolar transistor in combination with diodes only
- H01L27/0766—Vertical bipolar transistor in combination with diodes only with Schottky diodes only
Description
【発明の詳細な説明】
本発明はシヨツトキーバリアダイオード（以下
SBDと略記する）クランプ付きバイポーラトラ
ンジスタの製造方法に係り、特に高い歩留りと信
頼性にて高速動作を実現する事の出来る半導体装
置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Schottky barrier diode (hereinafter referred to as
The present invention relates to a method of manufacturing a clamped bipolar transistor (abbreviated as SBD), and particularly to a method of manufacturing a semiconductor device that can realize high-speed operation with high yield and reliability.
バイポーラトランジスタにおいて高速動作を実
現する為にポリシリコン膜にＮ型不純物を含ませ
て熱処理を行ない、浅いエミツタ接合を形成する
事が行なわれている。またさらに、SBDクラン
プ付きの構成にして高速化が計られている。この
SBDは通常高融点金属のシリサイド膜、例えば
白金シリサイド，パラジウムシリサイド等が用い
られる。このシリサイド膜はエミツタ上のポリシ
リコン膜の上にも同時に形成されると不都合を生
じる。すなわちポリシリコン膜上に形成されるシ
リサイド膜は高融点金属がポリシリコン膜の厚さ
全部と反応し、さらに単結晶シリコン表面に形成
されているエミツタ領域表面と不所望に反応して
しまう。これにより浅いエミツタ接合がシリサイ
ド膜により破壊されてしまう恐れを生じる。この
為、SBDの特性上必要な高融点金属の膜厚が決
まると、ポリシリコン膜上ではこの金属膜厚の約
２倍の厚さのポリシリコンが反応してシリサイド
膜になる為、シリサイド化しない部分の厚さをあ
る程度見込み、通常ポリシリコンの膜厚は前記金
属膜の約３倍程度の厚さで設けられる。しかし、
ポリシリコン高融点金属との反応はポリシリコン
の粒界に沿つて進行し易すい為局所的に深くシリ
サイド膜が形成される事が起こる。この為に、ポ
リシリコンの膜厚は前記の厚さよりさらに余裕を
見て厚くする必要があつた。この様に、ポリシリ
コン膜が厚くなるとエミツタ抵抗が高くなり、ト
ランジスタの高速化には不利となる。さらに電極
部に形成される大きな段差は微細パターニング及
び多層配線構造を進める場合に重大な欠点となり
易すい。 In order to achieve high-speed operation in bipolar transistors, a shallow emitter junction is formed by impregnating a polysilicon film with N-type impurities and subjecting it to heat treatment. Additionally, the configuration is equipped with an SBD clamp to increase speed. this
A silicide film of a high melting point metal, such as platinum silicide or palladium silicide, is usually used for SBD. If this silicide film is simultaneously formed on the polysilicon film on the emitter, a problem will arise. That is, in the silicide film formed on the polysilicon film, the high melting point metal reacts with the entire thickness of the polysilicon film, and further reacts undesirably with the surface of the emitter region formed on the surface of the single crystal silicon. This may cause the shallow emitter junction to be destroyed by the silicide film. For this reason, once the film thickness of the high-melting point metal required for SBD characteristics is determined, on the polysilicon film, polysilicon with a thickness approximately twice that of this metal film will react and become a silicide film, resulting in silicide formation. To some extent, the thickness of the non-metallic film is taken into consideration, and the polysilicon film is usually provided to be about three times as thick as the metal film. but,
Since the reaction between polysilicon and the high melting point metal tends to proceed along the grain boundaries of polysilicon, a locally deep silicide film may be formed. For this reason, it was necessary to make the polysilicon film thicker than the above-mentioned thickness with some margin. As described above, when the polysilicon film becomes thicker, the emitter resistance increases, which is disadvantageous for increasing the speed of the transistor. Furthermore, the large step difference formed in the electrode portion tends to become a serious drawback when proceeding with fine patterning and multilayer wiring structures.
本発明の目的は上述の従来の製造方法の欠点を
除去し、かつ自己整合等の技術を用い高い歩留で
かつ高信頼性の高速動作を実現する事のできる
SBDクランプ付きバイポーラトランジスタのも
つとも好ましい製造方法を提供する事にある。 The purpose of the present invention is to eliminate the drawbacks of the conventional manufacturing method described above, and to realize high-speed operation with high yield and high reliability using techniques such as self-alignment.
The object of the present invention is to provide a particularly preferable manufacturing method for a bipolar transistor with an SBD clamp.
本発明の特徴は、シヨツトキーバリアダイオー
ドクランプ付きのバイポーラトランジスタを有す
る半導体装置の製造方法において、窒化シリコン
膜を用いてシヨツトキーバリアダイオード部、エ
ミツタコンタクト部およびコレクタコンタクト部
以外のシリコン表面に酸化処理により二酸化シリ
コン膜を形成する工程と、シヨツトキーバリアダ
イオード部のみの窒化シリコン膜を残して、エミ
ツタコンタクト、コレクタコンタクト部の開口を
行う工程と、ポリシリコン膜を被着する工程と、
少なくともエミツタコンタクト部を覆い、かつシ
ヨツトキーバリアダイオード部上を除去する様に
ポリシリコン膜をパターニングする工程と、不純
物を該パターニングされたポリシリコン膜にイオ
ン注入する工程と、酸化性雰囲気中で熱処理を行
ない前記ポリシリコン膜中の不純物を半導体基板
中に導入することによりエミツタ領域を形成する
と同時に該パターニングされたポリシリコン膜の
上面および側面に熱酸化二酸化シリコン膜を形成
する工程と、シヨツトキーバリアダイオード部の
窒化シリコン膜を自己整合的に除去して開口する
工程と、金属膜を被着する工程と、熱処理を行な
い、自己整合的に前記開口部のみに金属シリサイ
ド膜を形成する工程と、前記ポリシリコン膜の上
面および側面上に形成された熱酸化二酸化シリコ
ン膜を除去する工程と、前記金属シリサイド膜と
電極金属膜との反応を防止する介在膜を被着する
工程と電極金属膜を被着する工程と、前記電極金
属膜、介在膜及びポリシリコン膜を連続的にパタ
ーニングする工程とを含む半導体装置の製造方法
にある。上記方法によればパターニングされたポ
リシリコンの側面にも熱酸化シリコン膜を設けた
状態でシヨツトキーバリアダイオード形成用の金
属膜を被着するから、側面からの反応も完全に阻
止されエミツタの上記不都合は皆無となる。又、
その他の諸工程は自己整合をとり入れているから
容易の製造を可能とする。 A feature of the present invention is that in a method of manufacturing a semiconductor device having a bipolar transistor with a shot key barrier diode clamp, a silicon nitride film is used to remove the silicon surface other than the shot key barrier diode portion, the emitter contact portion, and the collector contact portion. a step of forming a silicon dioxide film by oxidation treatment, a step of leaving the silicon nitride film only in the shot key barrier diode region and opening the emitter contact and collector contact regions, and a step of depositing a polysilicon film. and,
A process of patterning a polysilicon film so as to cover at least the emitter contact part and removing the top of the shot key barrier diode part, a process of ion-implanting impurities into the patterned polysilicon film, and a process of injecting impurities into the patterned polysilicon film in an oxidizing atmosphere. a step of forming an emitter region by performing heat treatment to introduce impurities in the polysilicon film into the semiconductor substrate, and at the same time forming a thermally oxidized silicon dioxide film on the top and side surfaces of the patterned polysilicon film; A process of removing the silicon nitride film in the Yotsuki barrier diode portion in a self-aligned manner to create an opening, a process of depositing a metal film, and heat treatment are performed to form a metal silicide film only in the opening in a self-aligned manner. a step of removing a thermally oxidized silicon dioxide film formed on the top and side surfaces of the polysilicon film; a step of depositing an intervening film to prevent reaction between the metal silicide film and the electrode metal film; and an electrode. A method of manufacturing a semiconductor device includes a step of depositing a metal film, and a step of successively patterning the electrode metal film, intervening film, and polysilicon film. According to the above method, a metal film for forming a shot key barrier diode is deposited with a thermally oxidized silicon film also provided on the side surfaces of the patterned polysilicon, so reactions from the side surfaces are also completely blocked and emitter All of the above inconveniences will disappear. or,
Other processes incorporate self-alignment, allowing for easy manufacturing.
以下図面を用いて詳細に説明する。 This will be explained in detail below using the drawings.
第１図は従来の製造方法の一例によるSBDク
ランプ付きバイポーラトランジスタのエミツタコ
ンタクト部及びSBD部分を説明する為の図であ
る。Ｎ型シリコン領域１の表面にＰ型ベース領域
２が設けられた後表面の二酸化シリコン膜にエミ
ツタコンタクトの開口が設けられ、エミツタ部分
の位置決めが行なわれる。次にポリシリコン膜５
が被着され、砒素のイオン注入を行い、熱処理工
程を経てエミツタ領域３が形成される。次に
SBDコンタクト部分の開口部をフオトレジスト
をマスクにしてポリシリコン膜、二酸化シリコン
膜の除去を行う事により設ける。次に、高融点金
属膜を被着し、熱処理を行う事により金属シリサ
イド膜６をSBD部分及びエミツタ上のポリシリ
膜の上に形成する。次に電極金属８とシリサイド
６との反応を防止する為の介在膜７を被着しさら
にその上に電極金属膜８を被着する。次に配線用
のフオトレジストのパターニングを行い、電極金
属８介在膜７シリサイド膜６及びエミツタ上のポ
リシリコン膜５を連続的に除去し配線を形成す
る。 FIG. 1 is a diagram for explaining an emitter contact portion and an SBD portion of a bipolar transistor with an SBD clamp according to an example of a conventional manufacturing method. After a P-type base region 2 is provided on the surface of the N-type silicon region 1, an emitter contact opening is provided in the silicon dioxide film on the surface, and the emitter portion is positioned. Next, polysilicon film 5
is deposited, arsenic ions are implanted, and an emitter region 3 is formed through a heat treatment process. next
An opening for the SBD contact portion is provided by removing the polysilicon film and silicon dioxide film using a photoresist as a mask. Next, a metal silicide film 6 is formed on the SBD portion and the polysilicon film on the emitter by depositing a high melting point metal film and performing heat treatment. Next, an intervening film 7 for preventing a reaction between the electrode metal 8 and the silicide 6 is deposited, and then an electrode metal film 8 is deposited thereon. Next, a photoresist for wiring is patterned, and the electrode metal 8 intervening film 7 silicide film 6 and polysilicon film 5 on the emitter are successively removed to form wiring.
この様な従来の製造方法によると、第１図に示
す様にエミツタ３の上のポリシリコン膜５の表面
に形成される金属シリサイド膜６は局所的に反応
が進行してエミツタ接合にまで達する事が起り易
すい。 According to this conventional manufacturing method, as shown in FIG. 1, the metal silicide film 6 formed on the surface of the polysilicon film 5 on the emitter 3 undergoes a local reaction and reaches the emitter junction. Things tend to happen.
次に、本発明を一実施例に基き、第２図乃至第
７図を用いて説明する。 Next, the present invention will be explained based on one embodiment using FIGS. 2 to 7.
第２図においてＰ型シリコン基板１１の主面に
選択的にN+型埋込みコレクタ領域１２が設けら
れた後Ｎ型シリコンエピタキシヤル層１３が形成
される。次にエピタキシヤル層表面に500Å程度
の二酸化シリコン膜が形成された後窒化シリコン
膜が被着される。以下簡単の為にこの薄い二酸化
シリコン膜と窒化シリコン膜を単に窒化シリコン
膜１５と呼ぶ。次に絶縁分離領域を形成する為に
前記窒化シリコン膜１５のパターニングを行つた
後エピタキシヤル層のシリコンを除去して溝を設
け、ボロンを拡散した後シリコンの酸化を行い絶
縁分離領域の二酸化シリコン膜１６を形成する。
次にフオトレジスト１８のパターニングを行いベ
ース領域１９をボロンのイオン注入により形成す
る。 In FIG. 2, an N + type buried collector region 12 is selectively provided on the main surface of a P type silicon substrate 11, and then an N type silicon epitaxial layer 13 is formed. Next, a silicon dioxide film of about 500 Å is formed on the surface of the epitaxial layer, and then a silicon nitride film is deposited. Hereinafter, for the sake of simplicity, the thin silicon dioxide film and silicon nitride film will be simply referred to as the silicon nitride film 15. Next, the silicon nitride film 15 is patterned to form an insulating isolation region, the silicon of the epitaxial layer is removed to form a groove, boron is diffused, and the silicon is oxidized to form silicon dioxide in the insulating isolation region. A film 16 is formed.
Next, the photoresist 18 is patterned and a base region 19 is formed by boron ion implantation.
次に第３図において、SBD部分、エミツタコ
ンタクト部分、及びコレクタコンタクト部分とな
る領域の窒化シリコン膜１５を残す様にパターニ
ングを行つた後酸化処理を行つて表面保護二酸化
シリコン膜１６′を形成する。 Next, in FIG. 3, patterning is performed to leave the silicon nitride film 15 in the areas that will become the SBD part, emitter contact part, and collector contact part, and then oxidation treatment is performed to form a surface protective silicon dioxide film 16'. do.
次に第４図において、コレクタコンタクト部の
窒化シリコン膜を除去し、リンを拡散させる事に
よりコレクタ領域２０を形成する。この時コレク
タ領域２０の表面には薄い二酸化シリコン膜が形
成される様にする。 Next, in FIG. 4, a collector region 20 is formed by removing the silicon nitride film at the collector contact portion and diffusing phosphorus. At this time, a thin silicon dioxide film is formed on the surface of the collector region 20.
次に第５図においてエミツタコンタクト部の窒
化シリコン膜及びコレクタコンタクト部の薄い二
酸化シリコン膜を除去した後ポリシリコン膜２１
を被着した後エミツタコンタクトとコレクタコン
タクト部分を覆う様にポリシリコン膜２１が残る
様にパターニングを行つた後砒素をイオン注入す
る。この時砒素がSBD部分及び、ポリシリコン
のパターン以外の単結晶シリコン側に浸入しない
様にイオン注入されねばならないのは当然であ
る。この後、窒素と酸素の混合雰囲気中で熱処理
を行う事によりエミツタ領域２３を形成すると同
時にポリシリコン膜の表面に二酸化シリコン膜２
２が形成される。 Next, in FIG. 5, after removing the silicon nitride film in the emitter contact area and the thin silicon dioxide film in the collector contact area, the polysilicon film 21 is removed.
After depositing the polysilicon film 21, patterning is performed so that a polysilicon film 21 remains so as to cover the emitter contact and collector contact portions, and then arsenic ions are implanted. At this time, it is natural that ions must be implanted to prevent arsenic from penetrating into the SBD portion and the single crystal silicon side other than the polysilicon pattern. Thereafter, an emitter region 23 is formed by heat treatment in a mixed atmosphere of nitrogen and oxygen, and at the same time a silicon dioxide film 2 is formed on the surface of the polysilicon film.
2 is formed.
次に第６図において自己整合的にSBD部分の
窒化シリコン膜１５を除去した後白金を被着し、
熱処理を行う事により白金シリサイド膜２４を形
成する。この時SBD部分以外は表面が全て二酸
化シリコン膜である為白金シリサイドはSBD部
分のみに形成される。SBD部分以外の白金を王
水で除去した後、ポリシリコン膜上の二酸化シリ
コン膜２２を除去する。 Next, in FIG. 6, after removing the silicon nitride film 15 in the SBD portion in a self-aligned manner, platinum is deposited.
A platinum silicide film 24 is formed by heat treatment. At this time, since the entire surface other than the SBD portion is a silicon dioxide film, platinum silicide is formed only on the SBD portion. After removing platinum other than the SBD portion with aqua regia, the silicon dioxide film 22 on the polysilicon film is removed.
次に第７図において、チタンとタングステンか
ら成る金属膜２５を被着した後さらにアルミニウ
ム膜２６を被着する。 Next, in FIG. 7, after a metal film 25 made of titanium and tungsten is deposited, an aluminum film 26 is further deposited.
次に配線用のパターニングを行い、アルミニウ
ム膜、チタンとタングステンから成る金属膜、及
びエミツタ上のポリシリコン膜を連続的にエツチ
ングし、配線を形成する。 Next, patterning for wiring is performed, and the aluminum film, the metal film made of titanium and tungsten, and the polysilicon film on the emitter are successively etched to form wiring.
この様に、本発明の技術によれば、金属シリサ
イドはSBD部分にのみ形成される為、エミツタ
上のポリシリコンを充分に薄くする事が出来エミ
ツタ抵抗が小さく、かつエミツタ接合のリークや
破壊の恐れのない高速動作を実現する事の出来る
SBDクランプ付きバイポーラトランジスタを高
い信頼性でかつ高い歩留りで得る事が出来、、電
極部分の段差が小さい為に微細パターン化や多層
配線構造にも極めて有利である事が判る。 As described above, according to the technology of the present invention, since metal silicide is formed only in the SBD portion, the polysilicon on the emitter can be made sufficiently thin, the emitter resistance is small, and the emitter junction is prevented from leaking or breaking. Able to realize fearless high-speed operation
It is possible to obtain bipolar transistors with SBD clamps with high reliability and high yield, and because the step difference in the electrode portion is small, it is found that it is extremely advantageous for fine patterning and multilayer wiring structures.
第１図は従来の技術を説明する為の図、第２図
乃至第７図は本発明の実施例を工程順に説明する
為の図である。
なお図において、１……Ｎ型シリコン領域、２
……Ｐ型ベース領域、３……N+型エミツタ領域、
４……表面保護二酸化シリコン膜、５……ポリシ
リコン膜、６……金属シリサイド膜、７……介在
膜、８……電極金属膜、１１……Ｐ型シリコン基
板、１２……N+型埋込みコレクタ領域、１３…
…Ｎ型エピタキシヤル層、１４，１７……チヤン
ネル防止領域、１５……窒化シリコン膜、１６…
…絶縁分離領域、１６′……表面保護二酸化シリ
コン膜、１８……フオトレジスト膜、１９……Ｐ
型ベース領域、２０……コレクタ領域、２１……
ポリシリコン膜、２２……二酸化シリコン膜、２
３……N+型エミツタ領域、２４……白金シリサ
イド膜、２５……チタンとタングステンから成る
膜、２６……電極アルミニウム膜、である。
FIG. 1 is a diagram for explaining a conventional technique, and FIGS. 2 to 7 are diagrams for explaining an embodiment of the present invention in the order of steps. In the figure, 1...N-type silicon region, 2
...P type base region, 3...N + type emitter region,
4... Surface protection silicon dioxide film, 5... Polysilicon film, 6... Metal silicide film, 7... Intervening film, 8... Electrode metal film, 11... P type silicon substrate, 12... N + type Embedded collector area, 13...
...N-type epitaxial layer, 14, 17...Channel prevention region, 15...Silicon nitride film, 16...
...Insulating isolation region, 16'...Surface protection silicon dioxide film, 18...Photoresist film, 19...P
Type base area, 20... Collector area, 21...
Polysilicon film, 22...Silicon dioxide film, 2
3... N + type emitter region, 24... platinum silicide film, 25... film made of titanium and tungsten, 26... electrode aluminum film.
Claims (1)
のバイポーラトランジスタを有する半導体装置の
製造方法において、窒化シリコン膜を用いてシヨ
ツトキーバリアダイオード部、エミツタコンタク
ト部およびコレクタコンタクト部以外のシリコン
表面に酸化処理により二酸化シリコン膜を形成す
る工程と、シヨツトキーバリアダイオード部のみ
の窒化シリコン膜を残して、エミツタコンタク
ト、コレクタコンタクト部の開口を行う工程と、
ポリシリコン膜を被着する工程と、少なくともエ
ミツタコンタクト部を覆いかつシヨツトキーバリ
アダイオード部上を除去する様にポリシリコン膜
をパターニングする工程と、不純物を該パターニ
ングされたポリシリコン膜にイオン注入する工程
と、酸化性雰囲気中で熱処理を行ない前記ポリシ
リコン膜中の不純物を半導体基板中に導入するこ
とによりエミツタ領域を形成すると同時に該パタ
ーニングされたポリシリコン膜の上面および側面
に熱酸化二酸化シリコン膜を形成する工程と、シ
ヨツトキーバリアダイオード部の窒化シリコン膜
を自己整合的に除去して開口する工程と、金属膜
を被着する工程と、熱処理を行ない、自己整合的
に前記開口部のみに金属シリサイド膜を形成する
工程と、前記ポリシリコン膜の上面および側面上
に形成された熱酸化二酸化シリコン膜を除去する
工程と、前記金属シリサイド膜と電極金属膜との
反応を防止する介在膜を被着する工程と電極金属
膜を被着する工程と、前記電極金属膜、介在膜及
びポリシリコン膜を連続的にパターニングする工
程とを含む事を特徴とする半導体装置の製造方
法。1 In a method for manufacturing a semiconductor device having a bipolar transistor with a shot key barrier diode clamp, a silicon nitride film is used to oxidize the silicon surface other than the shot key barrier diode portion, emitter contact portion, and collector contact portion by oxidation treatment. a step of forming a silicon film, and a step of opening the emitter contact and collector contact portions while leaving the silicon nitride film only in the shot key barrier diode portion;
A process of depositing a polysilicon film, a process of patterning the polysilicon film so as to cover at least the emitter contact part and removing the top of the shot key barrier diode part, and a process of ionizing impurities into the patterned polysilicon film. The impurities in the polysilicon film are introduced into the semiconductor substrate through the implantation process and heat treatment in an oxidizing atmosphere to form an emitter region, and at the same time thermal oxidation dioxide is applied to the top and side surfaces of the patterned polysilicon film. A step of forming a silicon film, a step of removing the silicon nitride film in the Schottky barrier diode portion in a self-aligned manner to form an opening, a step of depositing a metal film, and a heat treatment are performed to form the opening in a self-aligned manner. a step of forming a metal silicide film only on the polysilicon film; a step of removing the thermally oxidized silicon dioxide film formed on the top and side surfaces of the polysilicon film; and preventing a reaction between the metal silicide film and the electrode metal film. A method for manufacturing a semiconductor device, comprising the steps of depositing an intervening film, depositing an electrode metal film, and successively patterning the electrode metal film, the intervening film, and the polysilicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7250281A JPS57187963A (en) | 1981-05-14 | 1981-05-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7250281A JPS57187963A (en) | 1981-05-14 | 1981-05-14 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57187963A JPS57187963A (en) | 1982-11-18 |
| JPS6335109B2 true JPS6335109B2 (en) | 1988-07-13 |
Family
ID=13491171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7250281A Granted JPS57187963A (en) | 1981-05-14 | 1981-05-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57187963A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59111375A (en) * | 1982-12-08 | 1984-06-27 | エヌ・ベ−・フイリップス・フル−イランペンファブリケン | Semiconductor device and method of producing same |
| JPS59121872A (en) * | 1982-12-15 | 1984-07-14 | Fujitsu Ltd | Semiconductor device |
| US4512076A (en) * | 1982-12-20 | 1985-04-23 | Raytheon Company | Semiconductor device fabrication process |
| JPS63257269A (en) * | 1987-04-14 | 1988-10-25 | Fujitsu Ltd | Formation of contact in semiconductor device |
| JP2793207B2 (en) * | 1988-11-04 | 1998-09-03 | 株式会社日立製作所 | Method for manufacturing semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5177076A (en) * | 1974-12-27 | 1976-07-03 | Fujitsu Ltd | HANDOTAISOCHINOSEIZOHOHO |
-
1981
- 1981-05-14 JP JP7250281A patent/JPS57187963A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5177076A (en) * | 1974-12-27 | 1976-07-03 | Fujitsu Ltd | HANDOTAISOCHINOSEIZOHOHO |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57187963A (en) | 1982-11-18 |
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