JPS59111375A - Semiconductor device and method of producing same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

The present invention includes a semiconductor body having an N-type semiconductor region, a metal silicide layer adjacent to the N-type semiconductor region forming a rectifying junction with the N-type semiconductor region, and a conductive non-silicide layer forming a rectifying junction with the N-type semiconductor region. n
The present invention relates to a semiconductor device comprising at least Schottky rectifiers in ohmic contact with silicide hooks on opposite sides of a rectifying junction. Such a semiconductor device is described in U.S. Pat.
855,612. The invention also relates to a method of manufacturing such a semiconductor device. The junction between the gold and the N-type semiconductor can be a rectifying junction or an ohmic junction, that is, a non-rectifying junction, depending on the properties of the gold-semiconductor material. 】Publication published in 1977 “DeViceglectronics
for Integrated C1rcuit"I
John Wiley and 5ons: New
As pointed out by R. Muller et al. in York), the work function distinguishes between ohmic and rectifying junctions. The work function is the amount of average energy required to raise an electron from the Fermi energy level to an energy level where gold is completely unaffected by the single-semiconductor system. If the work function of the metal is greater than the work function of the semiconductor when the materials do not interact, a rectifying junction is formed when the materials interact. For rectifying junctions, a charge depletion region consisting of bound positive charges exists on the semiconductor side of the interface. In an ideal metal-semiconductor system, electrons associated with bound positive charges reside in the metal near the interface, ie, within a few monolayers of the interface. This generates an induced electric field that is directed across the depletion region towards the interface where the electric field terminates. As a result, a characteristic voltage φ exists across the depletion region, the magnitude of which depends on the N-type dopant concentration in the semiconductor. This characteristic voltage represents the energy barrier qφ that electrons in the conduction band of the semiconductor must overcome to cross the interface and enter the metal. Here, q is the charge of the electron. This energy barrier can be alleviated by applying an external voltage that is positive to the semiconductor. As we increase the supply voltage, we eventually reach a stage where electrons flow freely from the semiconductor to the gold cherry. Therefore, φ represents the conduction forward voltage drop φSH across the rectifying junction. However, it is difficult to directly measure the φ process. A parameter that can be more easily ascertained from the current/voltage characteristics of gold-based semiconductor systems is the Schottky barrier height, expressed in units of electrostatic potential as φB or in units of energy as qφB. This Schottky barrier height is such that electrons in the metal in Fermi units must overcome to cross the interface and enter the semiconductor. Most of the electrons in the metal cannot enter the semiconductor because φB is larger than φ and in an ideal system is not significantly affected by the supply voltage. φB is also W# related to φl, thus giving a direct step of φSH. Many types of gold-semiconductor rectifiers, commonly referred to as Schottky diodes, have been considered. The oldest Schottky diodes utilize aluminum as the gold M and doped silicon as the N-type semiconductor. These basic A/-si diodes are relatively easy to manufacture. However, these diodes degrade relatively quickly as the aluminum mixes with the silicon. In view of this problem, modern Schottky diodes include other materials sandwiched between aluminum and silicon. According to one basic structure, the diode is formed on a semiconductor body with a suitably doped N-type semiconducting region. The metal silicide layer is adjacent to the N-shaded region and forms a rectifying junction at the interface between the N-shaded region and the silicide layer. Since metal silicides are generally considered to be metallic in nature, this junction is still referred to as a metal-semiconductor or Schottky junction. A typical example of silicide is platinum silicide.
Its qφB for N-type silicon lies between 0.79 and 0.88 electron volts (eV) depending on the dopant concentration. For example, W. Rosvold, U.S. Pat.
Flfifi6] As described in the specification No. 2,
Nickel is contained together with platinum in the silicide layer. This nickel reduces the qφB of the junction. The reason is 6 years old, qφB of nickel is about 0.63 to 0.676 compared to N-type silicon! This is because V. In known prior art Schottky diodes with an S-conducting non-quiride layer adjacent to a silicide layer on the opposite side of the Schottky junction, ff of the silicide layer, 2
is typically on the order of] OOnm, approximately 501
m or more. This thickness is used based on the prior art concept that sufficient silicide is needed to stabilize the silicide and avoid continuous defects such as pinholes within the silicide layer. The conductive non-silicide layer typically consists of a barrier metal such as tungsten or titanium-tungsten.
It is in ohmic contact with the silicide layer on the opposite side of the rectifying junction. This barrier gold μ is sufficient to prevent material on one side of the barrier metal from diffusing to the other side. Also, the barrier metal does not diffuse into the silicide. Finally, an aluminum layer is normally provided on top of the barrier metal F. The known Schottky diode based on pt is
Although it can be used successfully without appreciably reducing the quality of the bond, it is relatively expensive due to the high price of platinum. In Schottky diodes where the silicide layer is composed of two or more metals, it is difficult to control the mutual ratio of these metals in the deposition target used to form the metal layer that is later converted to silicide. ,Also,
Have difficulty. It would be desirable to have an inexpensive silicide Schottky diode in which φB can be varied to properly adapt φSH more easily than in the prior art. In some integrated circuits, this silicide Schottky diode is used with other Schottky diodes of different φB. In such semiconductor structures, which are particularly used in STL gates, each high φB Schottky clamping diode is typically formed by reacting platinum with silicon along the surface of a silicon semiconductor, as described above. It is a type of PtSi diode. Each low φB Schottky output diode is typically made of metal or T on silicon semiconductor.
A true gold m-semiconductor diode formed by depositing a gold a-alloy such as i-w. A non-silicide layer is provided between the silicon and the Ti-W. To manufacture this structure, which is compared to a structure in which all of the Schottky diodes have identical
Only one additional masking culm is required. However, since low φB diodes are made directly by metal deposition, their rectifying junctions are not as clean as the rectifying junctions of high φB silicide diodes made by reaction. J. Bindall et al. in the publication "' IEEE Tr.
aZISaCtiOnSON Electron De
ViCe8”, VOl, ED-27, 46
2. February 1979, pages 420-425 “onI”
implanted Low-Barrier PtSi
5chottky-Barrier])iodes”
describes another method for achieving semiconductor structures with Schottky diodes of different φB. When manufacturing a structure such as Bindall, first of all,
N-type impurities are implanted into the second region. This results in a net N-type concentration that is greater than the net N-type concentration in the first region. Approximately 50 nm of PT4 is then deposited onto the exposed surface of each region. The resulting structure is suitably heated to cause the platinum to react with the silicon along the exposed surfaces, forming PtSiN. Deposited platinum that has not been converted to PtSi is appropriately removed. Next, the Ti-Pt-Au layer is applied to the Pt opposite the rectifying junction.
A non-silicide layer is deposited on the structure over the Si layer and appropriately etched. When manufacturing implanted structures such as Bindall et al.
Single φB! f! Compared to fi construction, typically only one additional masking step is required. However, different breakdown voltages exist between different types of diodes. This is often undesirable because it provides additional limitations on circuit design. In summary, prior art structures with different φB Schottky guimates are generally old in manufacture, have reliability problems, and/or have unduly limited system design. According to a first aspect of the present invention, the semiconductor body has an N-type semiconductor region, and the metal silicide layer is adjacent to the N-type semiconductor region to form a rectifying junction therewith. In a semiconductor device comprising at least one Schottky rectifier where a non-silicide layer is ohmically adjacent to the silicide layer on the opposite side of the rectifying junction, the actual conductor-semiconductor barrier height at the junction; φB is the same material as the material of the N-type semiconductor region along the junction;
not substantially equal to the intrinsic conductor-semiconductor barrier height φBO at the interface between a material that is the same as the material of the silicide layer along the junction and has the same average composition as the silicide layer; The silicide layer is made sufficiently thin. The intrinsic barrier height φBO is the barrier height that can exist if the silicide layer has an effective finite thickness. In particular, the absolute value of (φBO-φB)/(φBo-φBN) is at least 15%, preferably at least 25%. φBN is the conductor-semiconductor barrier height at the interface between the same material as that of the N-type semiconductor region along the junction and the same material as that of the non-silicide layer. The invention is based on the discovery that silicides composed of metals such as platinum and/or nickel can sustain small electric fields, such as those that exist across a typical semiconductor PN junction. By making the silicide layer sufficiently thin, the self-induced electric field generated in the charge depletion region of the N shadow region penetrates through the silicide layer and into the non-silicide layer. Due to the penetration of the electric field into the non-silicide layer, the work function of the silicide layer "mixes" with the work function of the non-silicide layer. As a result, φB is
This becomes different from φBO, which is the barrier height of a Schottky diode according to the prior art. The manufacture of this rectifier typically involves less deposition of gold M into the silicide layer than in the prior art. Therefore, φB can be easily adjusted without going through deposition target composition changes, which are difficult to control, such as those used to vary the forward voltage drop in some conventional Schottky diodes. According to a preferred embodiment of the present invention, the silicide layer is made of PtSi.
The thickness is 5 to 251 m. When the non-silicide layer consists of tungsten or titanium-tungsten as the barrier metal, the ptsi is
A thickness of s nm is preferred. In this case, due to the mixture of work functions, qφB is
about 0.74 which is about 0.07ev smaller than the qφBO of a comparable prior art Schottky diode using
It becomes eV. (A qφB of 1,74 eV is quite adequate for many semiconductor applications and is achieved with a modest amount of platinum used in comparable prior art PTSI Schottky diodes. An important variation in which the metal is used in the silicide layer is that the gold silicide is the remainder of the original metal silicide layer of greater thickness.The average composition of the original silicide layer is Typically, φBO is determined for a material with the same average composition as the original silicide layer, since it is different from the average composition of the (remaining) silicide layer.
Occurs when it is composed of two or more generally different layers. One of these layers is adjacent to the N shadow region, the other is on top of one layer and has a different average composition. When manufacturing a diode according to this variant, a gold M layer of the selected metal is deposited on the exposed surface of the N-type silicon semiconductor region in the semiconductor body. The structure thus obtained is heated to a suitable temperature to cause the metal layer to react with the silicon along the surface, thereby forming the original silicide layer. The gold M and dopant concentrations in the N shadow region are selected such that the interface between the silicide layer and the remainder of the N shadow region is a rectifying junction. Next, on the side opposite the junction, a significant portion of the original silicide layer thickness is removed to establish the desired φB. In this way, a non-silicide layer of barrier metal is formed on the (remaining) silicide layer. A layer of a suitable conductor, such as aluminum, can then be deposited over the non-silicide. According to a second aspect of the invention, the semiconductor device comprises:
A semiconductor body having an N-type semiconductor region and a second N-type semiconductor region, which can be continuous with each other. The first metal silicide layer forms a second rectifying Schottky junction adjacent the first N-type region. A second metal silicide layer forms a second rectifying Schottky junction adjacent the second N-type region. The characteristic conductor-semiconductor barrier height φB2 of this second junction is different from the characteristic conductor-semiconductor barrier height φB1 of the first junction. The conductive non-silicide layer is in ohmic contact with the second silicide layer on the side opposite the second junction. The inherent conductor-semiconductor barrier height φ3 is the same material as the second region along the second junction and the material of the second silicide layer along the second junction. and a material having the same average composition as said second silicide layer and have the same average composition as said second silicide layer. make it thin. Specific barrier height φ
B20 is the barrier height that would exist if the second silicide layer had an effectively infinite thickness. In particular, (φBl−φB2)/(φBgO−φBNg)
the absolute value of is at least 15% and at least 25%
% is preferable. φBN2 is the conductor-semiconductor barrier height of the interface between the same material as the second N-type region and the same material as the non-silicide layer along the second junction. Although the characteristics of the rectifying junction can be normal, they can also be made according to the present invention. In this case, the other conductive non-silicide layer is in ohmic contact with the silicide layer on the opposite side from the 1st junction. The specific barrier height φB□ is defined for the first junction in the same way that φB2o is defined. The first silicide layer is thin enough so that it is not substantially equal to . Similarly, (φB1o−φB□)/(φB□.−φBN
y) is at least 15%. φBNI is
As φBIN+ is defined, it is similarly defined for other non-silicide layers. These silicide layers are usually composed of the same metal silicide but have different thicknesses. To fabricate this structure, first a gold silicide layer is formed along the N'# region to form a rectifying junction. The N shadow regions are constructed of silicon, which is typically done in two sets of similar steps. In the second set of steps, a first metal layer comprising the material in the first silicide layer is deposited on the surface of the first N-type region exposed by the masking step. The structure is then suitably heated to cause the gold F layer to react with the adjacent silicon. In a second set of steps, a second metal layer of metal within the second silicide layer is similarly deposited onto the surfaces of the second regions exposed by the other masking step. The structure is then suitably heated to cause the second gold layer to react with the adjacent silicon. Preferably, the second set of steps is performed after the first set of steps. In this case, part of the thickness of the second gold M layer is
It also deposits on the previously formed metal silicide along the shaped area. This part is converted to metal silicide during the next heating step. As a result, the first silicide layer is thicker than the second silicide layer. Next, a non-silicide layer is formed on the second silicide layer. Preferably, at the same time and of the same material, another non-silicide layer is formed on the first silicide layer. Compared to a structure in which all of the Schottky diodes have the same φB, only one additional masking step is required to fabricate this structure. This can be done without any loss of reliability. therefore,
This structure is generally simpler and more reliable than the prior art structure described above, which was similarly manufactured with only one additional masking step. Embodiments of the present invention will be described below with reference to the drawings. Like reference numerals are used in the figures and in the description of the actual KEi example to indicate the same or very similar elements. The figure shows a side view of a semiconductor structure with a Schottky rectifier that allows the actual conductor-semiconductor barrier height at the rectifying junction 20 to be easily controlled. Junction 20 is located between a metal silicide layer 22 and an N-semiconducting region 24 within a single crystal silicon semiconductor body 26 of the integrated circuit. The thickness t of silicide layer 22 is at least 15 angstroms. To avoid the occurrence of pinholes and other such continuous defects in layer 22, it is preferred that t be at least 50 Angstroms. fi
22 can be used with metals like platinum or nickel, or with 2 & 1
It consists of silicon chemically combined with such metals. In a preferred embodiment, layer 22 is PtSi and has a thickness t less than or equal to 24 nm, preferably
Onm or less. In this example, t Get is optimally 6 to s nm. The N-region 24 has approximately 2 X]017 atoms/Cm8
It has a substantially uniform net N-type dopant concentration of less than (corresponding to a resistivity of 10.05 ohm-cm). This ensures that junction 20 is rectifying in nature (rather than resistive). The optimal net N-type dopant concentration for N-region 24 is approximately 9.8 x ] 0 atoms/Cm"
made of a metal such as tungsten or titanium-tungsten that acts well as a diffusion barrier to silicon and aluminum at temperatures of 0.520° C. or lower (corresponding to a resistivity of about 0.3 Ω-cm); A conductive non-silicide layer 28 is ohmically adjacent to the silicide layer 22 along an interface 30. Optimally, the scrap 28 comprises approximately 100 nm of Ti-W mixed in a ratio of 85% tungsten and 15% titanium. The Schottky barrier qφBN at the interface between Ti-W with the above ratio and N-type single crystal silicon with the optimum dopant concentration is about 0.65 eV. In the preferred embodiment described above, where the PtSi heel length t of layer 22 is 6-B nm, the thickness of layer 22 is so thin that the forward voltage drop φSH across junction 20 is 0μ
With a junction current of A and a diode temperature T of about 2520, it is about a Mo mv. φB is calculated as a function of φSH by the following relational expression. I-R''A'r2e-qφB/kT(eqφ5Vr1
7-1) In this relational expression, R'' is the Richardson constant, k is the Boltzmann constant, and n is the ideal coefficient. A is the area of the interface of the junction 20. In this case, A is approximately 4 .6X]0066cm2n is about 1.04 T. Therefore, qφB is about 0.74 eV. Furthermore, qφB can be reduced to about (1,72 eV by decreasing t to 5 nm. can or t
By increasing to 10 nm, approximately 0.76e
It can also be increased to V. For comparison, for a reference diode in which the rectifying junction is at the interface with a reference silicide layer of N shadow region and a sufficiently large thickness, i.e. approximately ]OQ nm, the intrinsic Schottky barrier height φBO is equal to the conductor-semiconductor barrier Assume that it means height. The N shadow region is defined to be compositionally the same as the N'' region 24 along junction 20. Similarly, the reference silicide layer is defined to be of the same material as the silicide layer 22 along junction 20. The reference silicide layer is also defined to have the same average composition as layer 22.The reference diode is therefore essentially a comparable silicide Schottky diode according to the prior art. If this reference diode is the same as the optimal diode described above, except for the differences, then qφBO
is approximately 0.81 eV. This is clearly different from the actual value of eφB of 0.74 eV. Comparison parameter 1 (φBO
-φB)/(φBO-φBN)1 is approximately 44% in this case
It is. In FIG. 1, a layer 8 of a material suitable for electrically interconnecting a non-silicide layer 28 to other elements of an integrated circuit.
2 is provided on top of layer 28. Layer 82 is preferably a highly conductive metal, optimally containing about 1% copper.
aluminum with a thickness of 1.1 μm. Alternatively, the layer 32 may be composed of doped polycrystalline silicon or doped amorphous silicon. Within semiconductor body 26, P-substrate region 34 is N-
It is provided below the area 24. A highly doped P+ region layer 36 is present along the interface of regions 24 and 34. Buried layer 36 extends approximately 6 microns below interface 38 and also extends slightly above interface a8. Approximately 3.7 mm upwardly from interface 38 to upper surface 40 of body 26
The .mu.m extending N- region 24 is essentially an active semiconductor head laterally separated from other semiconductor regions by a deep annular highly doped P+ region 42. The area 42 is N
- laterally surrounding region 24 and extending approximately 5.5 mm below interface 88;
00. nml has increased. A shallow annular highly doped P+ region 44 is below the rc 622 portion of the lateral boundary of junction 20 and extends laterally outwardly beyond the side edge P of layer 22. The P+ layer 44 extending approximately 2 μm below the surface 40 leaks. It is a protective ring to reduce the flow. Thickness is 350
~400 nm silicon dioxide patterned electrical insulation N
46 is a guard ring 4 that extends laterally outwardly beyond the separation region 42, a portion of the N-region 24, and the side edges of the layer 22.
It is provided on a part of 4. Additionally, FIG. 1 shows an ohmic electrical contact to N- region 24. FIG. The contact is comprised of a highly doped P+ region 48, a metal silicide layer 50, and a conductive non-silicide N52. The N+ region 48 is
From the surface 4o to the inside of the semiconductor body 26, downwardly about], 2
It extends by μm. The silicide layer 50 is below the N+ region 4 at the junction 54.
Adjacent to 8. Non-silicide 852 is silicide N5
It is in ohmic contact with the upper surface m1 of o. conductive layer 5
6 is provided on top of the non-silicide layer 52. layer 5
Preferably, 0.52 and 56 are constructed of the same material as layers 22.28 and 32, respectively, and have the same thickness as layers 22.28 and 32, respectively. The net N-type dopant concentration in the door region 48 along the interface 54 is approximately 5×]0
'' atoms/cm8 (corresponding to a sheet resistance of about 1097 holes). As a result, the interface 54 becomes an ohmic junction. During operation, electrons flow from the contact through the N-region 24 to the buried layer 36 and then to the buried layer 36. They travel along buried layer 86 to a location below silicide layer 22. At a location below silicide layer 22, the electrons return via region 24 and junction 20. In the fabrication of the structure shown in FIG. The starting material is a boron-doped P''' single crystal silicon semiconductor substrate, which has a resistivity of 7-2] Ω-cm. Arsenic is selectively diffused into the upper surface of the substrate at the N+ regions to form N+ working heads 6. After exposing surface 38, an arsenic-doped N-epitaxial layer having a resistivity of about 0.3 Ω-cm is grown on top of the substrate. During this processing step and the next processing step, the arsenic is suitably redistributed to form a buried layer N+ region 6 with a sheet resistance of 10~]2 Ω/hole. A layer of silicon dioxide is thermally grown along the top of the substrate. After providing a suitable window through the oxide layer, boron is diffused through the window to form an isolation region 42 with a sheet resistance of approximately 5 ohms/hole. Next, silicon dioxide is thermally grown to close this window. After providing other suitable windows through the grown oxide layer,
The boron is again diffused to form a guard ring 44 with a sheet resistance of approximately 200 ohms/hole. The oxide growth, new window opening and diffusion steps are then repeated again with phosphorus to form N+ region 48. Another layer of silicon dioxide is thermally grown to close the window for N+ region 48. Layer 46 is the resulting oxide layer. Next, windows are provided in the oxide layer 46 at the locations of the diodes and contacts. After the structure has been properly cleaned, sputter etching with argon ions is performed to remove the silicon dioxide within the diode and mount windows. A layer of platinum having a thickness of approximately 3.5 nm is added to the oxide layer 46.
The top surface of the structure, including the exposed silicon surface, is deposited by conventional sputtering techniques. The structure was then sintered in dry nitrogen containing ]% hydrogen at a temperature of 450 °C for 20 minutes to react the platinum with silicon along the exposed surfaces in both windows. , forming layers 22 and 50 of PtSi. During this reaction, each unit of Si thickness reacts with about 1 unit of pt4,
Form a PtSi thickness of approximately 2 units. Next, the platinum that has not reacted to form PtSi is removed by etching with heated aqua regia. 100 of said ratio
A layer of Ti--W of 1 nm is deposited on top of this structure by conventional sputtering techniques and etched with hydrogen peroxide to form layers 28 and 52. Similarly, an aluminum layer containing approximately 1% copper is deposited on top of the structure and appropriately patterned by sulfuric/phosphoric acid etching to form layers 32 and 56. This structure is then completed by conventional methods. As mentioned above, φB at junction 20 differs from φBO by a significant amount. This difference is because the self-induced electric field directed across the depletion region in N-region 24 towards junction 20 penetrates through the gold R thickness t of silicide layer 22 and into non-silicide layer 28. It is believed that this occurs in This self-induced electric field is generated in the vicinity of the interface 30, i.e. in the layer 2
Finish within a few monolayers to 8. Further penetration of the self-induced electric field through the silicide layer 22 is believed to occur because the silicide of the layer 22 is particularly semiconducting in nature. FIGS. 2a and 2b show the energy diagram and the N-region 24, silicide layer 22 and non-silicide layer 2, respectively.
FIG. These figures are intended to facilitate a qualitative understanding of the physical properties of the devices involved in this phenomenon. For ease of explanation, Figures 2a and 2b represent the case where no external voltage is applied to the diode. The solid line in FIG. 2a shows the actual energy variation of the diode in the case described above, where φBN for the material of the non-silicide layer 28 is smaller than φBO and the composition of the silicide layer 22 is uniform throughout its thickness. (as PtSi). The dashed line in FIG. 2a represents the energy change for a reference diode in which the silicide layer thickness is effectively infinite. The +++” symbol surrounded by circles in the N- region 24 of FIG. 2b represents the bound positive charge in the depletion region with width (thickness) in tD. The “-” in layers 22 and 28 The symbols represent electrons that combine with bound positive charges to achieve total charge neutrality. one portion located at layers 22 and 28 remote from junction 20 for inducing a portion of the electric field through silicide layer 22. The work function is generally expressed in units of electrostatic potential or units of energy. ΦSB and ΦMB are their respective bulk values when the N-type semiconductor and metal silicide do not interact (ie, there is no silicide-semiconductor rectifying junction). ΦSB exists in the N-type semiconductor outside its charge depletion region. In order to produce a rectifying effect, ΦMB must exceed ΦSB. Also, the work function Φ of the non-silicide layer 28 (or the corresponding non-silicide layer in the reference diode)
IN is smaller than ΦMB (because in this case φBN is smaller than ψBO). According to these considerations, a good starting position is the Fermi energy BF, which is constant in a Schottky diode with no applied pressure. The sum of this BF and the work function at any position in this diode is the energy EH at which the electron is not affected by the diode at all. Although EH changes, it is continuous at any conductor-semiconductor interface or at any conductor-conductor interface. Looking first at the reference diode, the characteristic work function Φso of its N shadow region increases from ΦSB outside the depletion region to a maximum value at its rectifying junction. This is because cumulatively more energy is required to raise the electrons to Tt EH. EF is constant and EH
Since is continuous, Φso corresponds to zero to the work function at the rectifying junction of the silicide layer of the reference diode. At that position, ΦNo is equal to ΦMB. Near the field 15 plane between the silicide and non-silicide layers in the reference diode, ΦM. decreases to ΦIN. In the diode shown in the figure, the actual work function ΦS of the N'' region 24 similarly rises from ΦSB outside the depletion region to a maximum value at the junction 20. In this junction 20, ΦS Similarly, at junction 30 ΦM corresponds to ΦIN. An important difference between the reference diode and the rectifier shown in FIG. means that ~ is always smaller than ΦMB. This generally makes ΦM low since ΦMO mixes with a low value of ΦIN. Therefore, the value of ΦM at junction 20 is equal to that of the reference diode. Φ in rectifying junction
It is lower than MO by ΔΦ. This difference ΔΦ is reflected as the difference between φBO and φB. This occurs because the difference qX between EH and the lowest energy Eo in the semiconductor conduction band is constant. E
As H increases across the depletion region, EQ increases as well. The change in EC is the actual semiconductor-conductor energy barrier qΦ, which is qΔΦ smaller than the intrinsic semiconductor-conductor energy barrier qΦIO. Similarly, qφB is the difference between EF and E at junction 20. Therefore, φBO exceeds φB by ΔΦ. Alternatively, ΦMN of non-silicide layer 28 may exceed ΦMO. In this case, φB becomes φBO
It will exceed. The dash-dotted line in Figure 2a represents the actual energy change for this complementary case,
The respective relevant parameters are indicated with a ``se'', i.e., this complementary ÷ (parameters for the case ~N, ΦM, ΦMO and Φ8"
correspond to ΦMN, ΦM, ΦMO and Φ8, respectively. In this complementary case, the physical properties of the base device are largely the same as in the base case, except that the sign is reversed. Therefore, here:
For a pair of conductors, the difference in their work functions represents the difference in their barrier heights for the same semiconductor. In particular, the difference between ΦNo and ΦMN represents the difference between φBO and φBN. Therefore, the parameter l(φBO−φB)
/(φBO−φBN), hereinafter referred to as ε) represents the amount of work functions mixed in this diode. FIG. 3 is a graph showing the experimental variation of φB versus silicide thickness t for a PtS earth diode. The endpoints of this curve are φBO when t is effectively infinite, i.e. approximately 100 nm, and φBO when t is 0, i.e. N
- φBN when region 24 is directly adjacent to non-silicide layer 28; FIG. 4 is a graph showing a curve representing all the changes in ε with respect to t. Some statistical variation exists in the data shown. Additionally, there are some difficulties in determining t due to measurement equipment and technical limitations. Even allowing for statistical variations and measurement precision, when t is less than or equal to about aonm, φB is φBO
It is clear that they are quite different. The kneading corresponds to the range starting at point 58 in FIG. 4 with ε of at least 15%. In particular, the curve begins to curve sharply near point 60, where ε is about 25%. Ranges greater than 25% are even more preferred. This is because φB can vary greatly within this range in which the variation in t is small. FIG. 5 shows an embodiment of the diode of FIG. 1, in which layer 22 is a nickel and platinum silicide divided into a set of layers 62 and 64. The lower layer 62 is adjacent to the N- region 24 along the interface 2o and is
can be changed between 0 and] N1-yP t 1-yS l
It consists of The positive layer 64 is adjacent to the non-silicide layer 28 along the interface 80 and is composed of N1zPt, -zSi, where 2 can vary between O and Y. therefore,
The lower layer 62 is rich in Ni compared to the upper layer 64. In the illustrated embodiment, Y is approximately 0.9 and 2 is approximately 0.9.
It is 25. Non-silicide layer 28 is comprised of Ti-W in the ratios described above. As mentioned above, the reference diode characteristic height is defined for a silicide layer having the same average composition as layer 22. This is important because the compositional differences between layers 62 and 64 must be considered. The rectifier layer 21'i of FIG. 5 is preferably the remainder of the original silicide layer of greater thickness. In this case, ΦBO is defined relative to a reference silicide layer that is the same as the original silicide layer along junction 20 and has the same average composition as the original silicide layer. In the particular embodiment of FIG. 5, if the original silicide layer is formed to a thickness of about 100 nm as described below, qφB is about 11.74 eV. This value is approximately the appropriate qφBO. The thickness tL of the lower layer 62 is slightly less than 50 nm. Upper layer 64
Based on the office chosen for, stU, qφBp O
,f! It can be adjusted as low as 6 eV. This minimum value occurs when tU is zero. The effect is obvious when ε is 15% or more. It is believed that the ability to completely control .phi.B by making upper layer 64 very thin is due to the electric field penetrating through silicide layer 22fl and into non-silicide layer 2B. Layer 22 has different average compositions 62 and 6
The physical properties of the device are essentially the same as those described in FIGS. 2a and 2b, although the 4-way separation results in slight differences in the work functions that are mixed. Figures 6a, 6b, 6c and 6d are the fifth
Each step of the manufacturing method of the specific rectifier shown in the figure is shown. In this method, silicon semiconductor body 26 is first processed as described above for the rectifier of FIG. Form windows for contacts (not shown). The structure at this stage is a #& structure as shown in FIG. 6a with N- region 68 below and adjacent buried region 36. Semiconductor body 26 ,
Doped regions 42, 44 and 48 are preferably present at this stage as shown in FIG. 1, but are not shown here. In the next step, layers F10.52 and 56 for the mount
, and at the same time layer 22, of the same material as layers 28 and 82.
2.28 and 32, respectively. For the sake of simplicity, we will not mention contacts. Next, Ni-pt with a ratio of 60% nickel to 40% platinum
A metal layer 70 of about 50 nm is deposited by conventional sputtering techniques onto the surface 66 shown in FIG. 6b. , make a deposit. This structure was sintered at 500° C. for 20 minutes in a dry oven containing 1% hydrogen to react the nickel and platinum with the silicon along the surface 66 and at the interface 2o as shown in Figure 6C. A native silicide layer 72 is formed along and adjacent the remainder 24 of the N-region 6s. The thickness of the resulting silicide layer 72 is approximately 100 nm;
Its average composition is Nio, 6Pto, and Si. During this sintering process, the silicide layer 72 actually forms the upper silicide hook shape 74f with the lower silicide 62. The average composition of the lower layer 62 is approximately Nio, Pto, ISi
It is. The average composition of the upper layer 74 is approximately Nio, 25Pto, 76
It is Si. The Ni--Pt that has not reacted to form the silicide layer is removed by etching with aqua regia at room temperature. A portion of the thickness of the upper layer 74 is as shown in FIG. 6d.
The upper portion 64 is removed by scraping with argon ions, leaving the silicide layer 22, which is the remainder of the original upper N74. ] 00 nm of Ti-W in the above ratio
A layer is deposited on top of this structure by conventional sputtering techniques and suitably etched with hydrogen peroxide to form the fifth layer.
A non-silicide layer 28 is formed as shown. A layer of aluminum containing approximately ]% copper is deposited on top of this structure and appropriately patterned by etching with sulfuric/phosphoric acid to form #82. As mentioned above,
Since the bottom layer 62 is very thin, removing a portion of the original layer 74 increases φB from about 0.74 eV with the top layer 74 intact to that of the case with the top layer 74 completely absent. It is possible to reduce it to about 0.6 fl eV. The rectifier shown in the figure is particularly suitable for semiconductor structures with Schottky diodes of different φB. 7th
The figure shows a side view of such a structure that can be used in the STL part of an integrated circuit. FIG. 8 is a corresponding circuit diagram. This structure is such that the N+ emitter] 62 preferably receives the supply voltage VEE t' with respect to earth (O volts), and the P- base]
64 is located around an NPN bipolar transistor Q which receives the digital input signal V. base 16
4 through an input resistor RI (not shown in FIG. 7),
2.5 volts is coupled to another preferred supply voltage CC. The collector of transistor Q is connected to the cathode of a Schottky diode S□ whose anode is connected to base 164. The collector is 1, in addition to directly supplying the digital output signal
connected to the cathode of The anodes of these diodes are connected to another output digital signal oA. VOB and voc are respectively supplied. Diode S
The actual conductor-semiconductor barrier height φB □ of □ exceeds the actual conductor-semiconductor barrier height φB2 of any of diodes S2A, 32B, and 820. As a result, the conduction forward voltage drop φSHI of the diode S0 exceeds the conduction forward voltage drop φSH2 of the diode S2A, 82B or S20. The rectifying junction 166 of diode S1 is at the interface between the full silicide layer 68 and the underlying N-semiconductor region 70 in the single crystal silicon semiconductor body 172. The silicide layer 68 also has an N-region 70 adjacent the P-region 64 below at the ohmic junction 174.
It extends laterally from Diode S2A, 3
Rectifying junctions 76A, 76B of 2B and S20, respectively
and 760 are N-regions] 70 and metal silicide #78
It exists all over the interface with A, 78B and 780. area] 70 is about 2 x ] 0” atoms/cm8 (0
, corresponding to a resistivity of .05 Ω-cm). This ensures that junctions 166.76A, 76B and 760 are actually rectifying junctions. The optimal net N-type dopant concentration in the area 70 is about 9.8×]O15 atoms/cm8 (corresponding to a resistivity of about 0.3 Ω-cm). Any of the metal silicide layers described above may include layers 168°78A,
78B and 780, the preferred silicide is PtSi. The thickness tl of layer]68 is ]0
0~] ] Onm (or more). Therefore, qφB1 is approximately 0.8 ] eV. This is the corresponding intrinsic Schottky barrier height qψBIO. In this case, φSHI is 480 with a junction current of 10 μA.
mV. As shown in FIG.
The thickness t2 of A, 78B or 780 is at least 1.
5 Ωm, preferably at least 5 nm. t
2 is below ] Onm, and optimally 5 to 6 nm. As a result, φB2 is
It depends on the material on the opposite side to flO. This is because the self-induced electric field passes completely through WIs 78A, 78B and 780. Conductive non-silicide layers 80A, 80B and 80G consisting of about 00 nm of Ti-W mixed in a ratio of 85% tungsten and 5% titanium are applied to the silicide layers 78A, 78B and 780, respectively, on top of them. Adjacent along the surface. an interface between Ti-W having the above ratio and N-type single crystal silicon having the above optimum dopant concentration;

[The Schottky barrier height qφBNg at this point is approximately 0.651
It is 9V. Therefore, qφB2 is approximately 0.726V at the optimal value of t2, while φSH2 is 340 mV at a junction current of 0 μA. In this way, qφB2 is
0.8] Intrinsic Schottky barrier height qφf3 in eV
20 is quite different. Ratio parameter 1 (φBsto−φB,)/(φB21
0-φBNg'l is approximately 56% in this case. More generally, 1(φB20−φB,)/(φBgo−φ
BNB ) I is at least 15%, more preferably at least 25% as discussed in FIG. In this case, φB. is equal to φB2o. The reason is that the net N-type dopant concentrations in the N-regions 7() along junctions 166.76A, 76B and 760 are the same, and in addition the silicide layers 168.78A, 71'l
B and 780 are composed of PtSi, i.e. these silicide layers have the same average composition and junction 1
66.76A. 76B and 76 (3). Otherwise, φBlo is generally φB2o
will not be equal to . A medium non-silicide layer 82 consisting of Ti--W mixed in the above ratio is in contact along the upper surface of the silicide layer 168. Such Ti-W and interface 16
6] The Schottky barrier height at the interface with N-type single crystal silicon with the same dopant concentration as 70 is:
%'L to φBN2. The dopant 6 degree of the region along the interface] 66] 70 is
If the dopant concentration is different from zero, φBN□ will generally not be equal to φBNg. This means that non-silicide layer 82 is non-silicide layer 80A. This also applies to materials other than 80B and Floo. Layers 84A, 84B and of suitable materials for non-silicide layers 80A, 80B and 800, respectively electrically interconnected to other elements of the integrated circuit, are preferably highly conductive metals and have approximately 1. ] μm thickness and approx. ]%
Aluminum containing copper is most suitable. or,
These layers can also be composed of doped polycrystalline silicon or doped amorphous silicon. The P-substrate region 88 in the semiconductor body 72 is the N-region]
It is provided on the lower side of 70. Highly doped door buried area #
9o is provided along an interface 92 between regions 170 and 88. A buried region 90 extending approximately 6 microns below interface 92 and slightly above provides a conductive path for electrons moving between elements of the structure. The N- region 170, which extends approximately 3.7 μm from the interface 92 upwardly to the upper surface 94 of the semiconductor body 72, is essentially an active semiconductor region separated laterally from the middle semiconductor region by a deep annular highly doped P+ region 96. It is. Area 96 is area]70
is laterally surrounded by approximately 500 mm below the interface 92.
It extends by nm. N-region 70 laterally and upwardly surrounds P-region 64, which extends approximately 2 μm below surface 94. Similarly, similarly, P″″ area]6
4 laterally and upwardly surrounds region N along surface 94. The last semiconductor region within semiconductor body 72 is a highly doped N+ region 98 laterally and upwardly surrounded by N- region 70. N shadow regions 170, 90 and 98 together form the collector of transistor Q. N+ working heads 62 and 98 extend approximately ], 0 μm downward from surface 94. Patterned electrical insulation 1100i of silicon dioxide 350-400 nm thick, silicide layer 16Fl
, 71'lA, 78B and 780, and N''
A silicide layer ohmically adjacent fJljt 162 and υ98 is provided on top of semiconductor body ]72 along surface 94, except at locations ]02 and ]04, respectively. Layers 102 and 04 are preferably comprised of PtSi having the same thickness as layers 78A, 78B and 780. consisting of Ti-W in the above ratio] OOn
Layers ]06 and ]08 of m are provided on the upper surfaces of the silicide layers ]02 and ]04, respectively. Finally, N54
h, s4B. Layers ]]0 and ]]2 having the same thickness and of the same highly conductive metal as 840 and 86 are provided on top of non-silicide 1106 and ]08, respectively. Figures 9a, 9b, 9c and 9d are
The manufacturing process of the structure shown in the figure is shown. General masking, etching and cleaning techniques, which are not discussed in detail for ease of explanation, are used to fabricate the various doped regions and overlying layers. In many diffusion processes, impurities can also be introduced by ion implantation. The starting material is a boron-doped P-single crystal silicon semiconductor substrate with a resistivity of about 7-2] Ω-cm. Arsenic is selectively diffused into the upper surface of the substrate at the location of N+ region 9o. After exposing surface 92, approximately 0
．． Arsenic-doped N- with resistivity of 3 Ω-cm
An epitaxial layer is grown on top of the substrate. During this and subsequent processing steps, the arsenic is suitably redistributed to form a buried region 90 with a sheet resistance of 0 to 2 ohms/hole. A layer of silicon dioxide is thermally grown along the top of the structure. After providing a suitable window in this oxide layer, boron is diffused through the window to form an isolation region 96 of 5 Ω/hole sheet resistance. A layer of silicon dioxide is thermally grown to close this window. Another window is provided at the location of P-region 164 and boron is diffused to form a p-region having a sheet resistance of 200 ohms/hole. Another layer of silicon dioxide is thermally grown to close this window. After providing suitable windows in this oxide layer, phosphorus is diffused to form N regions 62 and 98 with a sheet resistance of 0 Ω/hole. Another layer of silicon dioxide is then thermally grown to close regions 62 and 98. Layer ] 00 is the resulting oxide layer. At this stage, a structure as shown in FIG. 9a is formed. N-region 70 is the remainder of the original epitaxial layer with no further processing, while base 64 is the remainder of the original diffused P-region excluding emitter 62. In the first set of diode manufacturing processes, the diode S
A photoresist mask is used to create windows in oxide layer 100 at locations . This window also covers the P-region 16
It is located on a part of 4. After pre-rinsing the structure, the diode S is sputter-etched in situ with argon ions.
] to remove silicon dioxide within the window. This exposes the silicon surface of surface 94 ]]4. Next, a gold return layer 116 of platinum having a thickness of about 50 nm is applied.
is deposited by conventional sputtering techniques on top of the structure on surface 14 as shown in FIG. 9b. This structural tube is sintered at 4FIO'C in wet nitrogen for about 20 minutes to react the platinum with the silicon along the surface ]14 to form a PtSi layer ]]8 having a thickness of about 100 nm. . When converted into platinum Epts soil through such a process, each unit of silicon thickness reacts with approximately 1 unit of pt thickness to form a PtSi thickness of approximately 2 units. The platinum that has not reacted to form PtSi is removed by etching with heated aqua regia. In the manufacturing process of one diode of the second set, the portions of diodes S2A, 82B and 82G and the N area]
Another photoresistor mask is used when providing windows in oxide layer 100 over 62 and 98. After pre-rinsing the structure, sputter etching with argon ions in situ removes the diodes S2A, 82B.
, 820 and the silicon dioxide in the window for the N+ working head mount 62°98. As a result, the silicon surface portion 12OA of the surface 94. 120B, 120C, ], 22 and ]24 are exposed. Then platinum gold Jj with a thickness of about 2.5~a nm
1f@126 by conventional sputtering techniques to surfaces 120A, 120B, 1200.12 as shown in FIG. 9c.
2 and ]24 on top of the structure. In this deposition, gold H4N]26vptsiN]]s
Also make a deposit at the top. This structure was sintered in wet nitrogen at 450°C for approximately 10 minutes to deposit platinum on the surface of 120A.
, 120B, 120 (3° 122 and ] 24 to form silicide layers 7FIA, 78B,
780.102 and 104. During this heating step, portions of the gold layer 126 on the PtSi layer]
Similarly, by reacting with the adjacent silicon, the layer]]8 is converted to 5 to 6n
m thickness of the silicide layer 168. The unreacted platinum to form PtSi is removed by etching with heated aqua regia. 00 nm of Ti--W layer of said ratio is deposited on top of the structure by conventional sputtering techniques and suitably etched with hydrogen peroxide to form layers 80A, 80B, 800, 106 and 108 are formed. Similarly, W of aluminum containing about 1% copper
The top of the 4fl structure is deposited and suitably patterned with a nitric acid/phosphoric acid/acetic acid etch to form layers 84A, 84B184C11]0 and ]]2 as shown in FIG. This structure is then completed in the usual manner. In the structure of FIG. 7, fabricated as shown in FIGS. 9a-9d, φBl was chosen to be equal to φBl(l. In other structures using the diode of FIG. 1, the diode S] A silicide layer corresponding to layer 168 for φ
It can be made sufficiently thin that B1 is not substantially equal to φB0. In this case, 1(φB1 diφB1)/(φBlo−φBN
It is preferable that I )l be 5% or more, particularly 25% or more. Although the present invention has been described above based on specific embodiments, the present invention is not limited thereto, and it goes without saying that various modifications and changes can be made within the scope of the present invention. For example, it can be a non-silicide layer, approximately doped silicon, or other metal but not barrier gold. Furthermore, in cases where there are two or more Schottky rectifiers, the #1 composition of their non-silicide layers can be made different even if their silicide layers are composed of the same material. can. The composition of the silicide layers can vary as long as at least one of the silicide layers is thin and φB is not substantially the same as the φBO of that silicide layer.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor structure having a Schottky rectifier according to the invention; FIGS. 2a and 2b are energy diagrams and associated structural diagrams to aid in understanding the rectifier of FIG. 3 and 4 are graphs showing the variation of φB1′ and 1(φBO−φB)/(φBO−φBN)l, respectively, with respect to the silicide thickness in a PtSi Schottky diode, and FIG. 6a and 6b are partial cross-sectional views of a structure having a rectifier which is a specific embodiment of the rectifier shown in FIGS.
60 and 6d are cross-sectional views representing steps in the manufacturing process related to the structure of FIG. 5; FIG. 7 is a cross-sectional view of a semiconductor structure containing a Schottky diode according to the invention with different barrier heights; FIG. 8 is a diagram showing a circuit corresponding to the structure of FIG. 7; FIGS. 9a, 9b, 9c, and 9d are partial sectional views of
FIG. 3 is a cross-sectional view showing steps in the process of manufacturing the structure shown in the figure. 20, 76, 166... Rectifying junction 22, 5 (1,768... Gold E silicide hook shape 24, 6R
, 170... N- semiconductor region 2d, 172... semiconductor body jllR, 52, 82... conductive non-silicide layer 34,
8F+...P- substrate region 86.90...N+ buried layer 42, 44.96-P region 46.100--insulating layer 48, 98...N region 56...conductive layer 6
2... Lower layer 64... Upper layer 70, 1
lfl, 126...Metal layer]]8...PtSi layer]62...Door emitter]64...P-base. Patent applicant: N.P. Phillips Fluiran Penfapriken Fig, 3

Claims (1)

Claims: 1. A semiconductor body having an N-type semiconductor region, a metal silicide layer adjacent to the N-type semiconductor region forming a rectifying junction with the N-type semiconductor region; In a semiconductor device comprising at least ] Schottky rectifiers with a oxide layer ohmically adjacent to the silicide layer on the opposite side of the rectifying junction, the actual conductor-semiconductor barrier height φB at the junction is characteristic at the interface between a material that is the same as the material of the N-type semiconductor region along the junction and a material that is the same as the material of the silicide layer along the junction and has the same average composition as the silicide layer; A semiconductor device characterized in that the silicide layer is sufficiently thin such that it is not substantially equal to a conductor-semiconductor barrier height φBO. λ The semiconductor device according to claim 1, wherein φBN is between a material that is the same as the material of the N-type semiconductor region along the junction and a material that is the same as the material of the non-silicide layer. If the conductor-semiconductor barrier height at the interface is (φBO-φB)/(φBO-φB
A semiconductor device characterized in that the absolute value of NJ is 0.15 or more. & A semiconductor device according to claim 2, characterized in that the absolute value of (φBO−φB)/(φBO−φBN > is 0.25 or more. 4 Claims The semiconductor device according to claim 3, characterized in that the self-induced electric field passes through the entire thickness of the silicide layer and enters the non-silicide layer. A semiconductor device according to claim 4, wherein the N-type semiconductor region is made of fully doped silicon and the non-silicided hook is made of metal. 2. The semiconductor device according to item 2, wherein the silicide layer contains PtSi, and the silicide layer has a thickness t of 5 to 25 nm. , A semiconductor device according to claim 6, characterized in that the thickness t is at least 5 nm. & Claim 7 In the semiconductor device as described, the N-type semiconductor region is fully doped silicon, and the non-silicide layer is a metal that acts well as a diffusion barrier to silicon and aluminum at humidity below 520°C. 9. A semiconductor device according to claim 2, wherein the silicide layer includes a first layer adjacent to the N-type semiconductor region, and a first layer adjacent to the N-type semiconductor region; a second J layer on the opposite side of the junction and having a different average composition than the first layer;
A semiconductor device comprising fJ. 10 In the semiconductor device according to claim 9, the average composition of the first layer is substantially NiY''tl-ySi with Y being a variable between 0 and 1, and the average composition of the second layer is In effect, the average composition of N1zP tl with 2 as a variable between 0 and Y
A semiconductor device characterized in that -2s1. 11. The semiconductor device according to any one of claims 1 to 10, wherein the metal silicide layer is made of at least two selected metals, and the silicide layer comprises: A semiconductor device characterized in that the remainder of the original metal silicide layer is of greater thickness. 1λ a second N-type semiconductor region, a second silicide layer, and a second N-type semiconductor region;
with a rectifying junction and a second non-silicide layer, forming an actual conductor.
A semiconductor device according to any one of the claims, comprising a second rectifier having a semiconductor barrier height φB2 and a specific barrier height φB20, a first N-type semiconductor working area; a second non-silicide layer forming a rectifying junction adjacent to the first N-type semiconductor region and having an actual conductor-semiconductor barrier height φB different from the barrier height φB2; Characteristic semiconductor devices. l& The semiconductor device according to claim 12, wherein another conductive non-silicide layer is ohmically shielded to the first silicide layer on a side opposite the first junction, and the φBl is , the same material as the material of the first N-type semiconductor region and the same material as the material of the first silicide layer along the first junction and having the same average composition as the first silicide layer; 1. A semiconductor device characterized in that said silicide layer is sufficiently thin such that the intrinsic conductor-semiconductor barrier height at the interface therebetween is not substantially equal to φB]'0. 14. The semiconductor device according to claim 3, wherein φBNI is the same material as the first N-type semiconductor region along the first junction and the same material as the other non-silicide layer. If the height of the conductor-semiconductor barrier at the interface between the material and
/(φBIO−φBNI A semiconductor device characterized in that the absolute value of l is 0.15 or more. 15. In the semiconductor device according to claim 14, the N shadow regions are continuous with each other, By having approximately the same net N-type dopant concentration along the junction and by having the silicide layer have approximately the same composition along the junction and approximately the same average composition, making φBIO equal to φBgo 16. A semiconductor device according to claim 15, characterized in that the non-silicide layers have the same material, thereby making φBN□ equal to φBN′g. 17. A semiconductor device according to any one of claims 32 to 6, characterized in that the silicide layers have the same metal silicide having different thicknesses. 18. The semiconductor device according to claim 7, wherein another conductive non-silicide layer is ohmically bonded to the silicide layer on a side opposite to the junction. 19. A semiconductor device characterized in that the non-silicide layer is a metal layer of the same composition as the non-silicide layer.19. depositing on the exposed surface of the semiconductor region and heating the semiconductor body and the metal layer to a suitable temperature to cause the metal to react with silicon along the surface and forming a base adjacent to the remainder of the N shadow region; forming a metal silicide layer, selecting the metal and impurity dopant concentrations in the N shadow region such that the interface between the N shadow region and the original metal silicide layer is a rectifying junction; A method of manufacturing a semiconductor device comprising the step of removing a substantial portion of the thickness of the original metal silicide layer opposite the junction so as to leave a metal silicide layer of . 20. A method of manufacturing a semiconductor device according to claim 19, characterized in that a conductive non-silicide layer is formed on the remaining silicide layer. 21. In the method of manufacturing a semiconductor device according to range 20 gJ, the remaining silicide layer is formed on at least a first layer adjacent to the remainder of the N shadow region and on the first layer on the side opposite to the junction. forming an original second layer with an average composition different from that of the first layer, wherein the removing step includes removing at least a portion of the thickness of the original second layer; A method of manufacturing a semiconductor device, characterized in that the first layer is sufficiently thin such that the actual conductor-semiconductor barrier height φB at the junction can be controlled by the extent of removal. In the method for manufacturing a semiconductor device according to claim 22, φBO is made of the same material as the N-type semiconductor region along the junction and the original semiconductor region along the junction. Let the intrinsic conductor-semiconductor barrier height at the interface between the material be the same as that of the silicide layer and have the same average composition as the original silicide layer, and φBN
where is the conductor-semiconductor barrier height at the interface between the same material as the N-type semiconductor region and the same material as the non-silicide layer along the junction: (φBO−φB) The absolute value of /(φBO−φBN) is
A method for manufacturing a semiconductor device, characterized in that the ratio is 0.15 or more. 2. In the method for manufacturing a semiconductor device according to claim 22, the average composition of the first layer is substantially
N1yP t 1-Y as a variable between yt-o and]
A method for manufacturing a semiconductor device, characterized in that S soil is used, and the average composition of the second layer is substantially N1zPt1-ZS1 with 2 being a variable between 0 and Y. 24. A method of manufacturing a semiconductor device according to claim 19, by depositing a layer of gold comprising the metal material of the quarride layer on the exposed surface of the first N-type silicon semiconductor region. forming a first silicide layer; suitably heating the semiconductor body and the metal layer to react with the silicon in the region; forming a second silicide layer; The second gold R layer made of the metal material of the second silicide layer is
A semiconductor characterized in that it comprises depositing onto the exposed surface of an N-type silicon region and a subsequent step of suitably heating said semiconductor body and a second gold M layer to react with the silicon of said second region. Method of manufacturing the device. 2. In the method of manufacturing a semiconductor device according to claim FBI No. 24, the step of depositing the second gold layer is performed after the step of heating the semiconductor body and the second metal layer, and depositing a second metal layer, the second gold layer depositing a portion of the layer onto the metal silicide along the first region; and heating the semiconductor body and the second metal layer. 26. The method of manufacturing a semiconductor device according to claim 25, further comprising the step of heating the portion to react with silicon in the first region. 1. A method for manufacturing a semiconductor device, characterized in that metal layers are deposited of different thicknesses of the same material. In the method of manufacturing a semiconductor device according to claim 26, another conductive non-silicide layer is ohmically formed on the silicide layer on the side opposite to the first junction, A method for manufacturing a semiconductor device, characterized in that the non-silicide layers are formed simultaneously using the same forest material.