JPS6119179A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6119179A JPS6119179A JP13964484A JP13964484A JPS6119179A JP S6119179 A JPS6119179 A JP S6119179A JP 13964484 A JP13964484 A JP 13964484A JP 13964484 A JP13964484 A JP 13964484A JP S6119179 A JPS6119179 A JP S6119179A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicide
- substrate
- schottky barrier
- depth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 18
- 238000005530 etching Methods 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 150000002739 metals Chemical class 0.000 abstract description 2
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 abstract 3
- 229910021340 platinum monosilicide Inorganic materials 0.000 abstract 3
- 229910008484 TiSi Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 description 10
- 239000012535 impurity Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 1
- 241000277269 Oncorhynchus masou Species 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28537—Deposition of Schottky electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体基板上に順方向電圧（ＶＦ）の異な
る複数のショットキー・バリア・ダイオードを有する半
導体装置の製法に関し、複数種類の金属をシリサイド−
シリコン界面深さが異なるよう吟順次にシリサイド化す
ることにょシ所望の順方向電圧を有する安定した特性の
ショットキー・ツマリア・ダイオードが得られるように
したものである。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device having a plurality of Schottky barrier diodes having different forward voltages (VF) on a semiconductor substrate. Silicide-
A Schottky-Zumaria diode with stable characteristics and a desired forward voltage can be obtained by sequentially siliciding the silicon interface with different depths.
一般に、ショットキー拳バリア・ダイオードの順方向電
圧はバリア・ハイドによって決まり、このバリア・ハイ
ドは半導体表面の不純物濃度と、半導体表面に接触させ
るべ含金属の材料とに依存することはよく知られている
。Generally, the forward voltage of a Schottky barrier diode is determined by the barrier hide, and it is well known that this barrier hide depends on the impurity concentration on the semiconductor surface and the material of the metal that is in contact with the semiconductor surface. ing.
従来、シリコン基板上に順方向電圧を異にする複数のシ
ョットキー・バリア・ダイオードを作るにあたっては、
ｌａ）シリコン基板表面の不純物濃度を例えばイオン注
入法等により変える方法及び（ｂＪシリコン基板表面に
接触させるべき金属の材料を変える方法等が知られてい
る。Conventionally, when creating multiple Schottky barrier diodes with different forward voltages on a silicon substrate,
There are known methods such as la) changing the impurity concentration on the silicon substrate surface by, for example, ion implantation, and bJ changing the material of the metal to be brought into contact with the silicon substrate surface.
上記（ａｔの方法によると、順方向電圧を低下芒せたシ
ョットキー−バリア・ダイオードでは、リーク電流の増
大、耐圧の低下、高温での動作マージン劣化等の問題点
があった。また、上記ｆｂ）の方法によると、順方向電
圧の低いショットキー・バリア・ダイオード７形成する
ためにシリコン基板表面にタンタル（Ｔ１）、チタン−
タングステン（Ｔｉ−Ｗ）合金等の金属を接触嘔せてお
シ、表面の不安定性がそのま１ダイオード特性の不安定
性につながること、単なる金属材料の選定では所望の順
方向電圧を得難いこと々どの問題点があった。According to the above method (at), Schottky barrier diodes with a reduced forward voltage had problems such as an increase in leakage current, a decrease in withstand voltage, and a deterioration of the operating margin at high temperatures. fb) method, tantalum (T1) and titanium are deposited on the silicon substrate surface to form a Schottky barrier diode 7 with a low forward voltage.
When contacting metals such as tungsten (Ti-W) alloys, the instability of the surface directly leads to instability of the diode characteristics, and it is difficult to obtain the desired forward voltage simply by selecting the metal material. What problems were there?
この発明は、上記した問題点を解決するためになされた
ものであって、シリコン基板の第１の表面部分に第１の
金属層を被着してシリサイド−シリコン界面深さが比較
的深くなるようにシリサイド化することにより第１のシ
ョットキー・バリア・ダイオードを形成した後、シリコ
ン基板の第１の表面部分及びそれとは異なる第２の表面
一部分をおおうように第１の金属層とは異種の金属から
なる第２の金属層を被着してシリサイド−シリコン界面
深さが比較的浅くなるようにシリサイド化することによ
り第２の表面部分に第２のショットキーφバリア・ダイ
オードを形成するようにしたことを特徴とするものであ
る。This invention was made to solve the above-mentioned problems, and the silicide-silicon interface depth is relatively deep by depositing a first metal layer on the first surface portion of a silicon substrate. After forming a first Schottky barrier diode by silicidation as shown in FIG. A second Schottky φ barrier diode is formed on the second surface portion by depositing a second metal layer consisting of a metal and silicided so that the silicide-silicon interface depth is relatively shallow. It is characterized by the following.
上記のようにシリサイド−シリコン界面深さを異にする
順次のシリサイド化処理によって複数のショットキー・
バリア・ダイ万一ドを形成すると、基板の不純物濃度を
変えるのではないためリーク温
電流、耐圧、高音での動作マージン等に関して何等問題
を生ずることがない。As mentioned above, multiple Schottky crystals are produced by sequential silicide processing with different depths of the silicide-silicon interface.
If a barrier die is formed, since it does not change the impurity concentration of the substrate, no problems will occur with respect to leakage temperature current, withstand voltage, operating margin at high frequencies, etc.
また、整流接合はシリサイド層とシリコン基板との界面
に形成されるため、金属−シリコン接触の場合のように
表面の不安定性の影響を受けることが少なく、安定した
ダイオード特性が得られる。Furthermore, since the rectifying junction is formed at the interface between the silicide layer and the silicon substrate, it is less affected by surface instability unlike the case of metal-silicon contact, and stable diode characteristics can be obtained.
その上、順方向電圧は、金属材料の選定によってシリサ
イド−シリコン界面の深さを制御することができるので
、所望の順方向電圧を簡単に得ることができ、回路設計
上の要求にきめ細かに対応することができる。Furthermore, the forward voltage can be controlled by selecting the metal material to control the depth of the silicide-silicon interface, making it easy to obtain the desired forward voltage and precisely meeting circuit design requirements. can do.
さらに、第２の金属層は第１のショットキー・バリア・
ダイオードをおおうように被着するので、それをおおわ
ないようにする場合に比べて選択エッチ処理等が不要で
工程が簡単である。しかも、このようにしても、第２の
金属層のシリサイド化は第１の金属層の場合よりもシリ
サイド−シリコン界面深さが浅くなるように行なうので
、第１のショットキー・バリア・ダイオードにおけるノ
々リア・ハイドを変動させないようにすることができる
。Furthermore, the second metal layer is a first Schottky barrier layer.
Since it is deposited so as to cover the diode, there is no need for selective etching and the process is simpler than when the diode is not covered. Moreover, even with this method, the second metal layer is silicided so that the silicide-silicon interface depth is shallower than that of the first metal layer, so the first Schottky barrier diode is It is possible to prevent Nonoria Hyde from changing.
第１図（ａｔ〜（ｆｌは、この発明の一実施例による半
導体装置の製造工程を示すもので、以下、同図（ａ）〜
＋ｆ）の工程を順次に説明する。FIG. 1 (at to (fl) shows the manufacturing process of a semiconductor device according to an embodiment of the present invention, and hereinafter, FIG.
+f) steps will be explained in order.
（ａ）シリコン基板１００表面を熱酸化して５ｉ０２か
ら力る絶縁膜１２ケ形成した後、この絶縁膜１２に通常
のフォトエッチ技術により基板表面部分を露呈させるよ
うな孔を設ける。そして、スノゼツタリング法又は真空
蒸着法を用いて基板上全面に比較的シリサイド形成温度
の高い第１の金属層（例えば白金）１４を被着する。(a) After thermally oxidizing the surface of the silicon substrate 100 to form 12 insulating films starting from 5i02, a hole is formed in the insulating film 12 by a normal photo-etching technique to expose the surface of the substrate. Then, a first metal layer (for example, platinum) 14 having a relatively high silicide formation temperature is deposited on the entire surface of the substrate using a snorting method or a vacuum evaporation method.
ｔｂｌ熱処理を実施して第１の金属層１４ヲシリコン基
板１０と反応させることによシシリサイドーシリコン界
面深さがｄｌである第１のシリサイド層１６を形成する
。そして、第１の金属層１４の未反応部分をエッチ除去
する。A first silicide layer 16 having a silicide-silicon interface depth of dl is formed by performing TBL heat treatment to cause the first metal layer 14 to react with the silicon substrate 10 . Then, the unreacted portions of the first metal layer 14 are removed by etching.
ｔｃ＋フォトレジスト膜１８ヲマスクとして絶縁膜１２
を選択的にエッチすることにより前述の（ａｌの場合と
は異なる基板表面部分を露呈させるような孔を絶縁膜１
２に設ける。tc+ photoresist film 18 and insulating film 12 as a mask.
By selectively etching the insulating film 1, holes are formed that expose a different surface area of the substrate than in the case of (Al).
Provided in 2.
（ｄｌフォトレジスト膜１８ヲ除去した後、前述の（ａ
）の場合と同様にして基板上全面に比較的シリサイド形
成温度の低い第２の金属層（例えばチタン）２０ヲ被着
する。この場合、第２の金属層加の厚さは、次のシリサ
イド化処理でのシリサイド−シリコン界面深さが前述の
シリサイド−シリコン界面深さｄｌ より小てくなる
ように設定される。(After removing the dl photoresist film 18,
) A second metal layer (for example, titanium) 20 having a relatively low silicide formation temperature is deposited on the entire surface of the substrate. In this case, the thickness of the second metal layer is set so that the silicide-silicon interface depth in the next silicidation process is smaller than the silicide-silicon interface depth dl described above.
（ｅｌ熱処理を実施して第２の金属層２０’ｌｋシリコ
ン基板１０と反応させることによりシリサイド−シリコ
ン界面深さがｄｌ より小さいｄ２ である第２のシ
リサイド層２２ヲ形成する。この場合、第１のシリサイ
ド層１６上には第２の金属層加との反応による第３のシ
リツ゛イド層冴が形成されるが、上記のように第２の金
属層加の厚さを設定しておくと、第３のシリサイド層別
が第１のシリサイド層１６の最深部にまで到達してそこ
のバリア・）・イトヲ変動させるのを防ぐことができる
。なお、第２の金属層加の未反応部分はエッチ除去する
。(A second silicide layer 22 having a silicide-silicon interface depth d2 smaller than dl is formed by performing el heat treatment and reacting the second metal layer 20'lk with the silicon substrate 10. A third silicide layer is formed on the first silicide layer 16 by reaction with the second metal layer, but if the thickness of the second metal layer is set as described above, It is possible to prevent the third silicide layer from reaching the deepest part of the first silicide layer 16 and changing the barrier there. Note that the unreacted portions of the second metal layer are removed by etching.
上記の結果、第１のシリサイド層１６とシリコン基板１
０との間には第１のショットキー・バリアーダイオード
が、また第２のシリティド層ρとシリコン基板１０との
間には第２のショットキー・バリア昏ダイオードがそれ
ぞれ形成され、これら第１及び第２のショットキー赤バ
リア・ダイオードは互いに異なる順方向電圧を有するも
のである。As a result of the above, the first silicide layer 16 and the silicon substrate 1
A first Schottky barrier diode is formed between the first silicide layer ρ and the silicon substrate 10, and a second Schottky barrier diode is formed between the second silicided layer ρ and the silicon substrate 10. The second Schottky red barrier diodes have different forward voltages.
（ｆにの後は、例えばＭ等の配線用金属を蒸着してパタ
ーニングすることにより配線層が及び公！形成する。(After step f, a wiring layer is formed by depositing and patterning a wiring metal such as M, for example.
以上のように、この発明によれば、シリサイド−シリコ
ン界面深さケ異にする順次のシリサイド化処理により順
方向電圧の異なる複数のショットキー・／Ｓ リア・ダ
イオ−トン−半導体基板上に形成するようにしたので、
次のような優れた作用効果が得られる。As described above, according to the present invention, a plurality of Schottky/S rear diodes having different forward voltages are formed on a semiconductor substrate by sequential silicidation treatment that varies the depth of the silicide-silicon interface. I decided to do this, so
The following excellent effects can be obtained.
（１）各ダイオード毎に基板表面の不純物濃度ケ変える
のではないため、リーク電流の増大、耐圧の低下、高温
での動作マージン劣化等の問題がない。(1) Since the impurity concentration on the substrate surface is not changed for each diode, there are no problems such as an increase in leakage current, a decrease in breakdown voltage, or a deterioration in the operating margin at high temperatures.
（２）各ダイオード毎にシリサイド−シリコン界面に整
流接合が形成されるので、安定したダイオード特性が得
られる。(2) Since a rectifying junction is formed at the silicide-silicon interface for each diode, stable diode characteristics can be obtained.
（３）各ダイオード毎に金属材料の選定と、シリサイド
−シリコン界面の深さ制御とによって順方向電圧ン決定
できるので、所望の順方向電圧を簡単に得ることができ
る。(3) Since the forward voltage can be determined for each diode by selecting the metal material and controlling the depth of the silicide-silicon interface, the desired forward voltage can be easily obtained.
（４）基板上全面なおおうように第２の金属層を被着で
き、これを選択エッチする必要がないので工程が簡単で
あり、しかも第２のシリサイド層乞第１のシリサイド層
より浅く形成するので第１のショットキー−バリアーダ
イオードにおけるバリア・ハイド変動、すなわち順方向
電圧等の特性変動ケ未然に防止することができる。(4) The second metal layer can be deposited to cover the entire surface of the substrate, and there is no need to selectively etch it, so the process is simple, and the second silicide layer is formed shallower than the first silicide layer. Therefore, barrier-hide fluctuations in the first Schottky barrier diode, that is, fluctuations in characteristics such as forward voltage, can be prevented.
【図面の簡単な説明】
９月
第１図［ａｌ〜（ｆｌは、この発会の一実施例による半
導体装置の製造工程を示す基板断面図であるり１０・・
・シリコン基板、１２・・・絶縁膜、１４・・・第１の
金属層、１６・・・第１のシリサイド層、加・・・第２
の金属層、η・・・第２のシリサイド層。
出願人 日本楽器製造株式会社
代理人 升理士 伊 沢敏昭
第１図[BRIEF DESCRIPTION OF THE DRAWINGS] September 1, FIGS.
- Silicon substrate, 12... Insulating film, 14... First metal layer, 16... First silicide layer, Processing... Second
metal layer, η... second silicide layer. Applicant Nippon Musical Instruments Manufacturing Co., Ltd. Agent Masu Toshiaki Isawa Figure 1
Claims (1)
被着してシリサイド−シリコン界面深さが比較的深くな
るようにシリサイド化することにより第１のショットキ
ー・バリア・ダイオードを形成する工程と、 （ｂ）前記シリコン基板の前記第１の表面部分及びそれ
とは異なる第２の表面部分をおおうように前記第１の金
属層とは異種の金属からなる第２の金属層を被着してシ
リサイド−シリコン界面深さが比較的浅くなるようにシ
リサイド化することにより前記第２の表面部分に第２の
ショットキー・バリア・ダイオードを形成する工程とを
含む半導体装置の製法。[Claims] (a) A first gold layer is deposited on a first surface portion of a silicon substrate and silicided so that the silicide-silicon interface depth is relatively deep. (b) forming a Schottky barrier diode; (b) using a metal different from the first metal layer to cover the first surface portion and a second surface portion different from the first surface portion of the silicon substrate; forming a second Schottky barrier diode on the second surface portion by depositing a second metal layer of Manufacturing methods for semiconductor devices, including
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13964484A JPS6119179A (en) | 1984-07-05 | 1984-07-05 | Manufacture of semiconductor device |
| US06/747,175 US4619035A (en) | 1984-06-23 | 1985-06-21 | Method of manufacturing a semiconductor device including Schottky barrier diodes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13964484A JPS6119179A (en) | 1984-07-05 | 1984-07-05 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6119179A true JPS6119179A (en) | 1986-01-28 |
Family
ID=15250075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13964484A Pending JPS6119179A (en) | 1984-06-23 | 1984-07-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6119179A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4990988A (en) * | 1989-06-09 | 1991-02-05 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Laterally stacked Schottky diodes for infrared sensor applications |
| JPH0478812U (en) * | 1990-11-20 | 1992-07-09 | ||
| JP2007288082A (en) * | 2006-04-20 | 2007-11-01 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5318973A (en) * | 1976-08-05 | 1978-02-21 | Oki Electric Ind Co Ltd | Production of two kinds of schottky barrier diodes |
| JPS59111375A (en) * | 1982-12-08 | 1984-06-27 | エヌ・ベ−・フイリップス・フル−イランペンファブリケン | Semiconductor device and method of producing same |
-
1984
- 1984-07-05 JP JP13964484A patent/JPS6119179A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5318973A (en) * | 1976-08-05 | 1978-02-21 | Oki Electric Ind Co Ltd | Production of two kinds of schottky barrier diodes |
| JPS59111375A (en) * | 1982-12-08 | 1984-06-27 | エヌ・ベ−・フイリップス・フル−イランペンファブリケン | Semiconductor device and method of producing same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4990988A (en) * | 1989-06-09 | 1991-02-05 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Laterally stacked Schottky diodes for infrared sensor applications |
| JPH0478812U (en) * | 1990-11-20 | 1992-07-09 | ||
| JP2007288082A (en) * | 2006-04-20 | 2007-11-01 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
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