JPS618977A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS618977A JPS618977A JP12968184A JP12968184A JPS618977A JP S618977 A JPS618977 A JP S618977A JP 12968184 A JP12968184 A JP 12968184A JP 12968184 A JP12968184 A JP 12968184A JP S618977 A JPS618977 A JP S618977A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- substrate
- silicon substrate
- insulating film
- silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 23
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 abstract description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 2
- 230000006866 deterioration Effects 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 229910052697 platinum Inorganic materials 0.000 abstract description 2
- 239000010936 titanium Substances 0.000 abstract description 2
- 229910052719 titanium Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 238000011282 treatment Methods 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- -1 tantalum (T) Chemical class 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28537—Deposition of Schottky electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体基板上に順方向電圧（ＶＦ）の異な
る複数のショットキー・バリア・ダイオードを有する半
導体装置の製法に関し、シリサイド形成温度ケ異にする
複数種類の金属ン順次にシリサイド化することにより所
望の順方向電圧を有する安定した特性のショットキー・
バリア・ダイオードが得られるようにしたものである。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device having a plurality of Schottky barrier diodes having different forward voltages (VF) on a semiconductor substrate. By sequentially siliciding multiple types of different metals, a Schottky metal with stable characteristics and a desired forward voltage can be produced.
This allows a barrier diode to be obtained.
一般に、ショットキ−０バリア・ダイオードの順方向電
圧はバリア・ハイドによって決まり、このバリア・ハイ
ドは半導体表面の不純物濃度と、半導体表面に接触させ
るべき金属の材料とに依存することはよく知られている
。In general, the forward voltage of a Schottky-0 barrier diode is determined by the barrier hide, and it is well known that this barrier hide depends on the impurity concentration of the semiconductor surface and the metal material that is to be in contact with the semiconductor surface. There is.
従来、シリコン基板上に順方向電圧を異にする複数のシ
ョットキー・バリア・ダイオード２作るにあたっては、
（ａｌシリコン基板表面の不純物濃度を例えばイオン注
入法等により変える方法及び（ｂ）シリコン基板表面に
接触はせるべき金属の材料を変える方法等が知られてい
る。Conventionally, when creating multiple Schottky barrier diodes 2 with different forward voltages on a silicon substrate,
(b) A method of changing the impurity concentration on the surface of the silicon substrate by, for example, an ion implantation method, and (b) a method of changing the material of the metal to be brought into contact with the silicon substrate surface are known.
上記（ａ）の方法によると、順方向電圧を低下でせたシ
ョットキー・バリア・ダイオードでは、リーり電流の増
大、耐圧の低下、高温での動作マージン劣化等の問題点
があった。また、上記ｔｂｌの方法によると、順方向電
圧の低いショットキー・−バリア嗜ダイオード乞形成す
るためにシリコン基板表面にタンタル（Ｔ、）、チタン
−タングステン（Ｔｉ−Ｗ）合金等の金属を接触させて
おシ、表面の不安定性がそのままダイオード特性の不安
定性につ゛ながること、単なる金属材料の選定では所望
の順方向電圧を得難いことなどの問題点があった。According to the above method (a), the Schottky barrier diode with a reduced forward voltage has problems such as an increase in leakage current, a decrease in withstand voltage, and a deterioration in the operating margin at high temperatures. In addition, according to the TBL method described above, metals such as tantalum (T), titanium-tungsten (Ti-W) alloy, etc. are contacted on the silicon substrate surface to form a Schottky-barrier diode with a low forward voltage. Furthermore, there are other problems, such as the instability of the surface directly leading to instability of the diode characteristics, and the difficulty of obtaining a desired forward voltage simply by selecting a metal material.
この発明は、上記した問題点を解決するためになされた
ものであって、シリコン基板の第１の表面部分にシリサ
イド形成温度が比較的高い第１の金属層を被着してシリ
サイド化することにより第１のショットキーΦバリア・
ダイオードを形成した後、シリコン基板の第１の表面部
分とは異なる第２の表面部分にシリサイド形成温度が比
較的低ｌ い第２の金属層を被着してシ
リサイド化することにより第２のショットキー−バリア
・ダイオードを形成するようにしたことを特徴とするも
のである。The present invention has been made to solve the above-mentioned problems, and involves depositing a first metal layer having a relatively high silicide formation temperature on the first surface portion of a silicon substrate to form a silicide. The first Schottky Φ barrier is
After forming the diode, a second metal layer having a relatively low silicide formation temperature is deposited on a second surface portion of the silicon substrate different from the first surface portion, and the second metal layer is silicided. The device is characterized in that a Schottky barrier diode is formed.
上記のようにｊ１迫次のシリサイド化処理によって複数
のショットキー・バリア・ダイオードχ形成すると、基
板の不純物濃度を変えるのでけないためリーク電流、耐
圧、高温での動作マージン等に関して何等問題を生ずる
ことがない、、寸だ、整流接合はシリサイド層とシリコ
ン基板との界面に形成されるため、金属−シリコン接触
の場合のように表面の不安定性の影響を受けることが少
なく、安定したダイオード特性が得られる。その上、順
方向電圧は、金属材料の選定によってシリサイド−シリ
コン界面の深さを制御することができるので、所望の順
方向電圧乞簡単に得ることができ、回路設計上の要求に
きめ細かに対応することかできる。As mentioned above, if multiple Schottky barrier diodes are formed by the subsequent silicidation process, the impurity concentration of the substrate will change, causing problems with leakage current, withstand voltage, operating margin at high temperatures, etc. Since the rectifying junction is formed at the interface between the silicide layer and the silicon substrate, it is less affected by surface instability as in the case of metal-silicon contact, resulting in stable diode characteristics. is obtained. Furthermore, the forward voltage can be controlled by the depth of the silicide-silicon interface by selecting the metal material, so the desired forward voltage can be easily obtained, allowing fine-grained response to circuit design requirements. I can do something.
第１図（ａｔ〜＋ｆｌは、この発明の一実施例による半
。FIG. 1 (at~+fl is a half according to an embodiment of the present invention.
４よ□。ゎ工、。？４（７）ア、ワ□、１３．（８）
□′ｉ〜（ｆ）の工程’＆ １１１ｔ次に説明
するりＩａｌシリコン基板１０の表面暑熱酸化して８ｉ
０２からなる絶縁膜１２Ｙ形成した後、この絶縁膜１２
に通常のフォトエッチ技術により基板表面部分を露呈さ
せるような孔を設ける。そして、スパッタリング法又は
真空蒸着法Ｚ用いて基板上全面に比較的シリサイド形成
温度の高い第１の金属層（例えば白金）１４を被着する
。4, □. Wow,. ? 4 (7) A, W □, 13. (8)
□'Steps i to (f)'& 111t As will be explained next, the surface of the Ial silicon substrate 10 is heated and oxidized to 8i.
After forming the insulating film 12Y made of 0.02, this insulating film 12
A hole is formed in the substrate by a conventional photoetching technique to expose the surface portion of the substrate. Then, a first metal layer (for example, platinum) 14 having a relatively high silicide formation temperature is deposited on the entire surface of the substrate using a sputtering method or a vacuum evaporation method Z.
Ｉｂｌ熱処理ン実施して第１の金属層１４’ｌシリコン
基板１０と反応させることにより第１のシリサイド層１
６ケ形成する。そして、第１の金属層１４の未反応部分
をエッチ除去する。The first silicide layer 1 is formed by performing an Ibl heat treatment to react with the first metal layer 14'l silicon substrate 10.
Form 6 pieces. Then, the unreacted portions of the first metal layer 14 are removed by etching.
ｔｅｌフォトレジスト膜１８ヲマスクとして絶縁膜１２
を選択的にエッチすることにより前述の（ａ）の場合と
は異なる基板表面部分ン露呈させるような孔を絶縁膜１
２に設ける。The insulating film 12 is used as a mask for the tel photoresist film 18.
By selectively etching the insulating film 1, holes are formed that expose a different part of the substrate surface than in the case of (a) above.
Provided in 2.
ｔｄｌフオトレクスト膜１８ヲ除去した後、前述のＩａ
ｌの場合と同様にして基板上全面に比較的シリサイド形
成温度の低い第２の金属層（例えばチタン）２０を被着
する。After removing the tdl photorect film 18, the above-mentioned Ia
A second metal layer (for example, titanium) 20 having a relatively low silicide formation temperature is deposited on the entire surface of the substrate in the same manner as in case 1.
ｔｅｌ熱処理乞実施して第２の金ｇ／％１２ｏｖシ２ノ
コン基板１０と反応でせることにより第２のシリサイド
層２２を形成する。この場合、第１のシリティド層１６
上には第２の金属層加との反応による第３のシリサイド
層Ｕが形成でれるが、矛ｌのシリサイドＪ＠１６の界面
深さｄｌ より第２のシリサイド層加の界面深さｄｚ
を小きくするように処理すれば第３のシリ丈イド層列
が第１のシリサイド層１６の最深部にまで到達するのを
防ぐことができる。なお、第２の金属層加の未反応部分
はエッチ除去する。A second silicide layer 22 is formed by performing a tel heat treatment to react with the second gold g/% 12 ov silicon substrate 10. In this case, the first silicided layer 16
A third silicide layer U is formed on top by reaction with the second metal layer, but the interface depth dz of the second silicide layer is determined from the interface depth dl of the silicide J@16.
By processing to reduce the silicide layer, it is possible to prevent the third silicide layer sequence from reaching the deepest part of the first silicide layer 16. Note that the unreacted portions of the second metal layer are removed by etching.
上記ノ結果、第１のシリサイド層１６とシリコン基板１
０との間には第１のショットキー・バリアーダイオード
が、また第２のシリサイド層ｎとシリコン基板１０との
間には第２のショットキーΦバリア・ダイオードがそれ
ぞれ形成され、これら第１及び第２のショットキー・バ
リア・ダイオードは互いに異なる順方向電圧を有するも
のである。As a result of the above, the first silicide layer 16 and the silicon substrate 1
A first Schottky barrier diode is formed between the first silicide layer n and the silicon substrate 10, and a second Schottky Φ barrier diode is formed between the second silicide layer n and the silicon substrate 10. The second Schottky barrier diodes have different forward voltages.
げ）この後は、例えＩｄ、Ａ１等の配線用金属ヶ蒸着し
てパターニングすることにより配線層あ及び公を形成す
る。(g) After this, wiring metals such as Id and A1 are deposited and patterned to form wiring layers.
以上のように、この発明によれば、＋ｌｌ［次のシリサ
イド化処理により順方向電圧の異なる複数のショットキ
ー・バリア・ダイオードを一半導体基板上に形成するよ
うにしたので、次のような曖れた作用効果が得られる。As described above, according to the present invention, a plurality of Schottky barrier diodes with different forward voltages are formed on one semiconductor substrate by the following silicidation process, so that the following ambiguity is avoided. You can get the desired effect.
（１）各ダイオード毎に基板表面の不純物首席を変える
のではないため、リーク電流の増大、耐圧の低下、高温
での動作マージン劣イ〔等の問題が彦い。(1) Since the main impurity on the substrate surface is not changed for each diode, problems such as increased leakage current, decreased breakdown voltage, and poor operating margin at high temperatures occur.
（２）各ダイオード毎にシリサイド−シリコン界面に整
流接合が形成されるので、安定したダイオード特性が得
られるつ
（３）各ダイオード毎に金属材料の選定と、シリサイド
−シリコン界面の深さ制御とによって順方向電圧を決定
できるので、所望の順方向電圧乞簡単に得ることができ
る。(2) Since a rectifying junction is formed at the silicide-silicon interface for each diode, stable diode characteristics can be obtained. (3) Selection of metal material for each diode and depth control of the silicide-silicon interface Since the forward voltage can be determined by , the desired forward voltage can be easily obtained.
第１図（ａｌ〜ｔｆｌは、この発明の一実施例による半
導体装置の製造工程を示す基板断面図である。
１０・・・シリコン基板、１２・・・絶縁膜、１４・・
・第１の金属層、１６・・・第１のシリサイド層、加・
・・第２の金属層、２２・・・第２のシリサイド層。
出願人 日本楽器製造株式会社
代理人 弁理士 伊沢敏 昭
・デ
第１図
第１図FIG. 1 (al to tfl are cross-sectional views of substrates showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. 10... silicon substrate, 12... insulating film, 14...
・First metal layer, 16...first silicide layer,
...Second metal layer, 22...Second silicide layer. Applicant Nippon Musical Instruments Manufacturing Co., Ltd. Agent Patent Attorney Satoshi Izawa Akira De Figure 1 Figure 1
Claims (1)
温度が比較的高い第１の金属層を被着してシリサイド化
することにより第１のショットキー・バリア・ダイオー
ドを形成する工程と、 （ｂ）前記シリコン基板の前記第１の表面部分とは異な
る第２の表面部分にシリサイド形成温度が比較的低い第
２の金属層を被着してシリサイド化することにより第２
のショットキー・バリア・ダイオードを形成する工程と を含む半導体装置の製法。[Claims] (a) A first Schottky barrier diode is formed by depositing a first metal layer having a relatively high silicide formation temperature on a first surface portion of a silicon substrate and siliciding the first metal layer. (b) depositing a second metal layer having a relatively low silicide formation temperature on a second surface portion of the silicon substrate different from the first surface portion and silicidating the second metal layer; 2
A method for manufacturing a semiconductor device, comprising a step of forming a Schottky barrier diode.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12968184A JPS618977A (en) | 1984-06-23 | 1984-06-23 | Manufacture of semiconductor device |
| US06/747,175 US4619035A (en) | 1984-06-23 | 1985-06-21 | Method of manufacturing a semiconductor device including Schottky barrier diodes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12968184A JPS618977A (en) | 1984-06-23 | 1984-06-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS618977A true JPS618977A (en) | 1986-01-16 |
Family
ID=15015539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12968184A Pending JPS618977A (en) | 1984-06-23 | 1984-06-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS618977A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582772A (en) * | 1991-09-20 | 1993-04-02 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| KR100407369B1 (en) * | 2000-12-25 | 2003-11-28 | 샤프 가부시키가이샤 | Semiconductor device and manufacturing method therefor |
| JP2007288082A (en) * | 2006-04-20 | 2007-11-01 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
| JP2008305599A (en) * | 2007-06-06 | 2008-12-18 | Yazaki Corp | Connector housing and connector |
-
1984
- 1984-06-23 JP JP12968184A patent/JPS618977A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582772A (en) * | 1991-09-20 | 1993-04-02 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| KR100407369B1 (en) * | 2000-12-25 | 2003-11-28 | 샤프 가부시키가이샤 | Semiconductor device and manufacturing method therefor |
| JP2007288082A (en) * | 2006-04-20 | 2007-11-01 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
| JP2008305599A (en) * | 2007-06-06 | 2008-12-18 | Yazaki Corp | Connector housing and connector |
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