JPS63120419A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63120419A JPS63120419A JP26700886A JP26700886A JPS63120419A JP S63120419 A JPS63120419 A JP S63120419A JP 26700886 A JP26700886 A JP 26700886A JP 26700886 A JP26700886 A JP 26700886A JP S63120419 A JPS63120419 A JP S63120419A
- Authority
- JP
- Japan
- Prior art keywords
- silicide
- composition ratio
- layer
- silicon
- rich
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000000203 mixture Substances 0.000 claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 239000010410 layer Substances 0.000 abstract description 15
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 9
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 9
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 239000002356 single layer Substances 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の製造方法、詳しくは、安価で高
性能、高信頼性の配線の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming inexpensive, high-performance, and highly reliable wiring.
従来の技術
従来、半導体集積回路において、配線材料としてポリシ
リコンとシリサイドとの二層からなる、通称、ポリサイ
ドが多（使われている。これは、ポリシリコン単層配線
では、その抵抗値が高いために、その上に低抵抗のシリ
サイド層を蒸着して配線の低抵抗化をはかろうとするも
のである。ポリサイド構造の配線を使った半導体集積回
路を第２図に示す。Conventional technology Conventionally, in semiconductor integrated circuits, polycide, which is made up of two layers of polysilicon and silicide, is often used as a wiring material. Therefore, an attempt is made to reduce the resistance of the interconnect by depositing a low-resistance silicide layer thereon.A semiconductor integrated circuit using interconnects having a polycide structure is shown in FIG.
発明が解決しようとする問題点
しかし、このような構造においては、配線形成工程でポ
リシリコンとシリサイドとの二層を蒸着するためコスト
が高（なる。また、ポリサイド配線のパターニングを行
なう時に、二層構造のために、ドライエツチングが複雑
になり、配線の性能および信頼性で問題がある。また、
シリサイド単層を配線として用いた場合には、シリサイ
ドと下地の酸化シリコン膜の密着性が悪いために信頼性
で問題がある。Problems to be Solved by the Invention However, in such a structure, the cost is high because two layers of polysilicon and silicide are vapor-deposited in the interconnect formation process.Also, when patterning the polycide interconnect, The layer structure complicates dry etching and poses problems in interconnect performance and reliability.
When a single layer of silicide is used as a wiring, there is a problem in reliability due to poor adhesion between the silicide and the underlying silicon oxide film.
本発明は、このような問題を解決するもので、シリサイ
ド単層配線で良好な配線を形成することを目的とするも
のである。The present invention is intended to solve such problems, and aims to form good wiring using a single-layer silicide wiring.
問題点を解決するための手段
本発明は、コンタクトをとるシリコンまたはポリシリコ
ン１−に、組成比を変化させながら、好ましくは、Ｆ肩
部でシリコンリッチ、８ト層部でメタルリッチに制御し
て、シリサイドを蒸着する工程をそなえたものである。Means for Solving the Problems The present invention preferably controls silicon or polysilicon 1- to be in contact to be silicon-rich in the F shoulder region and metal-rich in the 8-T layer region while changing the composition ratio. It also includes a process of vapor depositing silicide.
作用
この製造方法によれば、シリサイド即層で配線が形成さ
れ、さらに、シリサイドの組成比を変えながら蒸着し２
シリザイド膜の密着性が良くなり、かつ、抵抗も低いた
めに、安価で高性能、高信頼性の配線が形成される。Function: According to this manufacturing method, wiring is formed using an immediate layer of silicide, and the silicide is further vapor-deposited while changing the composition ratio.
Since the adhesion of the silicide film is improved and the resistance is low, inexpensive, high performance, and highly reliable wiring can be formed.
実施例
本発明の半導体装置の製造方法の一実施例を第１図ａ〜
Ｃを参照して説明する。Embodiment An embodiment of the method for manufacturing a semiconductor device of the present invention is shown in FIGS.
This will be explained with reference to C.
まず、第１図３のように、Ｐ形単結晶シリコン基板１の
上に、フォトレジスト（図示せず）を塗布し、Ｎ形波散
層２を形成したい領域のみを、露光、現像により開孔す
る。次に、このフォトレジストをマスクにして、イオン
注入法により、ヒ素」：たはリンを注入し、その後、ア
ニールを行なってＮ形波散層２を形成する。その後、フ
ォトレジストを除去する。First, as shown in FIG. 1, a photoresist (not shown) is coated on a P-type single crystal silicon substrate 1, and only the area where the N-type scattering layer 2 is to be formed is exposed and developed. make a hole Next, using this photoresist as a mask, arsenic or phosphorus is implanted by ion implantation, and then annealing is performed to form the N-type wave dispersion layer 2. After that, the photoresist is removed.
次いで、第１図すのように、酸化シリコン膜３を全面に
２０００〜５０００Ａ蒸着し、アニールを行なう。フＡ
トリソゲラフイーによりＮ形波散層２の上部のみ開孔し
、レジストをマスクにして酸化シリ：Ｊン膜３を１くラ
イエッヂ法によりエツチングする。その後、フォトレジ
ストを除去する。Next, as shown in FIG. 1, a silicon oxide film 3 of 2000 to 5000 A is deposited over the entire surface and annealed. F A
A hole is formed only in the upper part of the N-type scattering layer 2 by trisogeraphy, and the silicon oxide film 3 is etched by a lie-edge method using a resist as a mask. After that, the photoresist is removed.
次に、第１図Ｃのように、Ｎ形波散層２の十に形成され
る自然酸化膜をフッ酸溶液で除去後シリサイド１Ｊｕ４
を蒸着する。シリ・す゛イド膜の種類はモリブデンシリ
′リイド、タングスデンシリザイド。Next, as shown in FIG.
Deposit. The types of silicide films are molybdenum silicide and tungsten silicide.
チタンシリサイド等があり、蒸着方法にはスパッタ法、
ＣＶＤ法等があるが、ここではＣＶＤ法によるタングス
テンシリサイド膜の場合を例にして説明する。ＣＶＤ法
において、圧力は１００〜３００ｍＴｏｒｒ 、温度は
３００〜４００℃、反応キャリアガスはＨｅまたはＡｒ
を用いる。また、反応ガスとしてはシラン（ＳｉＨ４）
と六弗化タングステン（Ｗ Ｆ ｅ ）を用いる。反応
の初期においては、ＳｉＨ４に対するＷ Ｆ ｓの流量
比を小さくして、形成するタングステンシリサイド（Ｗ
Ｓｉｘ）をシリコンリッチにする。組成比としてはｘ＝
３．０以」−とする。このようにすることで密着性が良
くなる。その後、少しずつＳ ＋、 Ｈ４に対するＷＦ
Ｇの流量比を大きくしてメタルリッチにする。組成比と
してはｘ＝２．４前後にする。このようにすると膜の比
抵抗が低（なる。したがって、タングステンシリサイド
膜４は、下の方でシリコンリッチ上の方でメタルリッチ
となる。トータルの膜厚は２０００〜４０００Ａとする
。その後、９００℃以上の温度でアニールを行ない、タ
ングステンシリサイド膜４のシート抵抗を下げる。There are titanium silicides, etc., and vapor deposition methods include sputtering,
Although there are methods such as CVD, here, a case of forming a tungsten silicide film by the CVD method will be explained as an example. In the CVD method, the pressure is 100 to 300 mTorr, the temperature is 300 to 400°C, and the reaction carrier gas is He or Ar.
Use. In addition, silane (SiH4) is used as a reaction gas.
and tungsten hexafluoride (W Fe ). In the early stage of the reaction, the flow rate ratio of WFs to SiH4 is made small to reduce the tungsten silicide (W
Six) to be silicon-rich. The composition ratio is x=
3.0 or higher”-. This improves adhesion. After that, S +, WF for H4 little by little
Increase the flow rate ratio of G to make it metal rich. The composition ratio is set to be around x=2.4. By doing this, the specific resistance of the film becomes low. Therefore, the tungsten silicide film 4 becomes silicon-rich at the bottom and metal-rich at the upper part.The total film thickness is set to 2000 to 4000A. Annealing is performed at a temperature of .degree. C. or higher to lower the sheet resistance of the tungsten silicide film 4.
以上説明した半導体装置の製造方法では、安価で高性能
、高信頼性の配線形成が可能となる。The method for manufacturing a semiconductor device described above enables formation of inexpensive, high-performance, and highly reliable wiring.
発明の効果
本発明の半導体装置の製造方法によれば、配線を二層で
行なう必要がな（、かつ膜の密着性が良く、また、抵抗
も低いために安価で高性能、高信頼性の配線形成が可能
となる。Effects of the Invention According to the method for manufacturing a semiconductor device of the present invention, it is not necessary to conduct wiring in two layers (and the film has good adhesion and low resistance, so it is possible to achieve low cost, high performance, and high reliability. Wiring formation becomes possible.
第１図ａ −ｃは本発明実施例の工程順断面図、第２図
は従来例半導体装置の断面図である。
■・・・・・・Ｐ形ＪＩｔ結晶シリコン基板、２・・・
・・・Ｎ形波散層、３・・・・・・酸化シリコン膜、４
・・・・・・タングステンシリサイド膜、５・・・・・
・ポリシリコン膜。
代理人の氏名 弁理士 中尾敏男 はがＪ−名−−６＝1A to 1C are cross-sectional views in the order of steps of an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a conventional semiconductor device. ■・・・P-type JIt crystal silicon substrate, 2...
...N-type wave dispersion layer, 3...Silicon oxide film, 4
...Tungsten silicide film, 5...
・Polysilicon film. Name of agent Patent attorney Toshio Nakao HagaJ-name--6=
Claims (3)
コンタクトを形成する場合に、前記シリサイドの組成比
を変化させながら堆積する工程を具備することを特徴と
する半導体装置の製造方法。(1) A method for manufacturing a semiconductor device, comprising the step of depositing the silicide while changing its composition ratio when forming a contact between a silicon or polysilicon layer and a silicide layer.
なるように制御される特許請求の範囲第（１）項記載の
半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim (1), wherein the composition ratio of the silicide layer is controlled so that the lower portion is silicon-rich.
．０以上、上部でＷ：Ｓｉ＝１：２．４程度に制御され
る特許請求の範囲第（１）項または第（２）項記載の半
導体装置の製造方法。(3) The composition ratio of the silicide layer is W:Si=1:3 at the bottom
．． The method for manufacturing a semiconductor device according to claim 1 or claim 2, wherein W:Si is controlled to be approximately 0 or more and W:Si=1:2.4 in the upper part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26700886A JPS63120419A (en) | 1986-11-10 | 1986-11-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26700886A JPS63120419A (en) | 1986-11-10 | 1986-11-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63120419A true JPS63120419A (en) | 1988-05-24 |
Family
ID=17438775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26700886A Pending JPS63120419A (en) | 1986-11-10 | 1986-11-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63120419A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02194524A (en) * | 1988-12-24 | 1990-08-01 | Samsung Electron Co Ltd | Method of ferming low resistance connection at low resistance area of vlsi device |
| US5780360A (en) * | 1994-09-27 | 1998-07-14 | Applied Materials, Inc. | Purge in silicide deposition processes dichlorosilane |
| EP0905752A2 (en) * | 1997-09-29 | 1999-03-31 | LG Semicon Co., Ltd. | Method for fabricating conductive electrode for semiconductor device |
| KR100243291B1 (en) * | 1997-04-30 | 2000-03-02 | 윤종용 | Method for forming silicide layers in processes fabricating a semiconductor device |
| US6103606A (en) * | 1996-09-21 | 2000-08-15 | United Microelectronics Corp. | Method of fabricating a word line |
| US6210813B1 (en) | 1998-09-02 | 2001-04-03 | Micron Technology, Inc. | Forming metal silicide resistant to subsequent thermal processing |
-
1986
- 1986-11-10 JP JP26700886A patent/JPS63120419A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02194524A (en) * | 1988-12-24 | 1990-08-01 | Samsung Electron Co Ltd | Method of ferming low resistance connection at low resistance area of vlsi device |
| US5780360A (en) * | 1994-09-27 | 1998-07-14 | Applied Materials, Inc. | Purge in silicide deposition processes dichlorosilane |
| US5817576A (en) * | 1994-09-27 | 1998-10-06 | Applied Materials, Inc. | Utilization of SiH4 soak and purge in deposition processes |
| US6193813B1 (en) | 1994-09-27 | 2001-02-27 | Applied Materials, Inc. | Utilization of SiH4 soak and purge in deposition processes |
| US6103606A (en) * | 1996-09-21 | 2000-08-15 | United Microelectronics Corp. | Method of fabricating a word line |
| KR100243291B1 (en) * | 1997-04-30 | 2000-03-02 | 윤종용 | Method for forming silicide layers in processes fabricating a semiconductor device |
| US6124202A (en) * | 1997-04-30 | 2000-09-26 | Samsung Electronics Co. | Methods of fabricating silicide layers and silicide contact structures in microelectronic devices |
| EP0905752A2 (en) * | 1997-09-29 | 1999-03-31 | LG Semicon Co., Ltd. | Method for fabricating conductive electrode for semiconductor device |
| EP0905752A3 (en) * | 1997-09-29 | 1999-10-13 | LG Semicon Co., Ltd. | Method for fabricating conductive electrode for semiconductor device |
| US6210813B1 (en) | 1998-09-02 | 2001-04-03 | Micron Technology, Inc. | Forming metal silicide resistant to subsequent thermal processing |
| US6537910B1 (en) | 1998-09-02 | 2003-03-25 | Micron Technology, Inc. | Forming metal silicide resistant to subsequent thermal processing |
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