JPS63298656A - 二重化された入出力制御装置 - Google Patents

二重化された入出力制御装置

Info

Publication number
JPS63298656A
JPS63298656A JP62136782A JP13678287A JPS63298656A JP S63298656 A JPS63298656 A JP S63298656A JP 62136782 A JP62136782 A JP 62136782A JP 13678287 A JP13678287 A JP 13678287A JP S63298656 A JPS63298656 A JP S63298656A
Authority
JP
Japan
Prior art keywords
input
connection
output
output device
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62136782A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0461385B2 (enrdf_load_stackoverflow
Inventor
Fumiaki Tahira
田平　文明
Kazuo Sumiya
炭谷　和男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62136782A priority Critical patent/JPS63298656A/ja
Publication of JPS63298656A publication Critical patent/JPS63298656A/ja
Publication of JPH0461385B2 publication Critical patent/JPH0461385B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Hardware Redundancy (AREA)
JP62136782A 1987-05-29 1987-05-29 二重化された入出力制御装置 Granted JPS63298656A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62136782A JPS63298656A (ja) 1987-05-29 1987-05-29 二重化された入出力制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62136782A JPS63298656A (ja) 1987-05-29 1987-05-29 二重化された入出力制御装置

Publications (2)

Publication Number Publication Date
JPS63298656A true JPS63298656A (ja) 1988-12-06
JPH0461385B2 JPH0461385B2 (enrdf_load_stackoverflow) 1992-09-30

Family

ID=15183391

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62136782A Granted JPS63298656A (ja) 1987-05-29 1987-05-29 二重化された入出力制御装置

Country Status (1)

Country Link
JP (1) JPS63298656A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006277250A (ja) * 2005-03-29 2006-10-12 Nec Corp 情報処理装置およびデータ通信制御方法
WO2012114498A1 (ja) * 2011-02-24 2012-08-30 富士通株式会社 情報処理装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006277250A (ja) * 2005-03-29 2006-10-12 Nec Corp 情報処理装置およびデータ通信制御方法
WO2012114498A1 (ja) * 2011-02-24 2012-08-30 富士通株式会社 情報処理装置
JP5733384B2 (ja) * 2011-02-24 2015-06-10 富士通株式会社 情報処理装置

Also Published As

Publication number Publication date
JPH0461385B2 (enrdf_load_stackoverflow) 1992-09-30

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