JPS6329294B2 - - Google Patents

Info

Publication number
JPS6329294B2
JPS6329294B2 JP57006653A JP665382A JPS6329294B2 JP S6329294 B2 JPS6329294 B2 JP S6329294B2 JP 57006653 A JP57006653 A JP 57006653A JP 665382 A JP665382 A JP 665382A JP S6329294 B2 JPS6329294 B2 JP S6329294B2
Authority
JP
Japan
Prior art keywords
cpu
write
access
buffer memory
ram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57006653A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58123138A (ja
Inventor
Toshio Imao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP57006653A priority Critical patent/JPS58123138A/ja
Publication of JPS58123138A publication Critical patent/JPS58123138A/ja
Publication of JPS6329294B2 publication Critical patent/JPS6329294B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)
JP57006653A 1982-01-18 1982-01-18 表示用メモリ制御方式 Granted JPS58123138A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57006653A JPS58123138A (ja) 1982-01-18 1982-01-18 表示用メモリ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57006653A JPS58123138A (ja) 1982-01-18 1982-01-18 表示用メモリ制御方式

Publications (2)

Publication Number Publication Date
JPS58123138A JPS58123138A (ja) 1983-07-22
JPS6329294B2 true JPS6329294B2 (OSRAM) 1988-06-13

Family

ID=11644335

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57006653A Granted JPS58123138A (ja) 1982-01-18 1982-01-18 表示用メモリ制御方式

Country Status (1)

Country Link
JP (1) JPS58123138A (OSRAM)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0192139A3 (en) * 1985-02-19 1990-04-25 Tektronix, Inc. Frame buffer memory controller
JPS62115189A (ja) * 1985-11-14 1987-05-26 日本電気株式会社 Ｃｒｔ制御器
JPS6392995A (ja) * 1986-10-08 1988-04-23 セイコーインスツルメンツ株式会社 デイスプレイ用ルツクアツプテ−ブルバツフア装置
JPS63104084A (ja) * 1986-10-22 1988-05-09 株式会社日立製作所 Ｃｒｔコントロ−ラ
US6091432A (en) * 1998-03-31 2000-07-18 Hewlett-Packard Company Method and apparatus for improved block transfers in computer graphics frame buffers

Also Published As

Publication number Publication date
JPS58123138A (ja) 1983-07-22

Similar Documents

Publication Publication Date Title
US5816921A (en) Data transferring device and video game apparatus using the same
US5507005A (en) Data transferring system between host and I/O using a main buffer with sub-buffers where quantity of data in sub-buffers determine access requests
US5682522A (en) Shared memory architecture of graphics frame buffer and hard disk cache
US4757441A (en) Logical arrangement for controlling use of different system displays by main proessor and coprocessor
US4833596A (en) Logical arrangement for controlling use of different system displays by main processor and co-processor
JPS6244303B2 (OSRAM)
US5625778A (en) Method and apparatus for presenting an access request from a computer system bus to a system resource with reduced latency
US6313845B1 (en) Method and apparatus for transporting information to a graphic accelerator card
JPS6329294B2 (OSRAM)
US5748203A (en) Computer system architecture that incorporates display memory into system memory
EP0482263A2 (en) Video memory system with intermediate buffer
JPH10333659A (ja) メモリ制御方法及び装置
JPS59178487A (ja) デイスプレイ装置
JPH0728990A (ja) グラフィックスメモリアクセス回路
JPS63245716A (ja) マルチウインドウ表示装置
JP3259095B2 (ja) データ転送方法
JPH06103026A (ja) メモリシステム
JPS60251431A (ja) メモリ表示装置
JPS63305447A (ja) メモリアクセス制御回路
JPH0727556B2 (ja) バスアクセス方式
KR0148894B1 (ko) 그래픽스 가속 시스템
JPH04359290A (ja) 中間バッファをもつビデオ用メモリシステムおよびメモリの表示方法
JPS5819965A (ja) 記録装置
JPS6169093A (ja) トグルｖｒａｍ制御方式
KR19980054412A (ko) 단일 메모리 구조의 병목현상을 개선한 그래픽 시스템