JPS6329294B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display memory control method for accessing the memory of a cathode ray tube display device.

Conventionally, in small-scale computer systems such as microcomputers, the video signal generator (V-RAM), which stores data corresponding to the screen displayed on the cathode ray tube (CRT), is the main part of the central processing unit (CPU). Set this V-RAM as part of the memory and connect it to the CPU bus line (CPU-BUS).
Write and read access directly from the V side, and
- Periodically read and access RAM from the CRT side to refresh the CRT screen. Therefore,
Since V-RAM is accessed from both the CPU-BUS side and the CRT side, countermeasures are required in case of conflict between the two. As a countermeasure for this, CPU-BUS
There is a method that gives priority to access from the side, but in this method, each time there is a conflict between the two,
Access from the CRT side is interrupted, causing noise on the CRT screen. In addition, as another measure, V
- There is a method in which the access period to RAM is time-divided between both parties, but in this method, each time an access from the CPU-BUS side occurs during the period allocated to the CRT side, that access waits for timing. This reduces the processing power of the CPU. When time-sharing the access period to V-RAM, the CRT raster retrace period that is not related to the CRT screen display is used as the access period from the PU-BUS side, and the CRT display period is used as the access period from the CRT side. If you allocate each, even if they conflict,
Noise does not occur on the CRT screen, but accesses from the CPU-BUS side that occur during the CRT display period require a considerable amount of time to wait for timing.
The CPU's processing power decreases significantly. Also, V
- Divide the access period to RAM into two, taking into account the access time from the CPU-BUS side and the access cycle from the CRT side, one half as the access period from the CPU-BUS side and the other as the access period from the CRT side. By assigning them to each, it is possible to prevent noise from occurring on the CRT screen, shorten the timing wait time for access from the CPU-BUS side, and reduce the decrease in CPU processing performance. , the access cycle from the CRT side, i.e.
Since the configuration of the CRT screen is affected by the access time from the CPU-BUS side, that is, the characteristics of the computer system itself, there are many restrictions and complicated timing control must be performed.

The purpose of the present invention is to eliminate the above-mentioned conventional drawbacks and to provide CRTs without complicated timing control.
Prevents noise from occurring on the screen and reduces CPU
Due to waiting timing for access from BUS side
It is an object of the present invention to provide a display memory control method that can eliminate or reduce a decrease in processing power of a CPU.

As shown in the principle diagram of FIG.
Separately from the display portion 2 of the main memory 1 of the CPU, a V-RAM 13 is provided which overlaps with the display portion 2 of the main memory 1 of the CPU.
A buffer memory 9 is provided to temporarily store the contents written to the RAM 13. Writing from the CPU-BUS side is performed to the display portion 2 of the main memory and the buffer memory 9, and reading from the CPU-BUS side is performed to the main memory. A display memory control method characterized in that reading from the display part 2 is performed, reading from the CRT side is performed from the V-RAM 13, and writing is performed from the buffer memory 9 to the V-RAM 13 when reading from the CRT side is not being performed. It is.

In the display memory control method of the present invention, a V-RAM is provided separately from the display portion of the main memory, and access from the CPU-BUS side is performed to the display portion of the main memory, and from the CRT side. accesses are made to V-RAM, so if the buffer memory, which requires a slight temporal shift in write access from the CPU-BUS side to V-RAM, has sufficient capacity so that it does not always become saturated,
There is no need to wait for a timing for write access from the CPU-BUS side, and there is no reduction in CPU processing ability due to the timing wait. If the buffer memory does not have sufficient capacity to avoid constant saturation, each time the buffer memory becomes saturated, write access from the CPU-BUS side must wait until the saturation state is released. The waiting time can be shortened by increasing the capacity of the buffer memory, and therefore, it is possible to reduce the decrease in CPU processing performance due to waiting for the timing of write access from the CPU-BUS side. Moreover,
The timing wait for write access from the CPU-BUS side is until the saturation state of the buffer memory is released, and the access cycle from the CRT side and
Since it is not directly related to and independent of the access time from the CPU-BUS side, complicated timing control is not required. Also, V-RAM is
Data is written from the buffer memory when reading from the CRT side is not being performed, and reading from the CRT side is not interrupted, so no noise is generated on the CRT screen.

Next, examples of the present invention will be described.

First Embodiment (See FIG. 2) This example is an example in which the buffer memory has sufficient capacity so as not to be saturated at all times, and there is no need to wait for timing for write access from the CPU-BUS side. As shown in FIG. 2, apart from the display portion 2 of the main memory 1 of the CPU, a V-RAM 13 having an address that overlaps with the main memory 1 is provided.
A buffer memory 9 is provided to temporarily store write data and write addresses to the buffer memory 9.
First-in-first-out memory (FiFo) is used to read the written contents in the order in which they were written.
The data line 4 and address line 5 in the CPU-BUS 3 are connected to the buffer memory 9, the write command line 6 in the CPU-BUS is connected to the input terminal of the AND gate 7, and a part of the address line 5 is connected to the decoder 8. The AND gate 7 is connected to the input terminal of the AND gate 7 through the input terminal of the AND gate 7 to determine a write command to the V-RAM 13 or the display portion 2 of the main memory from among write commands.
Connect the output end of the buffer memory 9 to the buffer memory 9, and connect the write data line 10 of the buffer memory 9 to the V-RAM 13.
and write address line 11 of the buffer memory.
Connect the address switch 15 to the CRT2
The read address line 17 of the control unit 16 connected to
and switch control line 18 are connected to the address changeover switch 15, respectively, and the address changeover switch 15 is connected to the address changeover switch 15.
is connected to the V-RAM 13, the read data line 14 of the V-RAM is connected to the control section 16, the write request signal line 12 of the buffer memory is connected to the control section 16, and the write signal line 19 of the control section is connected to the V-RAM. - It is connected to the RAM 13, and the write end signal line 20 of the control section is connected to the buffer memory 9.

CPU-BUS cycle is started and V-RAM1
3 or when there is a write command to the display portion 2 of the main memory, the AND gate 7 outputs a command to write to the buffer memory 9, and the buffer memory 9 stores the data and address from the data line 4 and address line 5. On the other hand, the display part 2 of the main memory
store the same data at the same address. CPU
-When there is a command to read this data from the BUS side,
Data stored in the display portion 2 of the main memory is read out. The control unit 16 time-divides write access to the V-RAM 13 and read access from the V-RAM 13, and connects the address changeover switch 15 to the write address line 11 during the write period, and connects the address switch 15 to the write address line 11 during the read period. The changeover switch 15 is connected to the read address line 17. When a write request is sent to the control unit 16 from the write request signal line 12 of the buffer memory during the write period, the write signal line 1 of the control unit
Writing is commanded from 9 to V-RAM13, and V-
RAM13 is buffer memory write data line 1
The data from 0 is stored in the write address line 11 of the buffer memory and the address from the address changeover switch 15, and is transferred from the buffer memory 9 to the V-RAM1.
When the writing to the buffer memory 9 is completed, the writing end signal line 20 of the control section notifies the buffer memory 9 of the end of writing. During the read period, the data in the V-RAM 13 stored in the read address line 17 of the control section and the address position from the address changeover switch 15 is read out to the control section 16 via the read data line 14 of the V-RAM. In the control unit 16, the CRT2
1 signal and displayed on the CRT21 screen.

In the display memory control method of this example,
Write access from the CPU-BUS side does not wait for timing, so
There is no decrease in CPU processing power. Furthermore, unlike the conventional method in which read access from the CRT side is interrupted due to access conflict, no noise is generated on the CRT screen due to interruption of read access from the CRT side. Furthermore, the access cycle from the CRT side is
Unlike the conventional method, which is affected by the access time from the BUS side, it is not directly related to and independent of the characteristics of the computer system itself, such as the access time from the CPU-BUS side, so it is not complex. No timing control is required, and it can be easily attached to a computer system by simply connecting it to the CPU-BUS data line, address line, and write command line.

Second Embodiment (See FIG. 3) This example is an example in which the buffer memory does not have sufficient capacity to avoid saturation at all times, and write access from the CPU-BUS side is made to wait for timing. To explain the difference from the previous example, as shown in Fig. 3, a data register 9d with a capacity of 1 word and an address register 9a with the same capacity are used in the buffer memory, and from a write command from the CPU-BUS3 side. Determine the write command to V-RAM 13 or main memory display section 2
Connect the output terminal of AND gate 7 to data register 9
The write request signal line 12 connected to the input terminal of the D-type flip-flop (DFF) gate 22 and the output terminal of the DFF gate 22 is connected to the control unit 1.
6 and connect the write end signal line 20 of the control unit to
Connected to the reset end of the DFF gate 22, and
Connect the output end of the DFF gate 22 to the input end of the AND gate 23, and connect the BUS of the Z80 micro CPU.
Main memory request signal (MREQ) line 24 in 3
is connected to the input terminal of the AND gate 23 and outputs a timing wait signal only when the CPU is accessing the main memory 1.The output terminal of the AND gate 23 is connected to the wait signal (WAIT) line 25 in the CPU-BUS.
is connected to. Other points are the same as those in the previous example, so the same reference numerals are given in FIG.

At the moment when the AND gate 7 for write command outputs and the output disappears, the data register 9d and the address register 9a respectively store data and address, and the DFF gate 22 is set and the DFF gate 22 outputs a write request signal to the control unit 16, and the DFF gate 22
A signal indicating the saturation state of the buffer memories 9d and 9a is output to the timing wait AND gate 23, and the timing wait AND gate 23 input from the MREQ line 24 outputs WAIT.
A wait signal is input to line 25, and write access from the CPU-BUS side is made to wait for a timing.
When the writing from the buffer memories 9d, 9a to the V-RAM 13 is completed, the buffer memories 9d, 9a
While the saturation state of a is canceled, the control unit 16
A write end signal is output to the DFF gate 22,
The DFF gate 22 is reset, the AND gate 23 waiting for timing no longer receives input from the DFF gate 22 and outputs no output, and no wait signal is input to the WAIT line 25, so that the timing wait is canceled.

In the display memory control method of this example, the buffer memory capacity is the minimum, so the CPU
Write access from the BUS side requires a long timing wait time, but the timing wait time can be shortened by increasing the buffer memory capacity;
Decrease in CPU processing power can be reduced.
Moreover, the timing wait is until the buffer memory is released from the saturated state, and no complicated timing control is required. Also, CPU-BUS
It can be easily attached to a computer system by simply connecting it to the data line, address line, write command line, request line, and standby signal line.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle of the invention, FIG. 2 is a block diagram of a first embodiment of the invention, and FIG. 3 is a block diagram of a second embodiment of the invention. 1: Main memory, 2: Display part, 3:
CPU-BUS, central processing unit bus line, 9,
9d, 9a: buffer memory, 13: V-
RAM, video signal generator, 21: CRT, cathode ray tube.

Claims (1)

[Claims] 1. A video signal generator is provided that is separate from the display portion of the main memory of the central processing unit and overlaps with it.
A buffer memory is provided to temporarily store the contents written to the video signal generator, and writing from the bus line side of the central processing unit is performed to the display part of the main memory and buffer memory, and from the bus line side of the central processing unit. Reading is performed from the display portion of the main memory, reading from the cathode ray tube side is performed from the video signal generator, and writing from the buffer memory to the video signal generator is performed when reading from the cathode ray tube side is not being performed. Characteristic display memory control method.