JPS58123138A - Memory controlling system for display - Google Patents

Abstract

PURPOSE:To prevent the generation of noises on a CRT screen and at the same time to avoid the deterioration of the CPU processing capacity due to the queuing for the timing of an access given from the CPU-BUS side without using any complicated timing control. CONSTITUTION:A V-RAM13 overlapping a display part 2 of a main memory 1 of a CPU is provided separately from said display part 2. A buffer memory 9 stores temporarily the contents written to the V-RAM13. Then the writing is carried out to the part 2 and the memory 9 from the CPU-BUS side, and the reading is carried out from the CPU-BUS side through the part 2. At the same time, the writing is carried out to the V-RAM13 from the memory 9 in case no reading is carried out from the CRT side.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display memory control method for accessing the memory of a cathode ray tube display device.

Conventionally, in small-scale computer systems such as microcomputers, a video signal generator (V-M) that stores data corresponding to the screen displayed on a cathode ray tube (CRT) is used as a central processing unit (ERU). This V-R program is set in a part of the main memory of the
(Direct write and read access from the (3FU-BH3) side, and read access from the CRT side periodically to refresh the V-RAMrtCRT picture. Therefore, the V-RAM is accessed directly from the CPU-Bus side and from the CRT side.
Since it is accessed from both RT sides, countermeasures are required in case of conflict between the two. As a countermeasure for this, CPU-B
There is a method that gives priority to access from the O2 side,
In this method, each time there is a conflict between the two, the access from the CRT side is interrupted, causing noise on the CRT screen.Another countermeasure is to time-share the access period to the V-RAM between the two. There is a method, but in this method, (3PU
- Every time an access occurs from the BO2 side, the access must wait for a timing (the processing capacity of the 3PU decreases).

V - In time-sharing the access period to RAM.

CRT CRT not related to screen display g) Raster retrace period pIf you assign 7 periods to the access from the CPU-BU8 side and the CRT display period to the access period from the CRT side, the CRT will not be affected even if the two conflict. Noise does not occur on the CRT screen, but the timing wait time for access from the CPU-BUS side that occurs during the CRT display period becomes considerably long.

The processing capacity of the CPU will decrease significantly. In addition, the access period to ■-Ram M is divided into two (taking into consideration the access time from the 3PU-BUS side and the access cycle from the CRT side, one is the access period from the CPU-BUS side, and the other is the access period from the CPU-BUS side. (By allocating each to the access period from the 311LT side, it is possible to prevent the generation of noise on the CjRT screen, shorten the timing waiting time for access from the CPU-BUS side, and reduce the decrease in CPU processing performance. is possible, but T, Kashi, CRT
The access cycle from the side, that is, the configuration of the first side of the CRTi is the CPU
- Since it is affected by the access time from the BUS side, that is, the characteristics of the computer system itself, there are many restrictions and complicated timing control must be performed.

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the conventional technology, to prevent noise from occurring on a CRT screen without using complicated timing control, and to prevent the generation of noise on a CRT screen by waiting for the timing of access from the CPU-BUS side. It is an object of the present invention to provide a display memory control method that can eliminate or reduce a decrease in the processing capacity of an OPU.

As shown in the principle diagram in the figure @, the present invention has a main memory (1) of the OPU that is separate from the display part (2) and has a part overlapping with it.
it, &V-RAM (13'ft installation'ff, V-
RAM Q3 Q') A buffer memory (9) is provided to temporarily store the written contents, and writing from the CPU-BUS side is performed to the display part (2) of the main memory and the buffer memory (9). C! Reading from the PU-BUS side is performed from the display part (2) of the main memory, and
Squeezing from the R and T sides is done from V-RAM (from Ll,
This is a display memory control system characterized in that data is written from the buffer memory (9) to V-RAMQ3 when successive output from the 0IILT side is not performed.

In the display memory control system of the present invention, a V-IL memory M is provided separately from the display portion of the main memory, and the CP
Access from the U-BUS side is to the display part of the main memory (access from the CRT side
jV-RAM)-c', CPU
-BUS side power G, V -RAM
There is no need to wait for a timing for write access from the S side, and there is no reduction in CPU processing power due to the timing wait. ) If the buffer memory does not have enough capacity to keep it from becoming saturated, each time the buffer memory becomes saturated, the CPU-B
Although it is necessary to wait for a timing for write access from the US side, the timing waiting time can be shortened by increasing the capacity of the sofa memory. PU-BUS @-71. It is possible to reduce the decrease in CPU processing performance caused by waiting for the timing of write access from the CPU.
There is no need to wait for the timing of write access from the BUS side until the saturation state of the buffer memory is released.
Since it is not directly related to and independent of the access cycle from the CRT side and the access time from the CPU-BUS side, there is no need for complicated timing control.
-RAM is written from the buffer memory when no reading is being performed from the CRT side, and reading from OR?@ is not interrupted, so no noise is generated on the C!RT@ side.

Next, one embodiment of the present invention will be described.

15th j! Example (See Figure 2) This example is an example in which the buffer memory has sufficient capacity so as not to be saturated at all times, and there is no need to wait for a timing for write access from the 3PU-BUS side.
As shown in the figure, in addition to the display part (2) of the main memory (1) of the CPU, the address
AM Q31 setting ff, V-RAM Buffer memory that temporarily stores write data and write address to Q3 (
9), and the buffer memory (9) is equipped with a first-in-first outdoor memory (FiFo) that reads the written contents in the order in which they were written.-1CPU-BU8 (3) data line (4) and address line (5) Buff Amezori (9)
Connect the write command line (6) in CPU-BU8 to A
At the same time, a part of the address line (5) is connected to the input end of the AND gate (7) via the decoder (8), and V - is connected to the input end of the AND gate (7) during the write command. R.A.
Connect the output terminal of M (+3 or the AND game that determines the write command to the display part (2) of the main memory) (7) to the buffer candy scale (9), and read the buffer memory +9) (
7) Write it ilQ*F V-RAM Q
3, connect the write address line Q'D of the buffer memory to the address changeover switch αO, and connect the readout address line αη of the control unit 01 connected to the CRT @ and the switch control line (to) to the address changeover switch ( Connect to address selector switch (g))) and connect to V-RAM Mo3 to read data from V-RAM! II (1→) is connected to the control unit (to), the write request signal line (2) of the buffer memory is connected to the control unit α→, and the write signal line (to) of the control unit is
6) is connected to the V-RAM (Ll), and the write end signal line of the control section is connected to the buffer memory (9).

When the CPU-BU8 cycle is started and there is a write command to the display part (2) of the main memory without V-RAM (to), the AND gate (7) outputs the data to the buffer memory (9). A write is commanded and the buffer memory (9) stores the data and addresses from the data line (4) and address line (5), while the display part (2) of the main memory
The same data is stored at the same address. CPU-BU
When there is a command to continue reading this data from the B side, the data stored in the display portion (2) of the main memory is read out.

The control unit 0Q time-divides write access to the V-RAM (to) and read access from the V-RAM (to), and during the write period, the address changeover switch (g) is set to the write address line αη. During the read period, connect the address selector switch (G) to the read atrea line αη.
-Pa”177fi<9 during the inclusive period.

When there is a write request from the write request signal line (2) to the control section (to), the V-RAMQ3
Writing is commanded to the V-RAM (11 transfers data from the write data line αQ of the pack memory to the write address line (b) of the buffer memory and the address changeover switch (g).
from the pack memory (9) to the address from V
- When writing to RAM (Ll) is completed, the write completion signal line of the control unit notifies the pack memory (9) of the completion of writing. The data in the V-RAM (to) stored in the address position from the address changeover switch (g) is
The signal is read out to the control section A (1) via the AM read data line 4, is converted into a signal for the CRT@ by the control section (to), and is displayed on the screen of the CRT@.

In the display memory control method of this example, (3PU-B
Write access from U8 @ does not wait for timing, so there is no decrease in CPU processing power due to timing wait, and ORT due to access contention.
Unlike the conventional method in which reading access from the CRT side is interrupted, there is no noise on the CRT @ side due to interruption of reading from the CRT side.Furthermore, the access cycle from the CRT9B1 is the same as the access time from the CPU-BU8 side. Unlike the conventional method, which is affected by , 01'U-BU8, it can be easily attached to the main body of the computer system by simply connecting it to the data line, address line, and write command line.

Second Embodiment (Refer to FIG. 3) This example is an example in which the buffer memory does not have sufficient capacity so as not to be constantly saturated, and write access from the CPU-BUS side is made to wait for timing. To explain the difference from the previous example, as shown in Figure 3, the buffer memory has a data register (9d
) with the same capacity as V diX p (9a) for atvy,
V -R during a write command from the CPU-BU8 (3) side
AM Q3 or the output terminal of the AND gate (7) that determines the write command to the display part (2) of the main memory is connected to the data register (9d) and the address register (9a).
and the input terminal of a D-type flip-flop (DFF) gate @.
The write request signal line (2) connected to the output terminal of 2) is connected to the control unit a, the write end signal line - of the control unit is connected to the reset terminal of the DFF gate (2), and Connect the output end of the gate wire to the input end of the AND gate (2), and connect the main memory request signal (MREQ) line (to) in BU8(a) of the zgo micro CPU to the input end of the AND gate (to). Connect to and the CPU is the main memo!
(1) Connect the output terminal of the AND gate (c) that outputs a timing wait signal only when accessing rt to 0PU-
It is connected to the wait signal (WAIT) line in BUB.

Other points are the same as those in the previous example, so the same reference numerals are given in FIG.

At the moment when the AND gate (7) for write command outputs and the output disappears, the data register (9d) and address register (9a) respectively store data and address, and the DFF generator (2) is set, D
A write request signal is output from the FF gate (a) to the control unit (g), and a buffer memory (9d) is sent from the DFF gate (to) to the AND gate (to) for timing.

A signal indicating the saturation state of (9a) is output, and the MRIQ
i! The AND gate (to) for the timing inputted from - outputs, and a wait signal is input to the W-MU T line),
Write access from the CPU-BU8 side is made to wait for a timing. Buff candy (9th.

When writing from (9a) to V-RAMQ3 is completed,
While the saturation state of t < yyimo9 (9d) and (9m) is released, a write end signal is output from the control unit α to the DFF gate, and the DFF gate (a) is reset.

The timing AND gate (2) no longer receives input from DFF gate 4 and no longer outputs, and the wait signal is no longer input to the WAIT line (c), so timing wait is canceled.

In the display memory control method of this example, since the capacity of the buffer memory is the minimum, write access from the CPU-BUS side requires a long timing wait time, but the timing wait time increases the capacity of the buffer memory. Therefore, it is possible to reduce the reduction in CPU processing capacity due to timing waiting. Moreover, waiting for that timing is delayed until the buffer memory is no longer saturated.
It does not require complicated timing control, and it also requires CPU-
It can be easily attached to the computer system body by simply connecting it to the data line, address line, write command line, request line, and standby signal line of BU8.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of the invention, FIG. 2 is a block diagram of a first embodiment of the invention, and FIG. 3 is a block diagram of a second embodiment of the invention. 1: Main memory 2: Display part 3: CPU
-BU8. Central processing unit path? Inn 9.9d, 9a:
Buffer memory 13: v-RAM, video signal generator 21: CRT, cathode ray tube Figure 1

Claims (1)

[Claims] A video signal generator is provided that overlaps with the display portion of the main memory of the central processing unit, and a buffer memory is provided to temporarily store the contents written to the video signal generator.
Writing from the /(S'9 input side of the central processing unit is performed to the display part of the main memory and buffer memory,
Reading from the central processing / A display memory control method characterized by writing from memory to a video signal generator.