CN117156176A

CN117156176A - Multi-protocol multi-resolution multi-source video signal real-time splicing method based on FPGA

Info

Publication number: CN117156176A
Application number: CN202311108338.4A
Authority: CN
Inventors: 郭伟杰; 林仁辉; 邹明杰; 谭兴柏; 吕毅军; 陈忠
Original assignee: Xiamen University
Current assignee: Xiamen University
Priority date: 2023-08-30
Filing date: 2023-08-30
Publication date: 2023-12-01

Abstract

The invention provides a multi-protocol multi-resolution multi-source video signal real-time splicing method and system based on an FPGA, wherein the method comprises the following steps: in response to reducing the plurality of different resolution images to the same size resolution; splicing the video signals after the images are reduced, wherein the splicing comprises two parts of writing storage and reading splicing; and the write-in storage stores multiple paths of videos with different resolutions into the DDR memory in a time-sharing way, and the read-in splicing performs the splicing operation of pictures during the readout. The splicing display of video images under different protocols is realized, the more complex application requirements are met, HDMI, optical fiber, ethernet and camera can be used as video input sources, and finally four paths of videos are displayed on the same picture; the DDR writing end performs multi-frame image caching, can input images with any resolution, and is not limited to video signal storage under the same protocol; the reading part realizes the image splicing of the DDR reading end, so that the splicing process is more flexible, and the code portability is good.

Description

Multi-protocol multi-resolution multi-source video signal real-time splicing method based on FPGA

Technical Field

The invention belongs to the technical field of image processing, and particularly relates to a multi-protocol multi-resolution multi-source video signal real-time splicing method and system based on an FPGA.

Background

An image is composed of pixel points, which are shown as small squares in fig. 1, and is composed of three colors of R (red), G (green) and B (blue). 1920×1080 means that the number of pixels of a frame of image is 1920×1080, that is, one column 1080 of pixels of the screen, and a total of 1920 columns, and the read-write sequence of each pixel is as indicated by a blue arrow from left to right and from top to bottom, as shown in fig. 1. Values 960 x 540, 1920 x 1080, 1280 x 720, etc. refer to image resolution.

Real-time monitoring of multiple pictures uses the same protocol (such as four-channel HDMI signals) as a spliced video source in most cases, and as the application environment becomes more complex, the real-time monitoring of multiple pictures needs to be compatible with more interface protocols to provide enough video signal sources. The video splicing of different protocols is realized, and besides the requirements of data encoding and decoding under different protocols are required to be met, more importantly, how to process the writing and reading of video source data of different protocols is also required.

In view of the above, it is very significant to provide a method and a system for splicing multi-protocol multi-resolution multi-source video signals in real time based on FPGA.

Disclosure of Invention

In order to solve the technical defect problems, the invention realizes the splicing display of video images under different protocols and meets more complex application requirements, and the invention provides a multi-source video signal real-time splicing method and system with multiple protocols and multiple resolutions based on an FPGA.

In a first aspect, the present invention provides a method for splicing multi-protocol multi-resolution multi-source video signals in real time based on FPGA, the method comprising the steps of:

in response to reducing the plurality of different resolution images to the same size resolution;

splicing the video signals after the images are reduced, wherein the splicing comprises two parts of writing storage and reading splicing;

and the write-in storage stores multiple paths of videos with different resolutions into the DDR memory in a time-sharing way, and the read-in splicing performs the splicing operation of pictures during the readout.

Preferably, the writing storage specifically includes:

judging the cache condition of an input video image as a gating condition for DDR memory writing, namely reading the data from a DRAM and storing the data into a page space of a designated DDR memory through a state machine after the data cached in a DRAM is close to the data quantity of one line;

storing images of different input sources into different page spaces, respectively distributing four page spaces for each video source for caching a plurality of frames of images, and performing page address self-increasing after one frame of image data is stored and a preset condition is met.

Further preferably, the multiple paths of different resolutions include four paths of input video sources, namely, videos input by a binocular camera, HDMI, ethernet and optical fiber, and when the multiple DRAMs simultaneously meet the readout condition, the priority order is as follows from large to small in sequence: binocular camera, optic fibre, ethernet, HDMI.

Preferably, the method further includes controlling the timing of reading and writing, i.e. when the writing operation has not yet entered a complete frame of image into the DDR memory, the reading operation reads the cached page space, but not the page space being written.

Preferably, the reading splice includes:

selecting the read page space as the cached page space corresponding to each input source, and ensuring the stability of the read image;

and performing two times of address reading operation on each data, and performing a second time of address reading operation after the first time of data reading operation is finished according to the field synchronous signal and the rising edge of the data effective signal after the output image delay as marks of the first time of address reading operation of the output data.

Further preferably, the reading and splicing further includes page address switching of the writing port, that is, when one frame of image is written and the page address is added by one and does not collide with the page address, the method specifically includes:

assuming that a read page address of 1 indicates that pixel values at each point of the image are being read from page 1 of the DDR, a write page address of 3 indicates that data is being written to the corresponding address in the DDR;

if the writing of one frame of image is completed on the page 3, and the read operation is performed on the page 1 at the moment, the space page 0 for performing the next writing operation is not the same page as the page 1 being read, and the address of the written page is added by one at the moment, namely, the data is written into the page 0 to cover one frame of the original buffer memory;

conversely, if page 0 is also written, while page 1 is still being read, this indicates that the write clock is much faster than the read clock, and the page address written at this time is not incremented, but rather the data continues to be written into page 1, covering a frame of the written image.

Further preferably, the reading splicing further includes page address switching of a reading port, specifically including:

if one frame of image is read and the added page address is not the page address being written, adding one to the page address;

if the address of the current page is in conflict with the address of the write page after adding one, the current page is repeatedly read.

In a second aspect, an embodiment of the present invention further provides a multi-protocol multi-resolution multi-source video signal real-time splicing system based on FPGA, where the system includes:

an image reduction module configured to reduce a plurality of paths of images of different resolutions to resolutions of the same size;

the writing storage module is configured to store multiple paths of videos with different resolutions into the DDR memory in a time-sharing manner;

and the reading splicing module is configured to carry out splicing operation of the pictures during reading.

In a third aspect, an embodiment of the present invention provides an electronic device, including: one or more processors; and storage means for storing one or more programs which, when executed by the one or more processors, cause the one or more processors to implement the method as described in any of the implementations of the first aspect.

In a fourth aspect, embodiments of the present invention provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method as described in any of the implementations of the first aspect.

Compared with the prior art, the invention has the beneficial effects that:

(1) The invention provides a multi-protocol multi-resolution multi-source video signal real-time splicing method based on an FPGA, which realizes the splicing display of video images under different protocols, meets more complex application requirements, can realize that HDMI, optical fiber, ethernet and a camera are taken as video input sources, and finally presents four paths of videos on the same picture.

(2) The DDR writing end performs multi-frame image caching, can input images with any resolution, and is not limited to video signal storage under the same protocol; the reading part realizes the image splicing of the DDR reading end, so that the splicing process is more flexible, and the code portability is good.

Drawings

The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain the principles of the invention. Many of the intended advantages of other embodiments and embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

FIG. 1 is a schematic diagram of pixel arrangement and read/write sequence in an embodiment of the present invention;

FIG. 2 is a schematic general flow diagram of a multi-protocol multi-resolution multi-source video signal real-time splicing system based on FPGA according to an embodiment of the present invention;

FIG. 3 is a flow chart of a multi-protocol multi-resolution multi-source video signal real-time splicing system based on FPGA according to an embodiment of the present invention;

fig. 4 is a flow chart of a method for splicing multi-protocol multi-resolution multi-source video signals in real time based on FPGA according to an embodiment of the present invention;

FIG. 5 is a schematic block diagram of write storage in a multi-protocol multi-resolution multi-source video signal real-time splicing method based on FPGA according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of DRAM buffering in a multi-protocol multi-resolution multi-source video signal real-time splicing method based on FPGA according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a "page" space usage in a multi-protocol multi-resolution multi-source video signal real-time splicing method based on an FPGA according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of the "page" space splicing in the FPGA-based multi-protocol multi-resolution multi-source video signal real-time splicing method according to an embodiment of the present invention;

fig. 9 is a schematic diagram of HDMI frame display timing in the FPGA-based multi-protocol multi-resolution multi-source video signal real-time splicing method according to an embodiment of the present invention;

fig. 10 is a schematic diagram of a splicing result in a multi-protocol multi-resolution multi-source video signal real-time splicing method based on an FPGA according to an embodiment of the present invention;

fig. 11 is a schematic structural view of a computer device suitable for use in implementing an embodiment of the present invention.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. For this, directional terms, such as "top", "bottom", "left", "right", "upper", "lower", and the like, are used with reference to the orientation of the described figures. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized or logical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

Values of 960×540, 1920×1080, 1280×720, etc. mentioned in the embodiments of the present invention refer to image resolution. An image is composed of pixel points, which are shown as small squares in fig. 1, and is composed of three colors of R (red), G (green) and B (blue). 1920×1080 means that the number of pixels of a frame of image is 1920×1080, that is, one column 1080 of pixels of the screen, and a total of 1920 columns, and the read-write sequence of each pixel is as indicated by a blue arrow from left to right and from top to bottom, as shown in fig. 1.

In a first aspect, an embodiment of the present invention discloses a multi-protocol multi-resolution multi-source video signal real-time splicing system based on FPGA, and the overall flow of the system disclosed in the embodiment of the present invention is shown in fig. 2.

Specifically, as shown in fig. 3, the system specifically includes: an image reduction module 31, a write storage module 32 and a read stitching module 33.

In one embodiment, the image reduction module 31 is configured to reduce multiple paths of images with different resolutions to the same resolution; a write storage module 32 configured to time-share the multiple paths of video with different resolutions into the DDR memory; the read splicing module 33 is configured to perform a splicing operation of pictures at the time of reading.

In a second aspect, the embodiment of the invention also discloses a multi-protocol multi-resolution multi-source video signal real-time splicing method based on the FPGA, as shown in fig. 4, the method comprises the following steps:

s1, responding to reducing multiple paths of images with different resolutions to the resolution with the same size;

s2, splicing the video signals after the images are reduced, wherein the splicing comprises two parts of writing storage and reading splicing;

and S3, storing multiple paths of videos with different resolutions into the DDR memory in a time-sharing manner by the write-in storage, and performing picture splicing operation during reading and splicing.

Specifically, four paths of images with different resolutions are firstly reduced to the same size, in the embodiment of the invention, 960 x 540 is set, the reduction module is based on a common bilinear interpolation algorithm, the video sources of different protocols after scaling are different in video clocks, for example, the HDMI video image is reduced from original 1920 x 1080@60Hz to 960 x 540, but the clock frequency is still 148.5M, and for example, the video image collected by a camera is reduced from original 1280 x 720@30Hz to 960 x 540, but the clock frequency is still 37.125M.

The method includes the steps of writing, storing and reading video signals, storing four paths of video signals with different resolutions into DDR, and performing image splicing operation during reading.

Further, in the embodiment of the present invention, as shown in fig. 5, four distributed RAMs are used to buffer a line of data of four input sources, where sources 1 to 4 represent input signal sources, respectively corresponding to videos input by a binocular camera, HDMI, ethernet and optical fiber, and in other embodiments, the input signal sources may be selected according to actual requirements.

Because video clocks of different input sources are different, if four video sources are adopted to write DDR sequentially, the efficiency of writing operation is reduced, the embodiment of the invention uses the situation of video image buffer memory input as DDR writing strobe condition, after data buffered in a certain DRAM approaches one line of data amount, as shown in FIG. 6, for 960 x 540 resolution images after HDMI shrinkage, the total number of pixels in one line is 960, when the number of corresponding DRAM buffer pixel points reaches 940, the line data is read out from the DRAM through a state machine and stored in a designated DDR "page" space, and the selection of the "page" space is determined by the upper few bits of DDR writing address, for example, 16 "page" spaces are used in the embodiment of the invention, and therefore, the upper 4 bits of a storage address are used for distinguishing the "page" space.

Specifically, when a plurality of DRAMs satisfy the readout condition at the same time, the priority order in the embodiment of the present invention is as follows: binocular camera > optical fiber > ethernet > HDMI.

The option of starting the read-out when the cache is approaching a line, i.e. starting the read-out from 940 data stored instead of 960, is to reduce the delay as much as possible, ensuring real-time. "read address self-increment" refers to reading data from the beginning of a row until the last in a row, and "waiting" refers to waiting for the number of caches in the DRAM to reach 940. When writing data, the images of different input sources are stored in different 'pages', in this embodiment, 4 'page' spaces are allocated for each video source for buffering several frames of images respectively, and when one frame of image data is stored, the page address is self-increased after meeting the condition (the condition needs to be combined with a readout splicing part described later), so that 16 'page' spaces are prepared for four paths of images. The stitching part is responsible for stitching four paths of 960 x 540 images into 1080P60Hz image output.

Further, the readout splice is specifically described as follows:

after the writing of different input sources is controlled by a state machine of a writing end, 4 storage spaces of a page are prepared for each input source, as shown in fig. 7, the full-shading part indicates that a frame of image is cached in the page, the half-shading part performs writing operation on the page, the shaded area with oblique lines indicates that a frame of image which is cached is actually read out, splicing operation is performed, and the blank part indicates that the page is in a blank state and is not written in. The frame images are cached, so that the picture taken out during the reading operation is a certain frame of cached image, and the integrity and stability of the image are ensured.

Further, as shown in fig. 1, the image read-write sequence is shown in fig. 1, since the frame needs to be divided into four equal parts, each line of the output image has 1920 pixel data, and each line of data stored in each page space is 960, each line of data of the output image needs to be spliced by each line of data of two frames of images in two page spaces, and as shown in fig. 8, the read-out page space is selected as the cached page space corresponding to each input source, so that the stability of the read-out image can be ensured, and the empty data cannot be read. When 1920×1080@60hz images are output, the first line data are formed by splicing the first line data in the storage spaces of the DDR 'page 1' and the 'page 4', and the same applies. It should be noted that the rising edge of the data valid signal is used as a flag for the first read address operation of the output data according to the field sync signal after the output image is delayed, and the second read address operation is after the end of the first read data operation. Because each "page" space stores an image with a resolution of 960 x 540, that is, only 540 lines of data, when the line counter counts to line 541, it is necessary to switch to the other two input source stored "page" spaces for reading.

Further, the writing and reading page address includes: the use condition of the page space allocated to the camera is shown in fig. 6, the data clock acquired by the camera is 37.125M, the data clock output after the splicing is 148.5M, the read clock is faster than the write clock, the read operation is faster than the write operation, several frames of images need to be cached, when the write operation does not yet input a complete frame of images into the DDR memory, the read operation can read the cached page space instead of the page space which is being written, and the read and write time sequence needs to be controlled to prevent the picture from tearing when the function is realized.

The determination of whether a frame of image has been written is based on the field sync signal, i.e., the VSYNC signal in fig. 9, which indicates that a new frame of image starts when the rising edge of the signal arrives, and the falling edge indicates that a frame of image ends, with a duration of high level.

When the address of the page of the writing port is switched, one frame of image is written, and when the address of the page is added by one and does not conflict with the address of the page, the address of the page is added by one. Taking the example of the "page" space usage of HDMI in fig. 7, when the read "page" address is 1, which indicates that the pixel value of each point of the image is being read from "page 1" of DDR, the write "page" address is 3, which indicates that the data is being written to the corresponding address in DDR, assuming that "page 3" has completed writing of one frame of image, and that "page 1" is still performing the read operation at this moment, then the space "page 0" for the next write operation is not on the same page as "page 1" being read, then the "page" address is added by one, that is, then the data is written into "page 0" (covering one frame originally buffered); conversely, if "page 0" is also written, while "page 1" is still being read (indicating that the write clock is much faster than the read clock), the written "page" address is not incremented by one, but the writing of data (one frame of image is overwritten) into "page 1" is continued.

Similarly, when the page address of the read port is switched, if one frame of image is read, and the added page address is not the page address which is being written, the page address is written and added by one; if the address of the page is collided with the address of the written page after adding one, the current page is repeatedly read.

Specifically, the splicing result of the embodiment of the invention is shown in fig. 10, wherein the upper left corner is an HDMI image, the upper right corner is an image acquired by a camera, the lower left corner is an image transmitted by an optical fiber interface, and the lower right corner is an image received by an ethernet interface.

The embodiment of the invention provides a multi-protocol multi-resolution multi-source video signal real-time splicing method based on an FPGA, realizes the splicing display of video images under different protocols, meets more complex application requirements, can realize that HDMI, optical fiber, ethernet and a camera are taken as video input sources, and finally presents four paths of videos on the same picture.

The DDR writing end performs multi-frame image caching, can input images with any resolution, and is not limited to video signal storage under the same protocol; the reading part realizes the image splicing of the DDR reading end, so that the splicing process is more flexible, and the code portability is good.

Referring now to FIG. 11, there is illustrated a schematic diagram of a computer apparatus 600 suitable for use in an electronic device (e.g., the server or terminal device illustrated in FIG. 1) for implementing an embodiment of the present invention. The electronic device shown in fig. 11 is only an example, and should not impose any limitation on the functions and scope of use of the embodiments of the present invention.

As shown in fig. 11, the computer apparatus 600 includes a Central Processing Unit (CPU) 601 and a Graphics Processor (GPU) 602, which can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 603 or a program loaded from a storage section 609 into a Random Access Memory (RAM) 604. In the RAM 604, various programs and data required for the operation of the apparatus 600 are also stored. The CPU 601, GPU602, ROM 603, and RAM 604 are connected to each other through a bus 605. An input/output (I/O) interface 606 is also connected to the bus 605.

The following components are connected to the I/O interface 606: an input portion 607 including a keyboard, a mouse, and the like; an output portion 608 including a speaker, such as a Liquid Crystal Display (LCD), etc.; a storage portion 609 including a hard disk and the like; and a communication section 610 including a network interface card such as a LAN card, a modem, or the like. The communication section 610 performs communication processing via a network such as the internet. The drive 611 may also be connected to the I/O interface 606 as needed. A removable medium 612 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 611 as necessary, so that a computer program read out therefrom is mounted into the storage section 609 as necessary.

In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flow chart. In such embodiments, the computer program may be downloaded and installed from a network via the communication portion 610, and/or installed from the removable medium 612. The above-described functions defined in the method of the present invention are performed when the computer program is executed by a Central Processing Unit (CPU) 601 and a Graphics Processor (GPU) 602.

It should be noted that the computer readable medium according to the present invention may be a computer readable signal medium or a computer readable medium, or any combination of the two. The computer readable medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor apparatus, device, or means, or a combination of any of the foregoing. More specific examples of the computer-readable medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution apparatus, device, or apparatus. In the present invention, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may be any computer readable medium that is not a computer readable medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution apparatus, device, or apparatus. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based devices which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The modules involved in the embodiments of the present invention may be implemented in software or in hardware. The described modules may also be provided in a processor.

As another aspect, the present invention also provides a computer-readable medium that may be contained in the electronic device described in the above embodiment; or may exist alone without being incorporated into the electronic device. The computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to: in response to reducing the plurality of different resolution images to the same size resolution; splicing the video signals after the images are reduced, wherein the splicing comprises two parts of writing storage and reading splicing; and the write-in storage stores multiple paths of videos with different resolutions into the DDR memory in a time-sharing way, and the read-in splicing performs the splicing operation of pictures during the readout.

The above description is only illustrative of the preferred embodiments of the present invention and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the invention referred to in the present invention is not limited to the specific combinations of the technical features described above, but also covers other technical features formed by any combination of the technical features described above or their equivalents without departing from the inventive concept described above. Such as the above-mentioned features and the technical features disclosed in the present invention (but not limited to) having similar functions are replaced with each other.

Claims

1. A multi-protocol multi-resolution multi-source video signal real-time splicing method based on FPGA is characterized by comprising the following steps:

2. The method for splicing multi-source video signals with multiple protocols and multiple resolutions based on the FPGA according to claim 1, wherein the writing storage specifically comprises:

3. The method for splicing multi-source video signals with multiple protocols and multiple resolutions based on FPGA according to claim 2, wherein the multiple paths of different resolutions comprise four paths of input video sources, namely, videos input by a binocular camera, HDMI, ethernet and optical fiber, and when the multiple DRAMs simultaneously meet the reading condition, the priority order is sequentially from large to small: binocular camera, optic fibre, ethernet, HDMI.

4. The FPGA-based multi-protocol multi-resolution multi-source video signal real-time splicing method of claim 1, further comprising controlling read and write timing such that when a write operation has not yet entered a complete frame of image into the DDR memory, the read operation reads the cached page space but does not read the page space being written.

5. The FPGA-based multi-protocol multi-resolution multi-source video signal real-time stitching method of claim 1, wherein the reading stitching comprises:

6. The method for splicing multi-source video signals with multiple protocols and multiple resolutions based on FPGA according to claim 5, wherein the read-splice further includes switching page addresses of a write port, that is, when one frame of image is written and one page address is added to one page address, which does not collide with the read page address, specifically including:

when the read page address is 1, the pixel values of each point of the image are being read from the page 1 of the DDR, and the write page address is 3, the data are being written to the corresponding address in the DDR;

7. The method for splicing multi-source video signals with multiple protocols and multiple resolutions based on the FPGA according to claim 6, wherein the reading and splicing further comprises page address switching of a reading port, and specifically comprises the following steps:

8. A multi-protocol multi-resolution multi-source video signal real-time splicing system based on an FPGA, the system comprising:

9. An electronic device, comprising:

one or more processors;

a storage system for storing one or more programs;

when executed by the one or more processors, causes the one or more processors to implement the method of any of claims 1 to 7.

10. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the method according to any one of claims 1 to 7.