JPS63283137A - Method for assembling semiconductor device - Google Patents

Method for assembling semiconductor device

Info

Publication number
JPS63283137A
JPS63283137A JP62119217A JP11921787A JPS63283137A JP S63283137 A JPS63283137 A JP S63283137A JP 62119217 A JP62119217 A JP 62119217A JP 11921787 A JP11921787 A JP 11921787A JP S63283137 A JPS63283137 A JP S63283137A
Authority
JP
Japan
Prior art keywords
wire
semiconductor element
semiconductor device
oxidation
inner lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62119217A
Other languages
Japanese (ja)
Inventor
Hitoshi Fujimoto
藤本　仁士
Kiyoaki Tsumura
清昭 津村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62119217A priority Critical patent/JPS63283137A/en
Publication of JPS63283137A publication Critical patent/JPS63283137A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To protect wires from peel-off by a method wherein the entire wirings and connections involving wires are covered by an oxidation-corrosion preventing agent after the accomplishment of connection between a semiconductor element and inner leads. CONSTITUTION:A semiconductor element 1 is bonded to an island 2 on a lead frame. Next, connection is established by a wire 3 between an electrode 1a of the semiconductor element 1 and a connecting portion 4a of an inner lead 4, and the wire 3, electrode 1a, and connecting portion 4a are coated by a thin film 11. For the provision of the coating, the potting method, wherein an oxidation-corrosion preventing agent in gel is caused to drip, or the spaying method, wherein the same is converted into spray before application, is used. A packaging process follows wherein resin is used for sealing the wire 3, inner lead 4, and element 1 in a package 12. This method suppresses the degrading of a wire as a whole or of its bonded portions, preventing the wire from peel- off.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路用のワイヤとして例えば銅製
の金属細線を使用する半導体装置の組立方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for assembling a semiconductor device using a thin metal wire made of copper, for example, as a wire for a semiconductor integrated circuit.

〔従来の技術〕[Conventional technology]

従来、この種の方法を用いて組み立てる半導体装置は第
３図に示すように構成されている。これを同図に基づい
て説明すると、同図において、符−号１で示すものはパ
ッケージ（図示せず）によって樹脂封止されたアイラン
ド２上の半導体素子、３はこの半導体素子１とインナー
リード４とを接続する銅製のワイヤである。Conventionally, a semiconductor device assembled using this type of method has a structure as shown in FIG. To explain this based on the same figure, in the same figure, what is indicated by the reference numeral 1 is the semiconductor element on the island 2 sealed with resin by a package (not shown), and 3 is the semiconductor element 1 and the inner lead. This is a copper wire that connects 4.

次に、このように構成された半導体装置の組立方法につ
いて説明する。Next, a method for assembling the semiconductor device configured as described above will be explained.

先ず、リードフレーム（図示せず）のアイランド２上に
半導体素子１を接合する。次いで、この半導体素子１の
電極（図示せず）とインナーリード４とを先端部が予め
球状に形成されたワイヤ３によって接続する。このワイ
ヤボンディングは熱圧着法あるいは超音波熱圧着法が採
用される。しかる後、このワイヤ３．インナーリード４
および半導体素子１をパッケージ（図示せず）によって
樹脂封止する。First, the semiconductor element 1 is bonded onto the island 2 of a lead frame (not shown). Next, an electrode (not shown) of this semiconductor element 1 and an inner lead 4 are connected by a wire 3 whose tip portion is previously formed into a spherical shape. For this wire bonding, a thermocompression bonding method or an ultrasonic thermocompression bonding method is adopted. After that, this wire 3. inner lead 4
Then, the semiconductor element 1 is sealed with a resin using a package (not shown).

このようにして、半導体装置を組み立てることができる
。In this way, a semiconductor device can be assembled.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、この種の半導体装置の組立方法においては、
ワイヤ３が酸化および腐食に対し耐久性を有する金線を
使用する場合は問題がないのであるが、ワイヤ３として
銅線を使用する場合には、パッケージ（図示せず）の内
部に浸入する空気。By the way, in this type of semiconductor device assembly method,
There is no problem if the wire 3 is made of gold wire, which is resistant to oxidation and corrosion, but if a copper wire is used as the wire 3, air may enter the inside of the package (not shown). .

湿気あるいは不純物等によってワイヤ３が酸化したり腐
食したりすることがあった。この結果、ワイヤ３および
ワイヤボンディング部が劣化して剥離が発生し、半導体
装置動作上の信顛性が低下するという問題があった。The wire 3 may be oxidized or corroded due to moisture or impurities. As a result, the wire 3 and the wire bonding portion deteriorate and peel off, resulting in a problem that reliability in the operation of the semiconductor device is reduced.

本発明はこのような事情に鑑みなされたもので、ワイヤ
の剥離発生を防止することができ、もって半導体装置動
作上の信頬性を向上させることができる半導体装置の組
立方法を提供するものである。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for assembling a semiconductor device that can prevent the occurrence of wire peeling and thereby improve reliability in the operation of the semiconductor device. be.

〔問題点を解決するための手段〕[Means for solving problems]

本発明に係る半導体装置の組立方法は、半導体素子とイ
ンナーリードとを接続した後にワイヤの全体およびワイ
ヤの接合部分を酸化・腐食防止剤で被覆するものである
。In the method for assembling a semiconductor device according to the present invention, after connecting a semiconductor element and an inner lead, the entire wire and the joint portion of the wire are coated with an oxidation/corrosion inhibitor.

〔作　用〕[For production]

本発明においては、パッケージ内に浸入する空気、湿気
あるいは不純物等からワイヤの全体およびワイヤの接合
部分を保護することができる。In the present invention, the entire wire and the bonded portion of the wire can be protected from air, moisture, impurities, etc. that enter the package.

〔実施例〕〔Example〕

第１図は本発明に係る方法によって組み立てられた半導
体装置の要部を示す断面図、第２図は同じく半導体装置
の全体を示す断面図で、同図において第３図と同一の部
材については同一の符号を付し、詳細な説明は省略する
。同図において、符号１１で示すものは酸化・腐食防止
剤からｄる薄膜であり、これによって前記ワイヤ３の全
体およびその接合部分（ワイヤボンディング部）が被覆
されている。すなわち、前記ワイヤ３．前記半導体素子
１の電極１ａおよび前記インナーリード４のワイヤ接続
部４ａが薄膜１１で囲繞されているのである。なお、１
２は前記半導体素子１．前記ワイヤ３および前記インナ
ーリード４を封止するエポキシ樹脂系のパンケージ、１
３は前記インナーリード４に接続するアウターリードで
ある。FIG. 1 is a sectional view showing the main parts of a semiconductor device assembled by the method according to the present invention, and FIG. 2 is a sectional view showing the entire semiconductor device. The same reference numerals will be given, and detailed explanation will be omitted. In the figure, the reference numeral 11 indicates a thin film made of an oxidation/corrosion inhibitor, which covers the entire wire 3 and its bonding portion (wire bonding portion). That is, the wire 3. The electrode 1a of the semiconductor element 1 and the wire connection portion 4a of the inner lead 4 are surrounded by the thin film 11. In addition, 1
2 is the semiconductor element 1. an epoxy resin pancage for sealing the wire 3 and the inner lead 4;
3 is an outer lead connected to the inner lead 4.

次に、本発明における半導体装置の組立方法について説
明する。Next, a method for assembling a semiconductor device according to the present invention will be explained.

先ず、リードフレーム（図示せず）のアイランド２上に
半導体素子１を接合する０次いで、この半導体素子１の
電極１ａとインナーリード４のワイヤ接続部４ａとを先
端部が予め球状に形成されたワイヤ３によって接続し、
このワイヤ３．半導体素子１の電極１ａおよびインナー
リード４のワイヤ接続部４ａを薄膜１１で被覆する。こ
の場合の被覆方法については、ゲル状の酸化・腐食防止
剤を滴下するボッティング方式あるいは霧状の酸化・腐
食防止剤を塗布するスプレ一方式を使用する。しかる後
、このワイヤ３．インナーリード４および半導体素子１
をパッケージ１２によって樹脂封止する。First, the semiconductor element 1 is bonded onto the island 2 of a lead frame (not shown).Next, the electrode 1a of the semiconductor element 1 and the wire connection part 4a of the inner lead 4 are connected to each other, the tip of which has been previously formed into a spherical shape. connected by wire 3;
This wire 3. The electrode 1a of the semiconductor element 1 and the wire connection portion 4a of the inner lead 4 are covered with a thin film 11. In this case, the coating method is a botting method in which a gel-like oxidation/corrosion inhibitor is dropped, or a spraying method in which a mist-like oxidation/corrosion inhibitor is applied. After that, this wire 3. Inner lead 4 and semiconductor element 1
is sealed with a resin using a package 12.

このようにして、半導体装置を組み立てることができる
。In this way, a semiconductor device can be assembled.

このような半導体装置の組立方法においては、ワイヤ３
およびワイヤボンディング部を薄膜１１で被覆するから
、パッケージ１２内に浸入する空気、湿気あるいは不純
物（有機酸）等からワイヤ３の全体およびその接合部分
を保護することができる。In such a semiconductor device assembly method, the wire 3
Since the wire bonding portion is covered with the thin film 11, the entire wire 3 and its bonding portion can be protected from air, moisture, impurities (organic acid), etc. that enter the package 12.

したがって、本発明においては、経年変化によるワイヤ
３およびワイヤボンディング部の劣化を確実に抑制する
ことができる。この場合、ワイヤ３として銅線を使用す
るため、金線を使用した場合と比較してワイヤ接合部の
金属間化合物の成長スピードが１／１００となる。Therefore, in the present invention, deterioration of the wire 3 and the wire bonding portion due to aging can be reliably suppressed. In this case, since a copper wire is used as the wire 3, the growth speed of the intermetallic compound at the wire joint is 1/100 compared to the case where a gold wire is used.

なお、本実施例においては、樹脂封止する以前にワイヤ
３およびその接合部分を薄膜１１で被覆する場合を示し
たが、本発明はこれに限定されるものではなく、樹脂封
止時にパッケージ１２内に酸化・腐食防止剤を混入する
ことにより被覆しても実施例と同様の効果を奏する。Although this embodiment shows a case where the wire 3 and its joint portion are covered with the thin film 11 before resin sealing, the present invention is not limited to this, and the package 12 is coated with the thin film 11 during resin sealing. Even if the coating is done by mixing an oxidation/corrosion inhibitor therein, the same effect as in the embodiment can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、半導体素子とイン
ナーリードとを接続した後にワイヤの全体およびワイヤ
の接合部分を酸化・腐食防止剤で被覆するので、パッケ
ージ内に浸入する空気、湿気あるいは不純物等からワイ
ヤの全体およびその接合部分を保護することができる。As explained above, according to the present invention, after the semiconductor element and the inner lead are connected, the entire wire and the joint part of the wire are coated with an oxidation/corrosion inhibitor, so that air, moisture, or impurities that enter the package can be prevented. It is possible to protect the entire wire and its joints from

したがって、ワイヤとして銅線を使用する場合にも経年
変化によるワイヤ全体およびワイヤ接合部分の劣化を抑
制することができるから、ワイヤの剥離発生を防止する
ことができ、半導体装置動作上の信軌性を向上させるこ
とができる。Therefore, even when copper wire is used as the wire, it is possible to suppress the deterioration of the entire wire and the wire bonding part due to aging, so it is possible to prevent the occurrence of wire peeling, and to improve the reliability of semiconductor device operation. can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明に係る方法によって組み立てられた半導
体装置の要部を示す断面図、第２図は同じく半導体装置
の全体を示す断面図、第３図は従来の方法によって組み
立てられた半導体装置の要部を示す断面図である。 １・・・・半導体素子、１ａ・・・・電極、２・・・・
アイランド、３・・・・ワイヤ、４・・・・インナーリ
ード、４ａ・・・・ワイヤ接続部、１１・・・・薄膜、
１２・・・・パッケージ。 代　理　人　大岩増雄 第１図 １　　：　４−４４案チ　　　　１／ｌシ方−ソート・
・３；Ａ欠　　　　　　　１２；ハリ１．ケージ゛手続
補正書（（，１間） □ ３、補正をする者 事件との関係　特許出願人 住　所　　　　東京都千代田区丸の内二丁目２番３号名
　称　　（６０１）三菱電機株式会社代表者志岐守哉 ４、代理人 住　所　　　　東京都千代田区丸の内二丁目２番３号）
、補正の対象 ＋１１　　明細書の発明の詳細な説明の欄（２）明細書
の図面の簡単な説明の欄 （３）図面 ５、補正の内容 ｔｉ）明細書６頁３行の「（有機酸）」を削除す５゜ （２）同書７頁１９行の「１２・・・・パッケージ」の
次に「、１３・・・・外部リード」を挿入する。 （３）第１図を添付図面の通り補正する。 以　　　上FIG. 1 is a cross-sectional view showing the main parts of a semiconductor device assembled by the method according to the present invention, FIG. 2 is a cross-sectional view showing the entire semiconductor device, and FIG. 3 is a semiconductor device assembled by the conventional method. FIG. 1... Semiconductor element, 1a... Electrode, 2...
Island, 3...Wire, 4...Inner lead, 4a...Wire connection part, 11...Thin film,
12...Package. Agent Masuo Oiwa Figure 1: 4-44 plan 1/l direction - sorting
・3; A missing 12; Hari 1. Cage procedural amendment ((, 1 space) □ 3. Relationship with the case of the person making the amendment Patent applicant Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Shiki, Representative of Mitsubishi Electric Corporation Moriya 4, agent address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo)
, Subject of amendment +11 Column for detailed explanation of the invention in the specification (2) Column for brief explanation of drawings in the specification (3) Drawing 5, content of amendment ti) "(Organic acid )" 5゜(2) In the same book, page 7, line 19, insert ", 13...external lead" next to "12...package". (3) Figure 1 is corrected as shown in the attached drawings. that's all

Claims (2)

【特許請求の範囲】[Claims] （１）リードフレームのアイランド上に半導体素子を接
合し、次いでワイヤによってこの半導体素子の電極と前
記リードフレームのインナーリードとを接続し、しかる
後パッケージによって前記半導体素子およびワイヤを樹
脂封止する半導体装置の組立方法において、前記半導体
素子と前記インナーリードとを接続した後にワイヤの全
体およびワイヤの接合部分を酸化・腐食防止剤で被覆す
ることを特徴とする半導体装置の組立方法。(1) A semiconductor device in which a semiconductor element is bonded onto an island of a lead frame, then the electrodes of this semiconductor element and the inner leads of the lead frame are connected by wires, and then the semiconductor element and wires are sealed with resin using a package. A method for assembling a semiconductor device, characterized in that after the semiconductor element and the inner lead are connected, the entire wire and the joint portion of the wire are coated with an oxidation/corrosion inhibitor. （２）パッケージ内に酸化・腐食防止剤を混入する特許
請求の範囲第１項記載の半導体装置の組立方法。(2) The method for assembling a semiconductor device according to claim 1, wherein an oxidation/corrosion inhibitor is mixed into the package.
JP62119217A 1987-05-15 1987-05-15 Method for assembling semiconductor device Pending JPS63283137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62119217A JPS63283137A (en) 1987-05-15 1987-05-15 Method for assembling semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62119217A JPS63283137A (en) 1987-05-15 1987-05-15 Method for assembling semiconductor device

Publications (1)

Publication Number Publication Date
JPS63283137A true JPS63283137A (en) 1988-11-21

Family

ID=14755852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62119217A Pending JPS63283137A (en) 1987-05-15 1987-05-15 Method for assembling semiconductor device

Country Status (1)

Country Link
JP (1) JPS63283137A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5950100A (en) * 1995-05-31 1999-09-07 Nec Corporation Method of manufacturing semiconductor device and apparatus for the same
WO2010147187A1 (en) * 2009-06-18 2010-12-23 ローム株式会社 Semiconductor device
JP2012231034A (en) * 2011-04-26 2012-11-22 Fujifilm Corp Bonding wire and printed circuit board and method of manufacturing the same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5950100A (en) * 1995-05-31 1999-09-07 Nec Corporation Method of manufacturing semiconductor device and apparatus for the same
KR100237511B1 (en) * 1995-05-31 2000-01-15 가네꼬 히사시 Method of manufacturing semiconductor device and apparatus for the same
WO2010147187A1 (en) * 2009-06-18 2010-12-23 ローム株式会社 Semiconductor device
CN102484080A (en) * 2009-06-18 2012-05-30 罗姆股份有限公司 Semiconductor device
JPWO2010147187A1 (en) * 2009-06-18 2012-12-06 ローム株式会社 Semiconductor device
TWI556392B (en) * 2009-06-18 2016-11-01 羅姆股份有限公司 Semiconductor device
US9780069B2 (en) 2009-06-18 2017-10-03 Rohm Co., Ltd. Semiconductor device
US10163850B2 (en) 2009-06-18 2018-12-25 Rohm Co., Ltd. Semiconductor device
JP2012231034A (en) * 2011-04-26 2012-11-22 Fujifilm Corp Bonding wire and printed circuit board and method of manufacturing the same

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