JPS60223147A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS60223147A JPS60223147A JP59078452A JP7845284A JPS60223147A JP S60223147 A JPS60223147 A JP S60223147A JP 59078452 A JP59078452 A JP 59078452A JP 7845284 A JP7845284 A JP 7845284A JP S60223147 A JPS60223147 A JP S60223147A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- lead
- semiconductor device
- leads
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置、特に樹脂封止半導体装置における
配線不良防止技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique for preventing wiring defects in semiconductor devices, particularly resin-sealed semiconductor devices.
樹脂封止形の半導体集積回路装置（ＩＣ，Ｌ８工）の一
般的構造は第１図、第２図に示すように半導体チップ１
（又はベレット）と、この半導体チップ１を固定するた
めの金属タブ２とタブ２を支持するタブリード（タブつ
りリード）３と、タブ２周辺に配設された複数のり−ド
４及びこれらを包囲封止する樹脂成形体５とから成るも
のである。樹脂成形後に半導体チップ１表面に形成され
たアルミニウム配線の断線不良が問題となりていること
がわかった。The general structure of a resin-sealed semiconductor integrated circuit device (IC, L8 type) is as shown in Figures 1 and 2.
(or a bellet), a metal tab 2 for fixing the semiconductor chip 1, a tab lead (tab suspension lead) 3 for supporting the tab 2, a plurality of glues 4 arranged around the tab 2, and surrounding these. It consists of a resin molded body 5 to be sealed. It has been found that disconnection of the aluminum wiring formed on the surface of the semiconductor chip 1 after resin molding is a problem.
このようなアルミニウム配線の初期の不良の原因として
タブリード３と樹脂成形体５との密着性が悪く、そのた
め！２図に示すようにタブリード３下に隙き間６ができ
、この隙き間６Ｖｃ水分がたまったり、あるいは隙き間
６を伝って外部の水分カタフ上のペレット１０載置位置
まで侵入し、アルミニウム配線腐食等を引き起すという
ことがわかった。The reason for the initial failure of such aluminum wiring is the poor adhesion between the tab lead 3 and the resin molded body 5! As shown in Fig. 2, a gap 6 is created under the tab lead 3, and moisture accumulates in this gap 6Vc, or enters through the gap 6 to the position where the pellet 10 is placed on the external moisture cathode. It was found that this caused corrosion of aluminum wiring.
ところで従来よりリード抜けを防止するため樹脂体との
間の接着性を向上する一つの対策として、たとえば特開
昭５８−９５８５２号公報に記載されているように、イ
ンナーリードの表面にプレス等の手段で凹凸のくぼみや
突起を設けることが提案されている。By the way, as one measure to improve the adhesion between the inner lead and the resin body in order to prevent the lead from coming off, as described in Japanese Patent Application Laid-Open No. 58-95852, for example, a press or the like is applied to the surface of the inner lead. It has been proposed to provide uneven depressions or protrusions by means of other means.
また、本出願にかかる発明者によって、たとえば第３図
に示すようにタブリード３の付は根部分に折り曲げ部７
を設けたり、あるいは孔あけしたりすることによりタブ
リード３と樹脂形成体５との密着性を良好なものとし、
水分の侵入を防止する方法が提案されている。Further, the inventor of the present application has proposed that the tab lead 3 is attached with a bent portion 7 at the root portion, as shown in FIG. 3, for example.
By providing or drilling holes, the adhesion between the tab lead 3 and the resin molded body 5 is made good,
Methods for preventing moisture intrusion have been proposed.
しかし、これらの対策はタブリード自体を加工するもの
でなく、ただ単にタブリードを変形させたものであるた
め、タブリード近傍での隙き間の発生を完全になくす充
分な手段とはならないことがわかった。However, these measures do not involve processing the tab lead itself, but simply deforming the tab lead, so it was found that they were not a sufficient means to completely eliminate the occurrence of gaps near the tab lead. .
本発明は上記の問題を解決するためになされたものであ
り、その目的はタブリード近傍での隙き間発生をなくし
、配線不良をなくした耐湿性の高い樹脂封止形半導体装
置の提供にある。The present invention has been made to solve the above problems, and its purpose is to provide a highly moisture-resistant resin-sealed semiconductor device that eliminates the occurrence of gaps near tab leads and eliminates wiring defects. .
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体チップと、半導体チップを固定するた
めの金属からなるタブと、タブを支持するタブリードと
、タブ周辺に配設された複数のリード及び半導体チップ
、タブ、リードの一部を包囲し封止する樹脂成形体から
なる半導体装置において、上記タブリードの表面に二酸
化チタンのごとき樹脂成形体との接着性の良好な金属酸
化物膜を施し、であることによりタブリードと樹脂成形
体との間に隙き間が発生することを防止し、前記目的を
達成するものである。That is, a semiconductor chip, a tab made of metal for fixing the semiconductor chip, a tab lead that supports the tab, a plurality of leads arranged around the tab, and a part of the semiconductor chip, tab, and leads that surrounds and seals. In a semiconductor device made of a resin molded body, the surface of the tab lead is coated with a metal oxide film such as titanium dioxide, which has good adhesion to the resin molded body, so that there is no space between the tab lead and the resin molded body. This is to prevent the generation of gaps and achieve the above objective.
第４図は本発明の一実施例を示すものであって、樹脂封
止形半導体装置の内部構造の平面図、第５図は第４図に
おけるＡ−に切断断面図である。FIG. 4 shows an embodiment of the present invention, and is a plan view of the internal structure of a resin-sealed semiconductor device, and FIG. 5 is a cross-sectional view cut along line A- in FIG. 4.
１は半導体素子、たとえばＩｃの形成された半 ゛導体
チップ１でその表面周辺にはアルミニウム配線の外部接
続端子であるポンディングパッド１７が形成されている
。２は半導体′チップ１が接続された金属タブ、３はタ
ブリードである。４はリードである。このリード４とチ
ップ１上のポンディングパッド１７との間は金属ワイヤ
８を介して接続されている。５はエポキシ樹脂等からな
る成形体である。Reference numeral 1 denotes a semiconductor chip 1 on which a semiconductor element, for example, Ic, is formed, and bonding pads 17, which are external connection terminals of aluminum wiring, are formed around the surface of the semiconductor chip 1. 2 is a metal tab to which the semiconductor chip 1 is connected, and 3 is a tab lead. 4 is the lead. The leads 4 and the bonding pads 17 on the chip 1 are connected via metal wires 8. 5 is a molded body made of epoxy resin or the like.
上記タブリード３の上面及び下面にチタン酸化物（Ｔｉ
Ｏｘ ）膜９が設けられている。Titanium oxide (Ti) is applied to the upper and lower surfaces of the tab lead 3.
An Ox ) film 9 is provided.
第６図は本発明の他の実施例を示すものであって、半導
体チップ１縁部へのワイヤ８の接触をさけるためリード
上面４ａを半導体チップ１上面の高さと一致させるよう
にタブリード３を折り曲げ、そのタブリード３の側面及
び上面及び下面部分にチタン酸化物膜９を施した場合の
正面断面図である。ここで注目すべきは、チタン酸化物
膜９がタブリード３の側面、上面、下面に設けられてい
るため、水の侵入経路は完全に断たれているということ
である。これにより、耐湿性の高い半導体装置が提供で
きるのである。FIG. 6 shows another embodiment of the present invention, in which the tab leads 3 are arranged so that the top surface 4a of the leads coincides with the height of the top surface of the semiconductor chip 1 in order to avoid contact of the wire 8 to the edge of the semiconductor chip 1. FIG. 3 is a front cross-sectional view when a titanium oxide film 9 is applied to the side, upper and lower surface portions of the tab lead 3 after the tab lead 3 is bent. What should be noted here is that since the titanium oxide film 9 is provided on the side, top, and bottom surfaces of the tab lead 3, the water intrusion route is completely cut off. This makes it possible to provide a semiconductor device with high moisture resistance.
第７図乃至第１２図は本発明の他の実施例であって、リ
ードフレーム１８上に半導体チップ１を組み立て樹脂封
止するプロセスの工程断面図（一部平面図）である。FIGS. 7 to 12 show other embodiments of the present invention, and are process cross-sectional views (partial plan views) of the process of assembling the semiconductor chip 1 on the lead frame 18 and sealing it with resin.
以下各工程に従りて詳述する。Each step will be explained in detail below.
（１）第７図、第８図に示すようにリードフレーム１８
を用意する。このリードフレーム１８は半導体チップ１
を取付けるためのタブ２とタブ２を支持するタブリード
３とタブ２周辺に配設された複数のリード４とリード４
及びタブリード３間な接続するように設けたダム（枝部
）１０及び図示されないフレーム（外枠部）からなる一
枚の金属板から打抜かれた通常のリードフレーム１８で
ある。(1) As shown in FIGS. 7 and 8, the lead frame 18
Prepare. This lead frame 18 is a semiconductor chip 1
A tab 2 for attaching the tab 2, a tab lead 3 supporting the tab 2, and a plurality of leads 4 arranged around the tab 2.
A lead frame 18 is a normal lead frame 18 punched out of a single metal plate consisting of a dam (branch portion) 10 provided to connect between the tab leads 3 and a frame (outer frame portion) not shown.
（２）タブリードの上下両面（両側面も含む）に液体状
のチタン酸化膜形成材１１を塗布する。このチタン酸化
膜形成材としては、たとえば、チタンエステル、チタン
アシレート、チタンキレートの１′ｍ又は２ｓ以上の混
合物を使用する。そしてチタン酸化膜形成材１】の塗布
は第９図に示すように、タブリード３の上方及び下刃に
設置したディスペンサ１２を上下に動作させてタブリー
ド３０所要部分に塗布するものである。(2) Apply liquid titanium oxide film forming material 11 to both the upper and lower surfaces (including both sides) of the tab lead. As the titanium oxide film forming material, for example, a mixture of titanium ester, titanium acylate, and titanium chelate of 1'm or 2s or more is used. As shown in FIG. 9, the titanium oxide film forming material 1 is applied to the desired portions of the tab lead 30 by moving the dispenser 12 installed on the upper and lower blades of the tab lead 3 up and down.
このとき、別の銀ペースト用ディスペンサ１２を使用し
て銀ペースト１３をタブ２の上面（ペレット付位置）に
塗布する。At this time, another silver paste dispenser 12 is used to apply silver paste 13 to the upper surface of the tab 2 (the pellet attachment position).
（３）このあと第１０図に示すようにベレットボンダ１
４を用いてＩＣチップ１をタブ２上に接続（ペレットボ
ンディング）スる。(3) After this, as shown in Figure 10, the bellet bonder 1
4 to connect the IC chip 1 onto the tab 2 (pellet bonding).
（４） ひきつづいて１５０℃、１５分間のエアベーク
を行い、銀ペースト１２及びチタン酸化膜形成材】１の
溶剤を揮散させ、銀を含む接着層１９にチタン酸化膜９
に変える（図示されない）。(4) Subsequently, air baking was performed at 150° C. for 15 minutes to volatilize the silver paste 12 and the solvent in [Titanium oxide film forming material] 1, and form a titanium oxide film 9 on the adhesive layer 19 containing silver.
(not shown).
（５） このあと第１１図に示すようにワイヤポンダ１
５を使用し、ＩＣチップ１表面の電極１７（ポンディン
グパッド）と周辺のリード４との間を金ワイヤ９で接続
（ワイヤボンディング）する。(5) After this, as shown in Figure 11, wireponder 1
5, the electrode 17 (ponding pad) on the surface of the IC chip 1 and the peripheral leads 4 are connected with a gold wire 9 (wire bonding).
（６）さいごに第１２図に示す樹脂モールド型の金型１
６内にリードフレーム１８を装填し、エポキシ樹脂等の
トランスファモールドにより樹脂成形体５で封止する。(6) Finally, the resin mold mold 1 shown in Figure 12.
A lead frame 18 is loaded into the inside of the lead frame 6 and sealed with a resin molded body 5 by transfer molding of epoxy resin or the like.
なお、樹脂封止されたリードフレーム１８は型から取り
出してダム８を切り取ることによりリード４間を電気的
に分離し、ここに樹脂封止形半導体装置が完成する。The resin-sealed lead frame 18 is taken out of the mold and the dam 8 is cut out to electrically isolate the leads 4, thereby completing a resin-sealed semiconductor device.
以上の実施例で述べた本発明によれば下記のように効果
が得られる。According to the present invention described in the above embodiments, the following effects can be obtained.
（１） タブリード表面に形成されたチタン酸化物は電
子顕微鏡観察によれば極めて粗い面をもっており、金属
に対しての接合性を有するとともに樹脂との密着性も大
きいことが実験的に確認されており、これによってタブ
リード下に隙き間の生じることがなくなり、したがって
水分の侵入を阻止しアルミニウムからなる配線やポンデ
ィングパッドの腐食を防止することができる。(1) The titanium oxide formed on the surface of the tab lead has an extremely rough surface according to electron microscopy, and it has been experimentally confirmed that it has bonding properties to metals and also has high adhesion to resins. This eliminates the formation of a gap under the tab lead, thereby preventing moisture from entering and corrosion of the wiring and bonding pads made of aluminum.
本発明者等の実験によれば、チタン酸化膜を塗布しない
場合、初期アルミニウム腐食発生率がたとえば数百ｐｐ
ｍであるのに対し、チタン酸化膜処理することによって
ほとんどｏ ｐｐｍに低減スルトいう結果が得られた。According to experiments conducted by the present inventors, when a titanium oxide film is not applied, the initial aluminum corrosion incidence rate is, for example, several hundred pp.
However, by treating the titanium oxide film, the sult was reduced to almost 0 ppm.
このことＫよりＩＣの信頼性を大幅に向上することが可
能となった。This makes it possible to significantly improve the reliability of the IC.
（２） タブリードへのチタン酸化膜形成材の塗布は銀
ペースト塗布に使用しているディスペンサと同様なもの
が使用でき、タブへの銀ペースト塗布と同時工程で行え
ることにより、新たな工程を付加することにならないこ
とより、安価な半導体装置を提供できる。(2) The same dispenser used for silver paste application can be used to apply the titanium oxide film forming material to the tab lead, and this can be done at the same time as the silver paste application to the tab, adding a new process. Since there is no need to do this, it is possible to provide an inexpensive semiconductor device.
以上本発明者によってなされた発明を実施例にもとつき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能である。Although the invention made by the present inventor has been specifically explained above based on the examples, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof.
たとえば、タブリードに塗布する樹脂との接合性を向上
させる物質はチタン酸化物に限らす、他の適当な金属酸
化物を用いることができる。For example, the substance applied to the tab lead that improves the bondability with the resin is not limited to titanium oxide, but other suitable metal oxides can be used.
チタン酸化膜形成材はタブリード以外にタブの下面及び
リードの下面全面にあらかじめ塗布しておいてもよい。In addition to the tab lead, the titanium oxide film forming material may be applied in advance to the bottom surface of the tab and the entire bottom surface of the lead.
し利用分野〕
本発明は樹脂封止形半導体装置の全てに応用することが
できる。Field of Application] The present invention can be applied to all resin-sealed semiconductor devices.
第１図は樹脂封止形半導体装置の一例を示す平面図、
第２図は第１図におけるＡ−Ａ’断面図、第３図は樹脂
封止形半導体装置の他の例を示す断面図、
第４図は本発明の一実施例であって樹脂封止形半導体装
置の平面図、
第５図は第４図におけるＡ−Ａ’断面図、第６図は本発
明の他の一実施例であって樹脂封止半導体装置の断面図
、
第７図はリードフレームの平面図、
第８図は第７図のＡ−Ａ′断面図、
第９図はＡｇペースト、チタン酸化膜形成材の塗布工程
を示す断面図、
第１０図はペレット付は工程を示す断面図、第１１図は
ワイヤボンディング工程を示す断面図、
第１２図はモールド工程を示す断面図である。
】・・・半導体チップ、２・・・タブ、３・・・タブリ
ード、４・・・リード、５・・・樹脂成形体、６・・・
隙き間、７・・・折り曲げ部、８・・・金属ワイヤ、９
・・・酸化チタン膜、１０・・・ダム、１１・・・醇化
チタン膜形成材、１２・・・ティスペンサ、１３・・・
銀ペースト、１４・・・ペレットボンダ、１５・・・ワ
イヤボンダ、１６・・・金型、１７・・・ポンディング
パッド、１８・・・リードフレーム、１９・・・９９層
（Ａｇペースト）。
第 １ 図
第 ２ 図
第 ４ 図
第 ５ 図
第 ７ 図
第 ９ 図FIG. 1 is a plan view showing an example of a resin-sealed semiconductor device, FIG. 2 is a sectional view taken along line AA' in FIG. 1, and FIG. 3 is a sectional view showing another example of a resin-sealed semiconductor device. , FIG. 4 is a plan view of a resin-sealed semiconductor device according to an embodiment of the present invention, FIG. 5 is a sectional view taken along line AA' in FIG. 4, and FIG. 6 is a plan view of another embodiment of the present invention. Examples are a cross-sectional view of a resin-sealed semiconductor device, FIG. 7 is a plan view of a lead frame, FIG. 8 is a cross-sectional view taken along line AA' in FIG. 7, and FIG. 9 is a cross-sectional view of Ag paste and titanium oxide film forming material. FIG. 10 is a cross-sectional view showing the pellet attachment process, FIG. 11 is a cross-sectional view showing the wire bonding process, and FIG. 12 is a cross-sectional view showing the molding process. ]...Semiconductor chip, 2...Tab, 3...Tab lead, 4...Lead, 5...Resin molded body, 6...
Gap, 7...Bending portion, 8...Metal wire, 9
...Titanium oxide film, 10...Dam, 11...Titanium oxide film forming material, 12...Tispensa, 13...
Silver paste, 14... Pellet bonder, 15... Wire bonder, 16... Mold, 17... Bonding pad, 18... Lead frame, 19... 99 layers (Ag paste). Figure 1 Figure 2 Figure 4 Figure 5 Figure 7 Figure 9
Claims (1)
属からなるタブと、タブを支持するタブリードと、タブ
周辺に配設された複数のリード及び半導体チップ、タブ
、リードの一部を包囲し封止する樹脂成形体からなる半
導体装置であって、上記タブリードの表面に樹脂成形体
との接着性の良好な金属酸化物膜が施されていることを
特徴とする半導体装置。 ２、上記金属酸化物は二酸化チタンである特許請求の範
囲第１項に記載の半導体装置。 ３、 タブ、タブリード及び複数のリードとが一体にな
っているリードフレーム上に半導体チップを接続し、半
導体素子上の電極と各リードとの間をワイヤにより接続
した後、上記半導体素子を封止するＪうに樹脂成形する
半導体装置の製造方法において、上記リードフレームの
タブ面に銀ペーストを塗布するとともにタブリード面Ｋ
ｍ化物形成材を塗布し、半導体チップをタブ上に接続し
た後上記酸化物形成材を焼付けることを特徴とする半導
体装置の製造方法。 ４、上記銀ペースト及び上記酸化物形成材の塗布はディ
スペンサを使用して同時に塗布する特Ｗ！ｆ請求の範囲
第３項に記載の半導体装置の製造方法。[Claims] 1. A semiconductor chip, a tab made of metal for fixing the semiconductor chip, a tab lead that supports the tab, a plurality of leads arranged around the tab, and a semiconductor chip, a tab, and a lead. A semiconductor device comprising a resin molded body partially surrounding and sealed, the semiconductor device characterized in that a metal oxide film having good adhesion to the resin molded body is applied to the surface of the tab lead. . 2. The semiconductor device according to claim 1, wherein the metal oxide is titanium dioxide. 3. After connecting the semiconductor chip onto a lead frame in which the tab, tab lead, and multiple leads are integrated, and connecting the electrodes on the semiconductor element and each lead with wires, the semiconductor element is sealed. In the method for manufacturing a semiconductor device by resin molding, silver paste is applied to the tab surface of the lead frame, and the tab lead surface K is also coated with silver paste.
1. A method of manufacturing a semiconductor device, comprising applying an oxide-forming material, connecting a semiconductor chip onto the tab, and then baking the oxide-forming material. 4. The silver paste and the oxide forming material are applied at the same time using a dispenser! f. A method for manufacturing a semiconductor device according to claim 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59078452A JPS60223147A (en) | 1984-04-20 | 1984-04-20 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59078452A JPS60223147A (en) | 1984-04-20 | 1984-04-20 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60223147A true JPS60223147A (en) | 1985-11-07 |
Family
ID=13662426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59078452A Pending JPS60223147A (en) | 1984-04-20 | 1984-04-20 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60223147A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5263242A (en) * | 1991-05-07 | 1993-11-23 | Cn Industries Ltd. | Method of making semiconductor package with segmented lead frame |
| US5452511A (en) * | 1993-11-04 | 1995-09-26 | Chang; Alexander H. C. | Composite lead frame manufacturing method |
-
1984
- 1984-04-20 JP JP59078452A patent/JPS60223147A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5263242A (en) * | 1991-05-07 | 1993-11-23 | Cn Industries Ltd. | Method of making semiconductor package with segmented lead frame |
| US5452511A (en) * | 1993-11-04 | 1995-09-26 | Chang; Alexander H. C. | Composite lead frame manufacturing method |
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