JPS63310149A - Package for highly integrated ic and its manufacture - Google Patents

Package for highly integrated ic and its manufacture

Info

Publication number
JPS63310149A
JPS63310149A JP62146773A JP14677387A JPS63310149A JP S63310149 A JPS63310149 A JP S63310149A JP 62146773 A JP62146773 A JP 62146773A JP 14677387 A JP14677387 A JP 14677387A JP S63310149 A JPS63310149 A JP S63310149A
Authority
JP
Japan
Prior art keywords
lead
package
bonding
tab
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62146773A
Other languages
Japanese (ja)
Inventor
Mamoru Onda
護 御田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP62146773A priority Critical patent/JPS63310149A/en
Publication of JPS63310149A publication Critical patent/JPS63310149A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To mount a large-sized device without changing an external size of a package and to bond a tip part of a lead frame directly and collectively without using a wire by a method wherein a recessed part is formed at a tab part and an electrode part and a lead part of a device are connected electrically in a direct coupling manner via a solder bump. CONSTITUTION:In a lead frame 10, a recessed part 2 corresponding to a shape of a lead tip part 30 is formed at a side face of a tab part 1. As a package the lead frame 10 is used; furthermore, a bump 7 is formed at an electrode part 60 of a device 6. Simultaneously with a bonding operation of the device, the lead tip part 30 of the lead frame 10 is brought into contact with the bump 7 by a positioning operation of the device; the lead tip part 30 is heated; the electrode part 60 and the lead tip part 30 are connected electrically via the bump 7. By this setup, even when a large-sized device is mounted, it is gang- bonded directly and collectively without increasing a size of a package structure; a wire bonding operation is not required.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、高集積化IC用パッケージ等に用いられ、特
に、外形寸法をかえずに従来より大型素子が塔載でき、
製造工程の簡易な高集積化IC用パッケージおよびその
製造方法に関する。
[Detailed Description of the Invention] <Industrial Application Field> The present invention is used for highly integrated IC packages, etc., and in particular, it is possible to mount larger elements than conventional ones without changing external dimensions.
The present invention relates to a highly integrated IC package with a simple manufacturing process and a manufacturing method thereof.

〈従来の技術〉 従来、高集積化IC用等に用いられるパッケージの構造
は、第3図に示すように、リードフレーム3のタブ部1
に素子付用の銀ペースト剤等の導電性ペースト9により
素子6を取付けて、ボンディングワイヤ8により素子の
電極部11とリードフレーム3のリード先端部とを接続
し、封止部5を樹脂で封止する方式がとられている。
<Prior art> Conventionally, the structure of a package used for highly integrated ICs, etc. is as shown in FIG.
The element 6 is attached using conductive paste 9 such as silver paste for attaching the element, the electrode part 11 of the element is connected to the lead tip of the lead frame 3 by the bonding wire 8, and the sealing part 5 is made of resin. A method of sealing is used.

しかし従来方式は、パッケージ2oの封止信頼性を確保
する為とリードの抜けを防ぐ為に、封止部5中のリード
の長さaを現状以上に短かくすることが出来ない。 こ
の−ことから大型の素子を取付ける場合には必然的にパ
ッケージ構造の大型化をともなう。 しかしパッケージ
の外形寸法は諸規格(JIS、SEMI)で抑えられて
おり、規格外に大型にすることは不可能である。
However, in the conventional method, in order to ensure sealing reliability of the package 2o and to prevent the leads from coming off, the length a of the leads in the sealing portion 5 cannot be made shorter than the current length. For this reason, when a large-sized element is attached, the package structure inevitably becomes larger. However, the external dimensions of the package are limited by various standards (JIS, SEMI), and it is impossible to make the package larger than the standard.

この為同一素子形状でより高集積の素子を作ることが試
みられるが、微細配線技術にも限界があり、より大型の
素子が封止出来るパッケージの構造が求められている。
For this reason, attempts are being made to create more highly integrated elements with the same element shape, but there are limits to fine wiring technology, and there is a need for a package structure that can seal larger elements.

具体的に形状寸法をあげて説明すると、封止部5中にあ
るリードの長さaは、通常最小(MIN、)で1.0m
mが求められているのに対して、パッケージ20の外形
寸法は6.3+nmである。 またワイヤボンディング
距離cはMIN、0.3mm必要である。 このことか
らパッケージの有効収納路@ d = 6.3−2 (
1,o +0−3) = 3.7 mmが、従来パッケ
ージの限界有効収納距離となる。
To explain the shape and dimensions specifically, the length a of the lead in the sealing part 5 is usually 1.0 m at the minimum (MIN).
m is required, whereas the external dimensions of the package 20 are 6.3+nm. Further, the wire bonding distance c is required to be MIN, 0.3 mm. From this, the effective storage path of the package @ d = 6.3-2 (
1, o +0-3) = 3.7 mm is the limit effective storage distance of the conventional package.

また、金線等のワイヤを用いてワイヤボンディングする
ことに伴う問題点もあり、以下の点での改良か望まれて
いる。
Furthermore, there are problems associated with wire bonding using wires such as gold wires, and improvements in the following points are desired.

1、パッケージ有効収納距離を大きく取れない。1. The effective storage distance of the package cannot be increased.

2、ワイヤボンディングをおこなう為、ICの組立工程
の所要時間が長く能率が悪い。
2. Since wire bonding is performed, the IC assembly process takes a long time and is inefficient.

3、腐食によるワイヤ切れ等があり、ICの信頼性が低
い。
3. There are wire breaks due to corrosion, and the reliability of the IC is low.

〈発明が解決しようとする問題点〉 本発明の目的は、パッケージの外型寸法をかえずに、よ
り大型の素子が塔載でき、ワイヤを用いずに、リードフ
レーム先端を直接に一括ボンディングできる構造の高集
積化IC用パッケージおよびその製造方法を提供しよう
とする。
<Problems to be Solved by the Invention> The purpose of the present invention is to enable mounting of a larger element without changing the external dimensions of the package, and to enable direct bulk bonding of the tips of lead frames without using wires. An object of the present invention is to provide an IC package with a highly integrated structure and a method for manufacturing the same.

く問題点を解決するための手段〉 本発明の第1の態様は、素子と、該素子を接着剤により
接着するタブ部と、該タブ部附近に位置して該素子と電
気的に接続されるリード部と、これらを外部から保護す
る封止部とを有する高集積化IC用パッケージにおいて
、 前記タブ部は、前記リード部先端が所定の間隔を保
ちつつ互いに嵌め込まれるような前記リード部先端形状
に対応する凹部を有し、前記素子の電極部と前記リード
部とが半田バンブを介する直接接合で電気的に接続され
てなる高集積化IC用パッケージを提供する。
A first aspect of the present invention includes an element, a tab portion for bonding the element with an adhesive, and a tab portion located near the tab portion and electrically connected to the element. In the highly integrated IC package, the tab portion is arranged so that the tips of the lead portions are fitted into each other while maintaining a predetermined interval. The present invention provides a highly integrated IC package having a concave portion corresponding to the shape, and in which the electrode portion of the element and the lead portion are electrically connected by direct bonding via a solder bump.

本発明の第2の態様は、素子を接着剤によりタブ部に接
着し、該素子とリード部とを電気的に接続して高集積化
IC用パッケージを製造するに際し、前記素子の前記タ
ブ部への接着と、前記素子の前記リード部への電気的接
続を同一工程で行う高集積化IC用パッケージの製造方
法を提供する。
In a second aspect of the present invention, when manufacturing a highly integrated IC package by bonding an element to a tab portion with an adhesive and electrically connecting the element and a lead portion, the tab portion of the element may be Provided is a method for manufacturing a package for a highly integrated IC, in which adhesion to the semiconductor device and electrical connection of the device to the lead portion are performed in the same process.

ここで、前記タブ部は、その表面に前記素子接着用の接
着剤層を有することが良い。
Here, the tab portion preferably has an adhesive layer for adhering the element on its surface.

また、前記タブ部は、前記リード部先端が所定の間隔を
保ちつつ互いに嵌め込まれるような前記リード部先端形
状に対応する凹部を有することが好ましい。
Further, it is preferable that the tab portion has a recess corresponding to the shape of the lead portion tips such that the lead portion tips are fitted into each other while maintaining a predetermined interval.

〈発明の構成〉 以下に図面に示す好適実施例について、本発明の詳細な
説明する。
<Configuration of the Invention> The present invention will be described in detail below with reference to preferred embodiments shown in the drawings.

第1図は、本発明のパッケージ20に用いるリードフレ
ーム10の斜視図である。  リードフレーム10は、
中央にIC等の素子が塔載されるタブ部1と、リード先
端部30を有するリード部3とを有する。
FIG. 1 is a perspective view of a lead frame 10 used in a package 20 of the present invention. The lead frame 10 is
It has a tab part 1 in the center on which an element such as an IC is mounted, and a lead part 3 having a lead tip part 30.

本発明に用いるリードフレーム10は、タブ部1のリー
ド部3に対している側面部の形状に特徴があり、タブ部
1の側面部が、リード先端部30の形状に対応した凹部
2を有する。 凹部2は、リード先端部30に対応した
位置に、対応した形状で設けられ、リード先端部30が
凹部2と所定の間隔を保ちつつ互いに嶽め込まれて位置
するよう構成される。− 第1図に示す例では、長方形状のリード先端部30のお
のおのの形状に対応して、タブ部1は、側面部に長方形
状の凹部2を有するが、これらの形状に限定されるもの
ではなく、いかなる形状でも対応したものであればよい
The lead frame 10 used in the present invention is characterized by the shape of the side surface of the tab portion 1 facing the lead portion 3, and the side surface portion of the tab portion 1 has a recess 2 corresponding to the shape of the lead tip portion 30. . The recess 2 is provided in a shape corresponding to the lead tip 30 at a position corresponding to the lead tip 30, and is configured such that the lead tip 30 and the recess 2 are fitted into each other while maintaining a predetermined distance. - In the example shown in FIG. 1, the tab portion 1 has a rectangular recess 2 on the side surface corresponding to each shape of the rectangular lead tip portion 30, but the tab portion 1 is not limited to these shapes. Instead, it can be of any shape as long as it is compatible.

第5図に示すように、リード先端部30の形状をカギ状
とした場合は、タブ部1の側面部に形成される凹部2は
、カギ状の凹部2となる。
As shown in FIG. 5, when the lead tip 30 has a hook-like shape, the recess 2 formed in the side surface of the tab portion 1 becomes a hook-shaped recess 2.

従来のリードフレーム10の斜視図を、第4図に示す。A perspective view of a conventional lead frame 10 is shown in FIG.

 従来は、タブ部1が素子6の形状とほぼ相似の略矩形
であり、リード部先端部30とタブ部1の側面部の形状
は無関係であった。
Conventionally, the tab portion 1 has a substantially rectangular shape that is substantially similar to the shape of the element 6, and the shapes of the lead portion tip portion 30 and the side portions of the tab portion 1 are unrelated.

本発明に用いるリードフレーム10の材質は、いかなる
ものでもよいが、銅系(Sn人無酸素銅)や4270イ
等が代表的に挙げられる。 リードフレーム材を上記の
形状とするには、いかなる方法でもよいが、プレス打抜
き法が好適である。
The lead frame 10 used in the present invention may be made of any material, but typical examples include copper-based (Sn-oxygen-free copper) and 4270I. Although any method may be used to form the lead frame material into the above shape, press punching is preferred.

素子6が塔載されるタブ部1は、あらかじめ、素子6を
接着するための接着剤層4を設けておくのが好ましい。
It is preferable that the tab portion 1 on which the element 6 is mounted is provided with an adhesive layer 4 for adhering the element 6 in advance.

 接着剤層4は、エポキシ樹脂、ポリイミド樹脂、ポリ
アミドイミド樹脂等を、あらかじめタブ部1上に印刷法
等でコーティングして設け、後に素子6を塔載して加熱
硬化等で接着硬化させる。
The adhesive layer 4 is provided by coating an epoxy resin, polyimide resin, polyamide-imide resin, etc. on the tab portion 1 in advance by a printing method or the like, and then the element 6 is placed thereon and the adhesive is cured by heat curing or the like.

本発明のパッケージ20は、前述のリードフレーム10
を用い、さらに素子6の電極部60にバンブ7を設けて
おく。 素子付けと同時に、素子の位置決めによりリー
ドフレーム10のリード先端部30を、バンブ7に当接
し、リード先端部30を加熱して、電極部60とリード
先端部30をバンブ7を介して電気的に接続する。
The package 20 of the present invention includes the lead frame 10 described above.
Further, a bump 7 is provided on the electrode portion 60 of the element 6. At the same time as attaching the element, the lead tip part 30 of the lead frame 10 is brought into contact with the bump 7 by positioning the element, the lead tip part 30 is heated, and the electrode part 60 and the lead tip part 30 are electrically connected via the bump 7. Connect to.

多数のり−ト先端部30が、対応する素子の電極部60
に、直接一括してギヤングボンディングされ、ワイヤボ
ンディングが不要である。
A large number of glue tips 30 connect to the electrode portions 60 of the corresponding elements.
It is directly and collectively bonded by gigang bonding, eliminating the need for wire bonding.

バンブ7は、良導電性の半田バンブであればいかなるも
のでもよいが、5n60%pbの半田バンブや金バンブ
が好適に用いられる。
The bump 7 may be any solder bump with good conductivity, but 5n60%pb solder bumps and gold bumps are preferably used.

リード先端部30は、銅系等のリードフレーム素材のま
までもよいが、リードフレーム素材上にあらかじめ半田
めっき等を設けておくと、バンブ7との密着性が良好と
なる。
The lead tip portion 30 may be made of a lead frame material such as copper, but if solder plating or the like is provided on the lead frame material in advance, the adhesion with the bump 7 will be improved.

本発明の高集積化IC用パッケージは、好ましくは以下
の方法で製造する。
The highly integrated IC package of the present invention is preferably manufactured by the following method.

好ましくは、第1図、第5図等に示すリードフレーム1
0を成形する(本発明の製造方法は、第4図に示す従来
例のリードフレーム10を用いてもよい)。
Preferably, the lead frame 1 shown in FIGS. 1, 5, etc.
0 (the manufacturing method of the present invention may use the conventional lead frame 10 shown in FIG. 4).

第2図に示すように、タブ部1の素子接着面にはあらか
じめ接着剤層4を印刷法等でコーティングして設けてお
くのが好ましい。素子6の電極部60には、あらかじめ
半田バンブ7を電気めっき法等により設けておき、素子
6を接着剤層4に取付けて加熱硬化させながら、バンプ
7をインナーリード先端部30に加熱溶融しつつ接合し
、同一工程で素子付けとギヤングボンディングを行う。
As shown in FIG. 2, it is preferable that the element adhesion surface of the tab portion 1 is coated with an adhesive layer 4 in advance by a printing method or the like. A solder bump 7 is provided in advance on the electrode portion 60 of the element 6 by electroplating or the like, and while the element 6 is attached to the adhesive layer 4 and cured by heating, the bump 7 is heated and melted onto the inner lead tip 30. They are then joined together, and element attachment and gigantic bonding are performed in the same process.

上記の製造方法による場合は、素子付けと、ギヤングボ
ンディングを同一工程で行うので、素子付けの接着剤と
、ギヤングボンディングのバンブは同一温度範囲で接着
や電気的接続が行える材料を選ぶ。
In the case of the above-mentioned manufacturing method, since element attachment and gigantic bonding are performed in the same process, the adhesive for attaching the element and the bump for gigantic bonding are selected from materials that can be bonded and electrically connected within the same temperature range.

〈実施例〉 以下に実施例により本発明を具体的に説明する。<Example> The present invention will be specifically explained below using Examples.

(実施例1) 第1図に示す凹部2を有するリードフレーム10を用い
て、18ビンDILP標準パツケージを試作した。
(Example 1) An 18-bin DILP standard package was prototyped using a lead frame 10 having a recess 2 shown in FIG.

銅系のリードフレーム(0,25t、Sn人無酸素銅)
材を用い、プレス打抜き法により製造した。リード先端
部30のタブ部1への食いこみ1立(第1図参照)は、
0.5in+で設計した。
Copper lead frame (0.25t, Sn oxygen-free copper)
It was manufactured using press punching method. The biting of the lead tip 30 into the tab 1 (see Figure 1) is as follows:
It was designed with 0.5in+.

封止部5中のり−ド3の長ga(第3図参照)を1.O
mm全全長63mmのパッケージとし、有効収納距I’
d(第3図参照)は、d=6.3−2 (1,0−0,
5) =5.3amであった。
The length ga (see FIG. 3) of the glue 3 in the sealing part 5 is set to 1. O
The package has a total length of 63 mm, and the effective storage distance I'
d (see Figure 3) is d=6.3-2 (1,0-0,
5) = 5.3 am.

タブ部1の素子塔載面にはエポキシ接着剤をあらかじめ
印刷法でコーティングして置き、素子の取付時にはリー
ドフレームを200℃に加熱し硬化させながら素子を押
し付けて素子付けした。 また素子付けと同時に素子の
位置決めによりリードフレームのリード先端部30を素
子6の電極部60に当接させてリード先端部30を20
0℃に加熱してボンディングした。
The element mounting surface of the tab portion 1 was coated with epoxy adhesive in advance by a printing method, and when the element was attached, the element was attached by pressing the element while heating the lead frame to 200° C. and hardening it. Also, at the same time as attaching the element, the lead tip part 30 of the lead frame is brought into contact with the electrode part 60 of the element 6 by positioning the element.
Bonding was performed by heating to 0°C.

素子6の電極部60には、20±5μの半田バンプ(S
n60%pb)を電気めっき法により形成しておき、こ
の部分とリード先端部を接合した。
The electrode part 60 of the element 6 is provided with a solder bump (S) of 20±5μ.
n60% pb) was formed by electroplating, and this portion and the lead tip were joined.

リード先端部30は銅素地のまま、あるいは半田の接合
性の信頼を高める為に銀めっき(約4μ)が施されるが
、本実施例ではめっきなしで接合させたが、特に問題は
なかった。
The lead tips 30 are either made of copper or are plated with silver (approximately 4μ) to increase the reliability of solder bonding, but in this example, they were bonded without plating, and there were no particular problems. .

(比較例1) 第4図に示す従来のリードフレームを用い、Cuボンデ
ィングワイヤ30μφを用いてワイヤボンディングし、
実施例1と同様の18ビンDILP標準パツケージを作
成した。
(Comparative Example 1) Using the conventional lead frame shown in FIG. 4, wire bonding was performed using a Cu bonding wire of 30μφ,
An 18-bin DILP standard package similar to Example 1 was prepared.

実施例1と比較例1について、表1に示す項目を比較し
、結果を表1に示した。
Regarding Example 1 and Comparative Example 1, the items shown in Table 1 were compared, and the results are shown in Table 1.

なお、性能は38個試作中の不良発生数で示したが、試
験条件は以下に記す(EIAJIC−121による)。
Note that the performance was shown by the number of defects generated during 38 prototypes, and the test conditions are described below (according to EIAJIC-121).

(1)蒸気加圧試験 水蒸気圧 2気圧、温度 121℃、 1000時間後の電気的動作試験による不良数を測定。(1) Steam pressurization test Water vapor pressure: 2 atm, temperature: 121℃, The number of defects was measured by electrical operation test after 1000 hours.

(2)耐湿性試験 RH90±5%、40±2℃、 1000時間後の電気的動作試験による不良数を測定。(2) Moisture resistance test RH90±5%, 40±2℃, The number of defects was measured by electrical operation test after 1000 hours.

(3)温湿度サイクル試験 RH90〜96%、 1サイクル 高温側65℃ 3.Oh 低温側25℃ 2.0h 1000時間後の電気的動作試験による不良数を測定。(3) Temperature and humidity cycle test RH90-96%, 1 cycle high temperature side 65℃ 3. Oh Low temperature side 25℃ 2.0h The number of defects was measured by electrical operation test after 1000 hours.

(実施例2) 実施例1と同構造でリードフレーム材に4270イを用
いた。 但し半田バンプとの接合を得る為にリード先端
部30に4μの銀めっきを施した。
(Example 2) It had the same structure as Example 1, but 4270I was used as the lead frame material. However, the lead tips 30 were plated with 4μ silver in order to achieve bonding with the solder bumps.

(実施例3) 実施例2と同様に、ただし塔載素子に金バンプ付きの素
子を用いたこの基合金と銀との接合は、拡散接合であり
、300℃までの昇温か必要であった為、フレームの温
度を300℃に昇温させた。 また素子接着剤は耐熱性
の高いポリイミド接着剤をあらかじめ印刷法によりコー
ティングされたリードフレームを使用した。
(Example 3) Same as Example 2, except that the base alloy and silver were bonded by diffusion bonding using an element with gold bumps as a mounting element, and it was necessary to raise the temperature to 300 ° C. Therefore, the temperature of the frame was raised to 300°C. The element adhesive used was a lead frame coated with a highly heat-resistant polyimide adhesive using a printing method.

(実施例4) 実施例1と同様のリードフレーム10を用いて、同様の
18ビンDILP標準パツケージを試作した。 ただし
搭載素子に金バンプ付きの素子を用い、リード先端部3
0のめっきは無電解のSnめっき0,5μを用いた。
(Example 4) Using the same lead frame 10 as in Example 1, a similar 18-bin DILP standard package was prototyped. However, if the mounted element is an element with gold bumps, the lead tip 3
For the 0 plating, electroless Sn plating 0.5μ was used.

この場合、金バンブとの接合はAu−3nの共晶反応接
合により行われた。 Au−5nの共晶反応温度は22
0℃〜230℃であり比較的低温で接合できる利点があ
る。
In this case, the bonding with the gold bump was performed by Au-3n eutectic reaction bonding. The eutectic reaction temperature of Au-5n is 22
The temperature is 0°C to 230°C, which has the advantage of being able to bond at a relatively low temperature.

〈発明の効果〉 本発明により下記の結果が得られた。<Effect of the invention> The following results were obtained according to the present invention.

1、封止収納面積のアップ 例えば従来型パッケージに対して43%upの収納面積
となる。
1. Increase in sealed storage area For example, the storage area is increased by 43% compared to a conventional package.

チップの配線技術が同レベルの場合、 1.43倍の記憶容量、演算容量の素子を組みこむこと
が出来る。 また同一の容量の半導体を作る場合に、素
子の微細配線に余裕を持たせることが出来る。
If the chip wiring technology is at the same level, it is possible to incorporate elements with 1.43 times the storage capacity and calculation capacity. Furthermore, when manufacturing semiconductors with the same capacity, it is possible to provide a margin for fine wiring of elements.

2、性能アップ 蒸気加圧試験(Pressure Te5t ) 、耐
湿性試験、温湿度サイクルの1000時間の試験で従来
のパッケージ構造より高い信頼性が得られた。
2. Improved Performance Steam Pressure Test (Pressure Te5t), moisture resistance test, and 1000-hour temperature/humidity cycle test showed higher reliability than the conventional package structure.

従来のボンディングワイヤを用いない為に腐食によるワ
イヤ切れによる電気的損傷がさけられる為である。
This is because conventional bonding wires are not used, so electrical damage due to wire breakage due to corrosion can be avoided.

信頼性の欠除はほとんど従来パッケージでワイヤの切断
、ワイヤと素子の接合部の腐食、ワイヤとリードフレー
ムの接合部の腐食であり本発明の場合半田バンプとの接
合面積が広い為、信頼性が非常に高まる。
In conventional packages, most of the defects in reliability are caused by wire breakage, corrosion at the joint between the wire and the element, and corrosion at the joint between the wire and the lead frame.In the case of the present invention, the reliability is improved because the joint area with the solder bump is large. increases significantly.

またモールド時のレジンの流れによるボンディングワイ
ヤ切れの心配がまったくなくなり、工程不良率1%が本
発明では0.3%に減少した。
Furthermore, there is no need to worry about the bonding wire breaking due to resin flow during molding, and the process defect rate of 1% has been reduced to 0.3% in the present invention.

3、組立作業の能率向上 御粘ポンディングおよび素子付けと同一工程で御粘ボン
ディングができ、組立時間の大幅な短縮が達成出来た。
3. Improving the efficiency of assembly work Since adhesive bonding can be performed in the same process as adhesive bonding and element attachment, a significant reduction in assembly time has been achieved.

従来のポンディングラインの1.8倍のスピードで組み
立てることが出来極めて能率的である。
It is extremely efficient and can be assembled 1.8 times faster than conventional bonding lines.

4、以上、本発明は従来のパッケージの構造の一大変革
をなすものでありボンディングワイヤの節減にもなり安
価となる。 ボンディングワイヤの省略は大幅な組立、
材料費の節減となった。
4. As described above, the present invention is a major change in the structure of conventional packages, and it also saves bonding wires, resulting in lower costs. Omission of bonding wires requires significant assembly,
This resulted in material cost savings.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明のパッケージに用いるリードフレーム
の斜視図である。 第2図は、本発明のパッケージの一実施例を示す断面図
である。リードフレームは第1図のA−A’線断面図で
示した。 第3図は、従来例のパッケージを示す断面図である。 第4図は、従来例のリードフレームを示す斜視図である
。 第5図は、本発明のパッケージに用いるリードフレーム
の他の実施例を示す線図である。 符号の説明 1・−・タブ部、 2−・凹部、 3・・・リード部、 30−・・リード先端部、 4・・・接着剤層、 40−・・絶縁ペースト、 5・・・封止部、 6・・・素子、 60−・・電極部、 7・・・バンブ、 8・・・ボンディングワイヤ、 9・・・導電性ペースト、 10−・・リードフレーム、 11−・電極部、 20−・・パッケージ FIG、4  1 FIG、5
FIG. 1 is a perspective view of a lead frame used in the package of the present invention. FIG. 2 is a sectional view showing an embodiment of the package of the present invention. The lead frame is shown in a sectional view taken along line AA' in FIG. FIG. 3 is a sectional view showing a conventional package. FIG. 4 is a perspective view showing a conventional lead frame. FIG. 5 is a diagram showing another embodiment of the lead frame used in the package of the present invention. Explanation of symbols 1--Tab part, 2--Concave part, 3--Lead part, 30--Lead tip, 4--Adhesive layer, 40--Insulating paste, 5--Sealing Stop part, 6... Element, 60-... Electrode part, 7... Bump, 8... Bonding wire, 9... Conductive paste, 10-... Lead frame, 11-... Electrode part, 20-...Package FIG, 4 1 FIG, 5

Claims (5)

【特許請求の範囲】[Claims] (1)素子と、該素子を接着剤により接着するタブ部と
、該タブ部附近に位置して該素子と電気的に接続される
リード部と、これらを外部から保護する封止部とを有す
る高集積化IC用パッケージにおいて、 前記タブ部は、前記リード部先端が所定の間隔を保ちつ
つ互いに嵌め込まれるような前記リード部先端形状に対
応する凹部を有し、 前記素子の電極部と前記リード部とが半田バンプを介す
る直接接合で電気的に接続されてなることを特徴とする
高集積化IC用パッケージ。
(1) An element, a tab portion for bonding the element with adhesive, a lead portion located near the tab portion and electrically connected to the element, and a sealing portion for protecting these from the outside. In the highly integrated IC package, the tab part has a recess corresponding to the shape of the lead part tips such that the lead part tips are fitted into each other while maintaining a predetermined interval, and the tab part has a recess part corresponding to the shape of the lead part tips, and the electrode part of the element and the A highly integrated IC package characterized in that a lead portion is electrically connected to a lead portion by direct bonding via a solder bump.
(2)前記タブ部は、その表面に前記素子接着用の接着
剤層を有する特許請求の範囲第1項に記載の高集積化I
C用パッケージ。
(2) The highly integrated I according to claim 1, wherein the tab portion has an adhesive layer for adhering the element on its surface.
Package for C.
(3)素子を接着剤によりタブ部に接着し、該素子とリ
ード部とを電気的に接続して高集積化IC用パッケージ
を製造するに際し、 前記素子の前記タブ部への接着と、前記素子の前記リー
ド部への電気的接続を同一工程で行うことを特徴とする
高集積化IC用パッケージの製造方法。
(3) When manufacturing a highly integrated IC package by bonding an element to the tab portion with an adhesive and electrically connecting the device and the lead portion, bonding the element to the tab portion; A method for manufacturing a highly integrated IC package, characterized in that electrical connection of the element to the lead portion is performed in the same step.
(4)前記タブ部は、前記リード部先端が所定の間隔を
保ちつつ互いに嵌め込まれるような前記リード部先端形
状に対応する凹部を有する特許請求の範囲第3項に記載
の高集積化IC用パッケージの製造方法。
(4) The tab portion has a recess corresponding to the shape of the lead portion tips such that the lead portion tips are fitted into each other while maintaining a predetermined interval. How the package is manufactured.
(5)前記タブ部は、その表面に前記素子接着用の接着
剤層を有する特許請求の範囲第3項または第4項に記載
の高集積化IC用パッケージの製造方法。
(5) The method for manufacturing a highly integrated IC package according to claim 3 or 4, wherein the tab portion has an adhesive layer for adhering the element on its surface.
JP62146773A 1987-06-12 1987-06-12 Package for highly integrated ic and its manufacture Pending JPS63310149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62146773A JPS63310149A (en) 1987-06-12 1987-06-12 Package for highly integrated ic and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62146773A JPS63310149A (en) 1987-06-12 1987-06-12 Package for highly integrated ic and its manufacture

Publications (1)

Publication Number Publication Date
JPS63310149A true JPS63310149A (en) 1988-12-19

Family

ID=15415217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62146773A Pending JPS63310149A (en) 1987-06-12 1987-06-12 Package for highly integrated ic and its manufacture

Country Status (1)

Country Link
JP (1) JPS63310149A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04174548A (en) * 1990-11-07 1992-06-22 Nec Corp Lead frame
KR20030025481A (en) * 2001-09-21 2003-03-29 주식회사 칩팩코리아 flip-chip semiconductor package and method of manufacturing thereof
CN110176502A (en) * 2018-02-21 2019-08-27 茂达电子股份有限公司 Optical detection apparatus and optical package structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5437469A (en) * 1977-08-29 1979-03-19 Yoshizaki Kozo Method of producing lead frame
JPS5811245B2 (en) * 1976-10-13 1983-03-02 三菱重工業株式会社 Sludge deodorization method
JPS6211438A (en) * 1985-07-08 1987-01-20 三菱電機株式会社 Nuclear magnetic resonance imaging apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5811245B2 (en) * 1976-10-13 1983-03-02 三菱重工業株式会社 Sludge deodorization method
JPS5437469A (en) * 1977-08-29 1979-03-19 Yoshizaki Kozo Method of producing lead frame
JPS6211438A (en) * 1985-07-08 1987-01-20 三菱電機株式会社 Nuclear magnetic resonance imaging apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04174548A (en) * 1990-11-07 1992-06-22 Nec Corp Lead frame
KR20030025481A (en) * 2001-09-21 2003-03-29 주식회사 칩팩코리아 flip-chip semiconductor package and method of manufacturing thereof
CN110176502A (en) * 2018-02-21 2019-08-27 茂达电子股份有限公司 Optical detection apparatus and optical package structure
CN110176502B (en) * 2018-02-21 2021-07-27 茂达电子股份有限公司 Optical detection device and optical packaging structure

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