JPS63310149A - Package for highly integrated ic and its manufacture - Google Patents

Package for highly integrated ic and its manufacture

Info

Publication number
JPS63310149A
JPS63310149A JP62146773A JP14677387A JPS63310149A JP S63310149 A JPS63310149 A JP S63310149A JP 62146773 A JP62146773 A JP 62146773A JP 14677387 A JP14677387 A JP 14677387A JP S63310149 A JPS63310149 A JP S63310149A
Authority
JP
Japan
Prior art keywords
lead
package
bump
lead frame
tip part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62146773A
Other languages
Japanese (ja)
Inventor
Mamoru Onda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP62146773A priority Critical patent/JPS63310149A/en
Publication of JPS63310149A publication Critical patent/JPS63310149A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE: To mount a large-sized device without changing an external size of a package and to bond a tip part of a lead frame directly and collectively without using a wire by a method wherein a recessed part is formed at a tab part and an electrode part and a lead part of a device are connected electrically in a direct coupling manner via a solder bump.
CONSTITUTION: In a lead frame 10, a recessed part 2 corresponding to a shape of a lead tip part 30 is formed at a side face of a tab part 1. As a package the lead frame 10 is used; furthermore, a bump 7 is formed at an electrode part 60 of a device 6. Simultaneously with a bonding operation of the device, the lead tip part 30 of the lead frame 10 is brought into contact with the bump 7 by a positioning operation of the device; the lead tip part 30 is heated; the electrode part 60 and the lead tip part 30 are connected electrically via the bump 7. By this setup, even when a large-sized device is mounted, it is gang- bonded directly and collectively without increasing a size of a package structure; a wire bonding operation is not required.
COPYRIGHT: (C)1988,JPO&Japio
JP62146773A 1987-06-12 1987-06-12 Package for highly integrated ic and its manufacture Pending JPS63310149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62146773A JPS63310149A (en) 1987-06-12 1987-06-12 Package for highly integrated ic and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62146773A JPS63310149A (en) 1987-06-12 1987-06-12 Package for highly integrated ic and its manufacture

Publications (1)

Publication Number Publication Date
JPS63310149A true JPS63310149A (en) 1988-12-19

Family

ID=15415217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62146773A Pending JPS63310149A (en) 1987-06-12 1987-06-12 Package for highly integrated ic and its manufacture

Country Status (1)

Country Link
JP (1) JPS63310149A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04174548A (en) * 1990-11-07 1992-06-22 Nec Corp Lead frame
KR20030025481A (en) * 2001-09-21 2003-03-29 주식회사 칩팩코리아 flip-chip semiconductor package and method of manufacturing thereof
CN110176502A (en) * 2018-02-21 2019-08-27 茂达电子股份有限公司 Optical detection apparatus and optical package structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5437469A (en) * 1977-08-29 1979-03-19 Yoshizaki Kozo Method of producing lead frame
JPS5811245B2 (en) * 1976-10-13 1983-03-02 Mitsubishi Heavy Ind Ltd
JPS6211438A (en) * 1985-07-08 1987-01-20 Mitsubishi Electric Corp Nuclear magnetic resonance imaging apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5811245B2 (en) * 1976-10-13 1983-03-02 Mitsubishi Heavy Ind Ltd
JPS5437469A (en) * 1977-08-29 1979-03-19 Yoshizaki Kozo Method of producing lead frame
JPS6211438A (en) * 1985-07-08 1987-01-20 Mitsubishi Electric Corp Nuclear magnetic resonance imaging apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04174548A (en) * 1990-11-07 1992-06-22 Nec Corp Lead frame
KR20030025481A (en) * 2001-09-21 2003-03-29 주식회사 칩팩코리아 flip-chip semiconductor package and method of manufacturing thereof
CN110176502A (en) * 2018-02-21 2019-08-27 茂达电子股份有限公司 Optical detection apparatus and optical package structure
CN110176502B (en) * 2018-02-21 2021-07-27 茂达电子股份有限公司 Optical detection device and optical packaging structure

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