JP2002299357A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2002299357A JP2002299357A JP2001099198A JP2001099198A JP2002299357A JP 2002299357 A JP2002299357 A JP 2002299357A JP 2001099198 A JP2001099198 A JP 2001099198A JP 2001099198 A JP2001099198 A JP 2001099198A JP 2002299357 A JP2002299357 A JP 2002299357A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- bonding wire
- semiconductor chip
- island
- semiconductor device
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は薄型の半導体装置及
びその製造方法に関するものである。The present invention relates to a thin semiconductor device and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】図５は従来の半導体装置（バイポーラト
ランジスタ）を表した断面図である。基板１上にアイラ
ンド２を設け、半導体チップ３は該アイランド２上に固
定する。内部リード５はアイランド２に近接するように
配置し、ベース電極１０やエミッタ電極（図示せず）と
導通している。ボンディングワイヤ６はボンディングパ
ッド４と内部リード５とを電気的に接続する。上記構成
の全体を樹脂７で封止することでパッケージ外形は完成
する。ベース電極１０及びコレクタ電極１１は半導体チ
ップ３の各電極を基板１裏面から外部へ導通するための
電極である。このとき、パッケージ外形は樹脂７によっ
て形成し、半導体装置内部を保護する。高さＨ２はパッ
ケージの樹脂７の肉厚相当を、高さＨ３はボンディング
ワイヤ６のループの最上点から基板１上面までの高さ
を、それぞれ表す。2. Description of the Related Art FIG. 5 is a sectional view showing a conventional semiconductor device (bipolar transistor). An island 2 is provided on a substrate 1, and a semiconductor chip 3 is fixed on the island 2. The internal lead 5 is arranged so as to be close to the island 2 and is electrically connected to the base electrode 10 and the emitter electrode (not shown). The bonding wire 6 electrically connects the bonding pad 4 and the internal lead 5. By sealing the entire structure with the resin 7, the package outer shape is completed. The base electrode 10 and the collector electrode 11 are electrodes for conducting each electrode of the semiconductor chip 3 from the back surface of the substrate 1 to the outside. At this time, the package outer shape is formed by the resin 7 to protect the inside of the semiconductor device. The height H2 represents the thickness of the resin 7 of the package, and the height H3 represents the height from the uppermost point of the loop of the bonding wires 6 to the upper surface of the substrate 1.
【０００３】[0003]
【発明が解決しようとする課題】近年、半導体デバイス
の高密度実装に伴うパッケージの小型化・薄型化のニー
ズの要請により、さらなる薄型の樹脂モールドパッケー
ジに対する需要が高まってきた。図５において、樹脂７
の肉厚を薄くすると、ボンディングワイヤ６のループの
最上部が樹脂７上方の外部に露出する可能性があるの
で、極端に薄くすることは困難である。また、ボンディ
ングワイヤ６のループを低く設定すると、今度はボンデ
ィングワイヤ６の一部と半導体チップ３とが接触して短
絡不良が生じるので、ある程度のループの高さを維持し
なければならない。この様なボンディングワイヤ６のル
ープの高さと樹脂７の厚みに関する制約が、薄型化を押
し進める際の弊害になるという欠点があった。本願は上
記課題に鑑み、パッケージの薄型化の需要に応えるもの
である。In recent years, demands for smaller and thinner packages due to high-density mounting of semiconductor devices have increased demand for thinner resin mold packages. In FIG.
Is too thin, the uppermost part of the loop of the bonding wire 6 may be exposed to the outside above the resin 7, so that it is difficult to make it extremely thin. Further, if the loop of the bonding wire 6 is set low, a part of the bonding wire 6 comes into contact with the semiconductor chip 3 to cause a short circuit failure, so that a certain level of loop height must be maintained. There is a drawback that such restrictions on the height of the loop of the bonding wire 6 and the thickness of the resin 7 cause a problem when the thickness is reduced. In view of the above problems, the present application meets the demand for a thinner package.
【０００４】[0004]
【課題を解決するための手段】本発明は、表面にボンデ
ィングパッドが形成された半導体チップと、前記半導体
チップを固着するアイランドと、前記アイランドとは離
間した位置に設けられた内部リードとを電気的に接続す
るボンディングワイヤと、前記半導体チップと前記ボン
ディングワイヤとを含めて全体を封止する樹脂とを有す
る半導体装置において、前記ボンディングワイヤが近接
する前記樹脂の表面に、絶縁物の被膜を形成したことを
特徴とする半導体装置を提供することを目的とする。According to the present invention, a semiconductor chip having a bonding pad formed on a surface thereof, an island for fixing the semiconductor chip, and an internal lead provided at a position separated from the island are electrically connected. In a semiconductor device having a bonding wire to be electrically connected and a resin for sealing the whole including the semiconductor chip and the bonding wire, an insulating film is formed on a surface of the resin where the bonding wire is close to the resin. It is another object of the present invention to provide a semiconductor device characterized by the above.
【０００５】[0005]
【発明の実施の形態】以下に本発明を、図面参照しなが
ら詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings.
【０００６】図１は本発明の一実施の形態（バイポーラ
トランジスタ）を示す断面図である。この図において、
１は絶縁性の支持基板、２はアイランド、３は半導体チ
ップ、４はボンディングパッド、５は内部リード、６は
ボンディングワイヤ、６（ａ）はボンディングワイヤ６
のループの最上部、７は樹脂７は絶縁物の被膜、９は樹
脂７の上面における内側面、１０はベース電極、１１は
コレクタ電極を、それぞれ表す。FIG. 1 is a sectional view showing an embodiment (bipolar transistor) of the present invention. In this figure,
1 is an insulating support substrate, 2 is an island, 3 is a semiconductor chip, 4 is a bonding pad, 5 is an internal lead, 6 is a bonding wire, and 6 (a) is a bonding wire 6.
, A resin 7 is an insulating film, 9 is an inner surface on the upper surface of the resin 7, 10 is a base electrode, and 11 is a collector electrode.
【０００７】この図において、基板１上にアイランド２
を設け、半導体チップ３はアイランド２上に固定する。
ボンディングパッド４は半導体チップ３上に形成され
る。内部リード５はアイランド２の近傍に配置される。
ボンディングワイヤ６は、ボンディングパッド４と内部
リード５とを電気的に接続する。ベース電極１０、コレ
クタ電極１１はそれぞれ外部と導通するための電極であ
る。In this figure, an island 2 is provided on a substrate 1.
And the semiconductor chip 3 is fixed on the island 2.
The bonding pad 4 is formed on the semiconductor chip 3. The internal lead 5 is arranged near the island 2.
The bonding wire 6 electrically connects the bonding pad 4 and the internal lead 5. The base electrode 10 and the collector electrode 11 are electrodes for conducting with the outside, respectively.
【０００８】本願の特徴は、樹脂７の表面に絶縁物８の
被膜を貼着したことにある。この絶縁物８は厚さ数十μ
ｍのポリイミドやアクリル形のテープ又はシートからな
る。絶縁物８の溶液を塗布した後、溶媒を揮発させて塗
布してもよい。このとき、樹脂７の厚みは、ボンディン
グワイヤ６の最上部６（ａ）が露出する、若しくは露出
する程度にまで薄くする。例えばワイヤ最上部６（ａ）
の位置が、設計値プラスマイナス１０％までのばらつき
を良品として生産する場合は、設計値〜プラス１０％の
位置まで樹脂７を薄くする。かかる設計を行った場合、
ばらつきの度合いによってはワイヤ最上部６（ａ）が樹
脂７の表面に露出する可能性もあるが、露出したとて絶
縁物８を設けたことによりボンディングワイヤ６が外部
と電気的短絡を起こす可能性は皆無となる。A feature of the present invention resides in that a film of an insulator 8 is adhered to the surface of a resin 7. This insulator 8 has a thickness of several tens of μ.
m of a polyimide or acrylic tape or sheet. After applying the solution of the insulator 8, the solvent may be volatilized and applied. At this time, the thickness of the resin 7 is reduced to such an extent that the uppermost portion 6 (a) of the bonding wire 6 is exposed or is exposed. For example, the wire top 6 (a)
In the case of producing a non-defective product having a variation of ± 10% from the design value, the thickness of the resin 7 is reduced to a position between the design value and ± 10%. With such a design,
Depending on the degree of variation, the wire uppermost portion 6 (a) may be exposed on the surface of the resin 7, but by providing the exposed insulator 8, the bonding wire 6 may cause an electrical short circuit with the outside. There is no gender.
【０００９】従って、ボンディングワイヤ６が露出する
ことによる危険性が皆無となるので、ワイヤ最上部６
（ａ）の上方に残す樹脂７の厚みを極限まで薄く設計す
ることができ、これによりパッケージ全体の薄型化が実
現できる。Therefore, there is no danger of the bonding wire 6 being exposed, so that the wire top 6
The thickness of the resin 7 left above (a) can be designed to be as thin as possible, thereby realizing a thinner package as a whole.
【００１０】次に、本発明の半導体装置の製造工程を以
下説明する。Next, the manufacturing process of the semiconductor device of the present invention will be described below.
【００１１】第１工程を説明する。図２は金型でモール
ドをする前の装置の状態を表した断面図である。先ずは
金属箔によってアイランド２と内部リード５を形成した
絶縁性の支持基板１を準備する。準備した状態でアイラ
ンド２とコレクタ電極１１とが、内部リード５とベース
（又はエミッタ）電極１０とがそれぞれ電気的に接続さ
れている。アイランド２上に半田又は導電性の接着材に
よって半導体チップ３をダイボンドする。その後、ワイ
ヤボンディング工程によりボンディングパッド４と内部
リード５とをボンディングワイヤ６により接続する。例
えばボールボンディング方式では、先ずボンディングワ
イヤ６の先端に形成したボール部を図示せぬキャピラリ
にてボンディングパッド４上に押圧・接着し（１ｓｔボ
ンド）、所定の軌跡にてキャピラリを移動せしめ、内部
リード５の表面に再び押圧・接着すると共にこれを切断
する（２ｎｄボンド）。このときボンディングワイヤ６
の半導体チップ３に接触することのないループ形状が、
前記キャピラリの軌跡によって与えられる。ここで基板
１の材質は、セラミックやガラスエポキシ等を使用す
る。ここまでは、従来例の技術による工程と一致する。The first step will be described. FIG. 2 is a cross-sectional view showing a state of the apparatus before molding with a mold. First, an insulating support substrate 1 having an island 2 and internal leads 5 formed by metal foil is prepared. In the prepared state, the island 2 and the collector electrode 11 are electrically connected, and the internal lead 5 and the base (or emitter) electrode 10 are electrically connected. The semiconductor chip 3 is die-bonded on the island 2 with solder or a conductive adhesive. Thereafter, the bonding pads 4 and the internal leads 5 are connected by bonding wires 6 in a wire bonding step. For example, in the ball bonding method, first, a ball portion formed at the tip of the bonding wire 6 is pressed and bonded (1st bond) on the bonding pad 4 by a capillary (not shown), and the capillary is moved along a predetermined trajectory to form an internal lead. 5 is again pressed and adhered to the surface and cut (2nd bond). At this time, the bonding wire 6
Loop shape that does not contact the semiconductor chip 3 of
It is given by the trajectory of the capillary. Here, the material of the substrate 1 is ceramic, glass epoxy, or the like. The steps up to this point correspond to the steps according to the conventional technique.
【００１２】次に第２工程を説明する。図３は図２の装
置を製造した後、基板１をモールド金型１２で上方から
嵌合した断面図である。このとき、高さＨ１は、図５の
高さＨ３よりも低くする。概ね、モールド金型１２の内
側上面部分とワイヤ最上部６（ａ）とが密着するか、あ
るいはワイヤループの高さによっては密着することもあ
り得るような状態とする。即ち、ワイヤ最上部６（ａ）
の位置が、設計値プラスマイナス１０％までのばらつき
を良品として生産する場合は、設計値〜プラス１０％の
位置まで、高さＨ１を低く設計する。斯様な設計である
と、ワイヤ最上部６（ａ）がばらつきにより高い場合に
は、モールド金型１２の内側上面部分が押圧することに
よりループ形状のワイヤ最上部６（ａ）が押しつぶされ
たような形状に加工できる。該ループのうち押しつぶさ
れた部分は、該モールド金型１２の内側上面部分と全て
密着している。結果、ボンディングワイヤ６のループの
形状は台形型となる。この台形型を形成することで、ボ
ンディングワイヤ６と半導体チップ３とが十分な距離を
保ち、両者が接触し、電気的ショートする危険性を回避
することができる。ここで、ボンディングワイヤ６のル
ープの形状は、ボンディングワイヤ６と半導体チップ３
とが十分な距離を保つことができれば、特に台形型に限
定されるものではない。Next, the second step will be described. FIG. 3 is a cross-sectional view in which the substrate 1 is fitted from above with a mold 12 after manufacturing the device of FIG. At this time, the height H1 is set lower than the height H3 in FIG. Generally, the inner upper surface portion of the mold 12 and the wire uppermost portion 6 (a) are in close contact with each other, or may be in close contact depending on the height of the wire loop. That is, the wire uppermost portion 6 (a)
In the case where the position is a non-defective product with a variation up to the design value plus or minus 10%, the height H1 is designed to be lower to a position between the design value and plus 10%. With such a design, if the wire top 6 (a) is higher due to variation, the loop-shaped wire top 6 (a) is crushed by pressing the inner upper surface of the mold 12. It can be processed into such a shape. The crushed portion of the loop is in close contact with the inner upper surface of the mold 12. As a result, the shape of the loop of the bonding wire 6 becomes trapezoidal. By forming the trapezoidal shape, the bonding wire 6 and the semiconductor chip 3 can be kept at a sufficient distance, and both can be in contact with each other, and the danger of an electrical short can be avoided. Here, the shape of the loop of the bonding wire 6 depends on the bonding wire 6 and the semiconductor chip 3.
Is not particularly limited to a trapezoidal shape as long as the distance can be maintained sufficiently.
【００１３】第３工程を説明する。図４（ａ）は上記第
２工程で嵌合させたモールド金型１２に樹脂７を封入し
パッケージが完成したときの断面図である。また図４
（ｂ）は図４（ａ）を上方からみた平面図である。第２
工程の樹脂７が硬化した後、モールド金型１２を外し半
導体装置ができる。しかし、モールド金型１２を外した
とき、ボンディングワイヤ６のループの最上部６（ａ）
が樹脂７から露出している（図４（ｂ）参照）。The third step will be described. FIG. 4A is a cross-sectional view when the resin 7 is sealed in the mold 12 fitted in the second step and a package is completed. FIG. 4
FIG. 4B is a plan view of FIG. 4A as viewed from above. Second
After the resin 7 in the process is cured, the mold 12 is removed to complete the semiconductor device. However, when the mold 12 is removed, the uppermost portion 6 (a) of the loop of the bonding wire 6
Are exposed from the resin 7 (see FIG. 4B).
【００１４】第４工程（図１参照）を説明する。樹脂外
部上面に厚さ数十μｍ程度の絶縁物８の被膜を樹脂７の
上方から貼付ける。素材として、ポリイミド系のカバー
や耐熱性のあるアクリル系のテープを用いる。絶縁物８
を被せることにより、ボンディングワイヤ６の樹脂外部
への露出は完全に防ぐことができる。The fourth step (see FIG. 1) will be described. A film of an insulator 8 having a thickness of about several tens μm is attached to the upper surface of the resin from above the resin 7. As a material, a polyimide cover or a heat-resistant acrylic tape is used. Insulator 8
The exposure of the bonding wire 6 to the outside of the resin can be completely prevented.
【００１５】上記の工程を経て、本発明の半導体装置
（図１参照）は完成する。Through the above steps, the semiconductor device of the present invention (see FIG. 1) is completed.
【００１６】現在、一般的な半導体パッケージの肉厚は
基板１の板厚が０．２０ｍｍ程度、半導体チップ３の板
厚が０．１５ｍｍ程度、該半導体チップ３上方の樹脂７
の肉厚が０．２５ｍｍ程度である。よって、図５の高さ
H２に相当するパッケージ全体の肉厚は合計０．６０ｍ
ｍ程度である。また図１において、本発明の半導体チッ
プ３上方の樹脂７の肉厚は０．０８ｍｍ程度である。よ
って、基板１下面からパッケージ最上面までのパッケー
ジ全体の肉厚は０．４８ｍｍ程度になる。これらより基
板１の板厚を変えないと仮定すると、本発明は従来例と
比較して、０．１２ｍｍ程度減少するといえる。結果、
絶縁物８の厚みを加算したとしても、半導体チップ３上
方の樹脂７の肉厚は４０％削減し、パッケージ全体の肉
厚においては２０％削減する。At present, the thickness of a general semiconductor package is such that the board 1 has a thickness of about 0.20 mm, the semiconductor chip 3 has a thickness of about 0.15 mm, and the resin 7 above the semiconductor chip 3 has a thickness of about 0.15 mm.
Has a thickness of about 0.25 mm. Therefore, the height of FIG.
The total thickness of the entire package equivalent to H2 is 0.60 m
m. In FIG. 1, the thickness of the resin 7 above the semiconductor chip 3 of the present invention is about 0.08 mm. Therefore, the thickness of the entire package from the lower surface of the substrate 1 to the uppermost surface of the package is about 0.48 mm. Assuming that the thickness of the substrate 1 is not changed, it can be said that the present invention is reduced by about 0.12 mm as compared with the conventional example. result,
Even if the thickness of the insulator 8 is added, the thickness of the resin 7 above the semiconductor chip 3 is reduced by 40%, and the thickness of the entire package is reduced by 20%.
【００１７】以上より、本発明によれば樹脂外形上部に
絶縁物８を形成することでボンディングワイヤ６が樹脂
外部へ露出することを防止したので、図３の高さＨ１の
モールド金型１２の使用を可能とし、結果従来例よりも
薄型の半導体パッケージを得ることができる。また、ボ
ンディングワイヤ６のループは台形型をしているため、
該ボンディングワイヤ６と半導体チップ３とは十分な距
離を保ち、両者が短絡不良を生じるという欠点を有しな
い。加えて、モールド金型１２により、ワイヤ最上部６
（ａ）を押さえる構成にしたので、別途工程を用意する
ことなくボンディングワイヤ６のループの高さを抑える
ことができる。As described above, according to the present invention, since the bonding wire 6 is prevented from being exposed to the outside of the resin by forming the insulator 8 on the upper portion of the resin outer shape, the molding die 12 having the height H1 shown in FIG. The semiconductor package can be used, and as a result, a semiconductor package thinner than the conventional example can be obtained. Also, since the loop of the bonding wire 6 has a trapezoidal shape,
The bonding wire 6 and the semiconductor chip 3 are kept at a sufficient distance, and do not have a drawback that a short circuit occurs between them. In addition, the uppermost wire 6
(A) is suppressed, so that the height of the loop of the bonding wire 6 can be suppressed without preparing a separate process.
【００１８】[0018]
【発明の効果】以上に示した如く、本発明において図３
のＨ１が従来のパッケージの肉厚よりも薄いモールド金
型１２を使用し、パッケージの肉厚を薄くすることがで
きる。嵌合する際にモールド金型１２の金型上部の内側
面とボンディングワイヤ６の一部とが密着するように形
成し、その後図１にみられるように樹脂７の外形上部に
絶縁物８を形成することで、樹脂７内のボンディングワ
イヤ６が樹脂外へ露出することを防ぐ。また、ボンディ
ングワイヤ６のループが台形型をしているため、該ボン
ディングワイヤ６と半導体チップ３とは十分な距離を保
ち、両者が接触する可能性を低くする効果も有する。As described above, according to the present invention, FIG.
The thickness of the package can be reduced by using the mold 12 whose H1 is smaller than the thickness of the conventional package. At the time of fitting, the inner surface of the upper part of the mold 12 is formed so as to be in close contact with a part of the bonding wire 6, and then, as shown in FIG. The formation prevents the bonding wires 6 in the resin 7 from being exposed to the outside of the resin. Further, since the loop of the bonding wire 6 has a trapezoidal shape, the bonding wire 6 and the semiconductor chip 3 are kept at a sufficient distance, and have an effect of reducing the possibility of contact between them.
【図１】本発明の一実施の形態を説明するための断面図
である。FIG. 1 is a cross-sectional view for explaining an embodiment of the present invention.
【図２】本発明の製造方法におけるモールド金型をする
前の段階の断面図である。FIG. 2 is a cross-sectional view of a stage before forming a mold in the manufacturing method of the present invention.
【図３】本発明の製造方法におけるモールド金型をした
状態の断面図である。FIG. 3 is a cross-sectional view showing a state in which a mold is used in the manufacturing method of the present invention.
【図４】本発明の製造方法におけるモールド金型を外し
た状態の断面図及び平面図である。FIG. 4 is a cross-sectional view and a plan view of the manufacturing method of the present invention in a state where a mold is removed.
【図５】従来例の半導体装置の断面図である。FIG. 5 is a sectional view of a conventional semiconductor device.
フロントページの続き Ｆターム(参考） 4M109 AA01 BA03 CA21 DB15 ED01 ED03 5F044 AA02 HH02 JJ03 5F061 AA01 BA03 CA21 CB03 CB13 DA06 Continued on the front page F term (reference) 4M109 AA01 BA03 CA21 DB15 ED01 ED03 5F044 AA02 HH02 JJ03 5F061 AA01 BA03 CA21 CB03 CB13 DA06
Claims (3)
導体チップと、 前記半導体チップを固着するアイランドと、 前記アイランドとは離間した位置に設けられた内部リー
ドと、 前記ボンディングパッドと前記内部リードとを電気的に
接続するボンディングワイヤと、 前記半導体チップと前記ボンディングワイヤとを含めて
全体を封止する樹脂とを有する半導体装置において、 前記ボンディングワイヤが近接する前記樹脂の表面に、
絶縁物の被膜を形成したことを特徴とする半導体装置。A semiconductor chip having a bonding pad formed on a surface thereof, an island for fixing the semiconductor chip, an internal lead provided at a position separated from the island, the bonding pad and the internal lead. In a semiconductor device having a bonding wire electrically connected, and a resin for sealing the whole including the semiconductor chip and the bonding wire, a surface of the resin in which the bonding wire is close to the surface of the resin,
A semiconductor device having an insulating film formed thereon.
ボンディングワイヤの一部が露出したことを特徴とする
請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a part of said bonding wire is exposed between said resin and said insulating film.
導体チップと、 前記半導体チップを固着するアイランドと、 前記アイランドとは離間した位置に設けられた内部リー
ドと、 前記ボンディングパッドと前記内部リードとを電気的に
接続するボンディングワイヤと、 前記半導体チップと前記ボンディングワイヤとを含めて
全体を樹脂でトランスファーモールドした半導体装置の
製造方法であって、 前記トランスファーモールドの金型面で前記ボンディン
グワイヤの最上部を押圧して、樹脂を注入し、その後前
記樹脂の表面に露出する前記ボンディングワイヤの最上
部を被覆するように、前記樹脂の表面に絶縁物の被膜を
形成することを特徴とする半導体装置の製造方法。3. A semiconductor chip having a bonding pad formed on a surface thereof, an island for fixing the semiconductor chip, an internal lead provided at a position separated from the island, and the bonding pad and the internal lead. What is claimed is: 1. A method of manufacturing a semiconductor device in which the whole including a bonding wire electrically connected to the semiconductor chip and the bonding wire is transfer-molded with a resin. Press, to inject the resin, and then form an insulating film on the surface of the resin so as to cover the uppermost portion of the bonding wire exposed on the surface of the resin. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001099198A JP2002299357A (en) | 2001-03-30 | 2001-03-30 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001099198A JP2002299357A (en) | 2001-03-30 | 2001-03-30 | Semiconductor device and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002299357A true JP2002299357A (en) | 2002-10-11 |
Family
ID=18952773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001099198A Pending JP2002299357A (en) | 2001-03-30 | 2001-03-30 | Semiconductor device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002299357A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6793091B2 (en) * | 2001-03-30 | 2004-09-21 | Toyoda Gosei Co., Ltd | Tank cap |
| US8169089B2 (en) | 2008-06-24 | 2012-05-01 | Elpida Memory, Inc. | Semiconductor device including semiconductor chip and sealing material |
| CN110692135A (en) * | 2019-06-14 | 2020-01-14 | 深圳市汇顶科技股份有限公司 | Chip packaging structure and electronic equipment |
-
2001
- 2001-03-30 JP JP2001099198A patent/JP2002299357A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6793091B2 (en) * | 2001-03-30 | 2004-09-21 | Toyoda Gosei Co., Ltd | Tank cap |
| US8169089B2 (en) | 2008-06-24 | 2012-05-01 | Elpida Memory, Inc. | Semiconductor device including semiconductor chip and sealing material |
| CN110692135A (en) * | 2019-06-14 | 2020-01-14 | 深圳市汇顶科技股份有限公司 | Chip packaging structure and electronic equipment |
| CN113035795A (en) * | 2019-06-14 | 2021-06-25 | 深圳市汇顶科技股份有限公司 | Chip packaging structure and electronic equipment |
| CN113035795B (en) * | 2019-06-14 | 2022-11-08 | 深圳市汇顶科技股份有限公司 | Chip packaging structure and electronic equipment |
| US11545517B2 (en) | 2019-06-14 | 2023-01-03 | Shenzhen GOODIX Technology Co., Ltd. | Chip package structure, electronic device and method for preparing a chip package structure |
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