JPS6328039A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPS6328039A
JPS6328039A JP17241086A JP17241086A JPS6328039A JP S6328039 A JPS6328039 A JP S6328039A JP 17241086 A JP17241086 A JP 17241086A JP 17241086 A JP17241086 A JP 17241086A JP S6328039 A JPS6328039 A JP S6328039A
Authority
JP
Japan
Prior art keywords
film
insulating film
ions
coated
step coverage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17241086A
Other languages
Japanese (ja)
Inventor
Kenya Sakurai
建弥 桜井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP17241086A priority Critical patent/JPS6328039A/en
Publication of JPS6328039A publication Critical patent/JPS6328039A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form an arbitrary oblique surface on the edge of an insulating film thereby to improve the step coverage of a metal electrode film thereon by implanting ions to the surface layer of an insulating film before forming a pattern. CONSTITUTION:After a whole silicon substrate 1 is coated with an insulating film 2, such as an oxide film, a PSG film, ions 3 are implanted to the whole surface. Then, after the film 2 is coated with resist, a pattern of a resist film 4 is formed by photoprocessing. Then, when the film 2 is etched, since the surface layer of the insulating film is damaged by ion implanting, an oblique surface 5 is formed on the edge of the remaining film 2. Thus, the step coverage of the electrode metal film coated on the insulating film can be improved.

Description

【発明の詳細な説明】[Detailed description of the invention] 【発明の属する技術分野】[Technical field to which the invention pertains]

本発明は、半導体基板上に絶縁膜を介して金属電極膜が
被着される半導体素子の製造方法に関する。
The present invention relates to a method for manufacturing a semiconductor element in which a metal electrode film is deposited on a semiconductor substrate via an insulating film.

【従来技術とその問題点】[Prior art and its problems]

半導体素子の金属電極膜を絶縁膜の上に形成する際、絶
縁膜の縁部に存在する段差部において、いわゆるステッ
プカバレージの問題が起こり、電極膜の断線が生ずるお
それがある。このようなステップカバレージの改善する
方法として、絶縁膜としてりんガラス (PSG)を使
用し、リフローによって段差部に傾斜をつける技術があ
るが、この技術では傾斜角を任意に制御することが陽め
て困難である。傾斜角を小さすぎると絶縁膜の微細パタ
ーンが形成できないという問題が生ずる。従って、ステ
ップカバレージの改善を電極膜付は方法で対策しなけれ
ばならず、を極膜付は方法を制限することになる。
When a metal electrode film of a semiconductor element is formed on an insulating film, a so-called step coverage problem occurs in a step portion existing at the edge of the insulating film, and there is a risk that the electrode film may be disconnected. One way to improve step coverage is to use phosphor glass (PSG) as an insulating film and use reflow to create a slope at the step, but this technology does not require arbitrary control of the slope angle. It is difficult to If the inclination angle is too small, a problem arises in that a fine pattern of the insulating film cannot be formed. Therefore, steps must be taken to improve the step coverage using a method with an electrode film, and the method with an electrode film is limited.

【発明の目的】[Purpose of the invention]

本発明は、絶縁膜の縁部に任意の傾斜面を形成すること
ができ、それによってその上の金属電極膜のステップカ
バレージが良好になる半導体素子の製造方法を提供する
ことを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device, in which an arbitrary inclined surface can be formed at the edge of an insulating film, thereby improving step coverage of a metal electrode film thereon.

【発明の要点】[Key points of the invention]

本発明は、半導体基板へのイオン注入時のイオン種、エ
ネルギー、ドーズ量などの注入条件により、基板上に存
在する絶縁膜のエツチング速度が変化することに着目し
たもので、エツチングによるパターニング前に絶縁膜の
表面層にイオンを注入することにより表面層にt員傷を
与え、下要とのエツチング速度を変えることにより、絶
縁膜の所定の頭載を被覆してバターニングのためのエツ
チングを行う際に絶縁膜の縁部に所定の角度の傾斜面が
形成でき、上記の目的が達成される。
The present invention focuses on the fact that the etching rate of an insulating film on a semiconductor substrate changes depending on the implantation conditions such as ion species, energy, and dose during ion implantation into a semiconductor substrate. By implanting ions into the surface layer of the insulating film, a number of scratches are caused to the surface layer, and by changing the etching rate with respect to the underlying layer, the predetermined head of the insulating film is covered and etched for patterning. When performing this, an inclined surface having a predetermined angle can be formed on the edge of the insulating film, and the above object can be achieved.

【発明の実施例】[Embodiments of the invention]

第1図は本発明の一実施例の絶縁膜バターニング工程を
示し、シリコン基板1上の酸化膜、  PSG膜などの
絶縁膜2を全面に被着したのち、第1図fa+に示すよ
うに全面にイオン3を注入する0次いで絶縁膜2の表面
にレジストを塗布後、フォトプロセスにより第1図(b
lに示すようにレジスト膜4のパターンを形成する。こ
のあと絶縁膜2のエツチングを行うと、絶縁膜の表面層
はイオン注入により損傷を受けているので、残った絶縁
膜2の縁部には図示のように傾斜面5が形成される。こ
れにより、この絶縁膜の上に被着する電極金属膜のステ
ップカバレージは改善される。 第2図は絶縁膜2として酸化膜を用いたときに生ずる傾
斜面5のテーパ角度、θとイオン種およびドーズ量との
関係を示し、線21はひ素イオン、線22はほう素イオ
ンあるいはアルゴンイオンを注入したときであり、打ち
込みエネルギーは何れも80keVである。従って、イ
オン種、注入エネルギーあるいはドーズ量を選定するこ
とにより、任意のテーバ角度の傾斜面5を絶縁膜に形成
することができる。 【発明の効果] 本発明によれば、絶縁膜の表面層にイオン注入により損
傷を与えることによって絶縁膜のバターニング時に縁部
に傾斜面を形成することができ、金it極膜のステップ
カバレージを良好にすることができる。しかも傾斜面の
テーバ角度の調整が容易にできるため、電極形成方法に
幅を持たせることができ、半導体素子のパターンの微細
化、信転性の向上に与える効果は極めて大きい。
FIG. 1 shows an insulating film buttering process according to an embodiment of the present invention. After an insulating film 2 such as an oxide film or a PSG film is deposited on the entire surface of a silicon substrate 1, as shown in FIG. Ions 3 are implanted into the entire surface of the insulating film 2. After coating the surface of the insulating film 2 with a resist, a photo process is performed to form a pattern as shown in Fig. 1 (b).
A pattern of the resist film 4 is formed as shown in FIG. When the insulating film 2 is etched after this, since the surface layer of the insulating film has been damaged by the ion implantation, an inclined surface 5 is formed at the edge of the remaining insulating film 2 as shown in the figure. This improves the step coverage of the electrode metal film deposited on this insulating film. FIG. 2 shows the relationship between the taper angle θ of the inclined surface 5 that occurs when an oxide film is used as the insulating film 2, and the ion species and dose. Line 21 indicates arsenic ions, line 22 indicates boron ions or argon ions. This is when ions were implanted, and the implantation energy was 80 keV in both cases. Therefore, by selecting the ion species, implantation energy, or dose, it is possible to form the inclined surface 5 with an arbitrary Taber angle on the insulating film. Effects of the Invention According to the present invention, by damaging the surface layer of the insulating film by ion implantation, an inclined surface can be formed at the edge during patterning of the insulating film, and step coverage of the gold-IT electrode film can be improved. can be made good. Moreover, since the taper angle of the inclined surface can be easily adjusted, the electrode formation method can be varied, and the effect on miniaturizing the pattern of the semiconductor element and improving the reliability is extremely large.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の絶縁膜バターニング工程を
順次示す断面図、第2図は絶縁II!1IIIJ!斜面
と注入イオン種およびドーズ量との関係線図である。 1:シリコン基板、2:絶縁膜、3:注入イオン、4=
レジスト膜、5:傾斜面。 第1図
FIG. 1 is a sectional view sequentially showing the insulating film patterning process according to an embodiment of the present invention, and FIG. 2 is an insulating film patterning process according to an embodiment of the present invention. 1IIIJ! FIG. 3 is a relationship diagram between a slope, implanted ion species, and dose amount. 1: silicon substrate, 2: insulating film, 3: implanted ions, 4=
Resist film, 5: inclined surface. Figure 1

Claims (1)

【特許請求の範囲】[Claims] 1)半導体基板上に被着された絶縁膜を選択的にエッチ
ングして形成した絶縁膜パターンの上に金属電極膜が被
着されるものの製造方法において、パターン形成前の絶
縁膜の表面層にイオンを注入することを特徴とする半導
体素子の製造方法。
1) In a manufacturing method in which a metal electrode film is deposited on an insulating film pattern formed by selectively etching an insulating film deposited on a semiconductor substrate, a metal electrode film is deposited on the surface layer of the insulating film before pattern formation. A method for manufacturing a semiconductor device, characterized by implanting ions.
JP17241086A 1986-07-22 1986-07-22 Manufacture of semiconductor element Pending JPS6328039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17241086A JPS6328039A (en) 1986-07-22 1986-07-22 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17241086A JPS6328039A (en) 1986-07-22 1986-07-22 Manufacture of semiconductor element

Publications (1)

Publication Number Publication Date
JPS6328039A true JPS6328039A (en) 1988-02-05

Family

ID=15941439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17241086A Pending JPS6328039A (en) 1986-07-22 1986-07-22 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPS6328039A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01312098A (en) * 1988-06-10 1989-12-15 Sumitomo Metal Ind Ltd Molten salt electroplating apparatus having superior durability

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5787134A (en) * 1980-11-20 1982-05-31 Seiko Epson Corp Local etching method
JPS6055631A (en) * 1983-09-07 1985-03-30 Oki Electric Ind Co Ltd Preparation of semiconductor device
JPS60240131A (en) * 1984-05-14 1985-11-29 Toshiba Corp Manufacture of semiconductor device
JPS6140035A (en) * 1984-07-31 1986-02-26 Ricoh Co Ltd Manufacture of semiconductor device
JPS61114536A (en) * 1984-11-09 1986-06-02 Nec Corp Manufacture of semiconductor device
JPS61116842A (en) * 1984-11-12 1986-06-04 Mitsubishi Electric Corp Manufacture of semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5787134A (en) * 1980-11-20 1982-05-31 Seiko Epson Corp Local etching method
JPS6055631A (en) * 1983-09-07 1985-03-30 Oki Electric Ind Co Ltd Preparation of semiconductor device
JPS60240131A (en) * 1984-05-14 1985-11-29 Toshiba Corp Manufacture of semiconductor device
JPS6140035A (en) * 1984-07-31 1986-02-26 Ricoh Co Ltd Manufacture of semiconductor device
JPS61114536A (en) * 1984-11-09 1986-06-02 Nec Corp Manufacture of semiconductor device
JPS61116842A (en) * 1984-11-12 1986-06-04 Mitsubishi Electric Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01312098A (en) * 1988-06-10 1989-12-15 Sumitomo Metal Ind Ltd Molten salt electroplating apparatus having superior durability

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