JPS5933827A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5933827A JPS5933827A JP14372082A JP14372082A JPS5933827A JP S5933827 A JPS5933827 A JP S5933827A JP 14372082 A JP14372082 A JP 14372082A JP 14372082 A JP14372082 A JP 14372082A JP S5933827 A JPS5933827 A JP S5933827A
- Authority
- JP
- Japan
- Prior art keywords
- light
- film
- resist film
- exposure
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置の製造方法に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for manufacturing a semiconductor device.
近年、半導体装置の微細化に伴って、解像度の高いポジ
型レゾスト膜を使用する半導体装置の製造方法が開発さ
れている。このような半導体装置の製造方法として、例
えば゛、第１図に示すようなアルミゲートプロセスがあ
る。図中１は、ソース、ドレイン等の不純物領域を形成
した半導体基板である。半導体基板１上には、Ｃ０Ｖ、
Ｄ （Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔ
ｉｏｎ ）法により厚さ約５２００１のフィールド酸化
膜２となる酸化膜が形成されている。この酸化膜には、
リンケイ酸化ガラス膜（以下、ＰＳＧ膜と記す。）を形
成してリンケ゛ツタ−を行い、デンシファイ処理を施し
た後、２５〜３５°のテーパ角（θ）でダート穴の開口
処理が施されている。ダート穴の露出表面には、熱酸化
により厚さ６００Ｘ程度のダート酸化膜３が形成されて
いる。ダート酸化膜３及びフィールド酸化膜２上には、
ダート電極を形成するためのアルミニウム等からなる金
属被膜４が形成されている。金属被膜４上には、ポジ型
レジスト膜５が形成されている。而して、ポジ型レジス
ト膜５の上方に設けたマスク６を遮蔽板にして露光を行
い、金属被膜４のノｊターニングが行われている。In recent years, with the miniaturization of semiconductor devices, methods for manufacturing semiconductor devices using positive resist films with high resolution have been developed. An example of a method for manufacturing such a semiconductor device is an aluminum gate process as shown in FIG. 1 in the figure is a semiconductor substrate on which impurity regions such as a source and a drain are formed. On the semiconductor substrate 1, C0V,
D (Chemical Vapor Deposit
An oxide film which will become the field oxide film 2 and has a thickness of approximately 52,001 mm is formed by the ion method. This oxide film has
After forming a phosphosilicate glass film (hereinafter referred to as PSG film) and performing linkage and densification processing, dart hole opening processing is performed with a taper angle (θ) of 25 to 35°. . A dart oxide film 3 having a thickness of approximately 600× is formed on the exposed surface of the dart hole by thermal oxidation. On the dirt oxide film 3 and field oxide film 2,
A metal coating 4 made of aluminum or the like is formed to form a dirt electrode. A positive resist film 5 is formed on the metal film 4. Then, exposure is performed using a mask 6 provided above the positive resist film 5 as a shielding plate, and turning of the metal coating 4 is performed.
このような従来の半導体装置の製造方法では、フィール
ド酸化膜２の段部２ａ上の金属被膜４の部分には、これ
に対応した傾斜面４ａが形成されているため、ポジ型レ
ジスト膜５を透過した光７は、この傾斜面４ａで反射す
る。その結果、第２図に示す如く、ケ゛−） ｉｉ、極
のパターンに残存させるはずのポジ型レジストＢＤ５’
（Ｄ傾斜面４ａと対向する領域が、反射光によって溶解
する所謂逆ひけ現象が起きる。このため逆ひけ現象によ
って除去された月？ジ型レジスト膜５′の直下の金属被
膜４は当然除去され、形成されたダート電極の配線幅は
局部的に狭くなシ、断線を起こす原因となって信頼性、
歩留の低下を招く問題があった。In such a conventional semiconductor device manufacturing method, since a corresponding inclined surface 4a is formed on the metal coating 4 on the stepped portion 2a of the field oxide film 2, the positive resist film 5 is The transmitted light 7 is reflected by this inclined surface 4a. As a result, as shown in FIG.
(The so-called reverse sink phenomenon occurs in which the area facing the D inclined surface 4a is dissolved by the reflected light. Therefore, the metal coating 4 directly under the moon-shaped resist film 5' removed by the reverse sink phenomenon is naturally removed. However, the wiring width of the formed dart electrode is locally narrow, which may cause wire breakage and reduce reliability.
There was a problem that led to a decrease in yield.
本発明は、逆ひけ現象の発生を防止した半導体装置の製
造方法を提供することをその目的とするものである。An object of the present invention is to provide a method for manufacturing a semiconductor device that prevents the occurrence of the reverse sink phenomenon.
本発明は、金属被膜が載置された絶縁膜の段差面で反射
する光量を減少させることによシ、逆ひけ現象の発生を
防止した半導体装置の製造方法である。The present invention is a method for manufacturing a semiconductor device that prevents the occurrence of the reverse sink phenomenon by reducing the amount of light reflected on the step surface of an insulating film on which a metal coating is placed.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
先ず、第３８図峻）に示す如く、ソース、ドレインの不
純物領域を形成した半導体基板２ｏの表面に、フィール
ド酸化膜２ノを形成するだめの酸化膜としてｃ、ｖ、Ｄ
、−５ｔｏ２膜を厚さ５２００Ｘ形成する。次イテ、Ｃ
，Ｖ、Ｄ、−８ｉ０２膜上にＰＳＧ膜を厚さ約７００Ｘ
形成してリンダ−ターを行い、デンシファイ処理した後
写真蝕刻法によりダート穴２２を開口する。ここで、ダ
ート穴２２の内周面２２ａの傾斜角（θ）は、４０〜５
０°の範囲内に設定する。傾斜角（θ）が４０°に満た
ない場合は、後述する露光処理の際の反射光量が多くな
シ、後述する逆ひけ現象を防止できない。傾斜角（θ）
が５０°を超えると、フィールド酸化膜２１上からダー
ト領域にかけて形成されるダート電極等の配線が断切れ
し易くなる。次いで、熱酸化によシダート領域にダート
酸化膜２３を厚さ約５−
７００Ｘ形成する。次いで、所定の不純物をダート領域
にイオン注入し、焼成を施してしきい値電圧の制御を行
う。次いで、ソース、ドレインの取出電極用のコンタク
ト開口（図示せず）を形成した後、同図（Ｂ）に示す如
く、デート領域、フィールド酸化膜２１の表面に、厚さ
約０．６μのアルミニウム等からなる金属被膜２４を形
成する。次いで、金属被膜２４上にプラズマ処理によっ
て光吸収率の高いチ、化シリコン被膜２５を厚さ約３０
０Ｘ形成する。次に、チッ化シリコン被膜２５上に、色
素を含有した光吸収率の高いポジ型レジスト膜２６を形
成する。然る後、ポジ型レジスト膜２６の上方に設けた
所定パターンのマスク２７を遮蔽板にして露光を行い、
号？ジ型レジスト膜２６のノリーニングを施す。ここで
、露光量は、フィールド酸化膜２１の傾斜面２２ａで生
じる光反射が逆ひげを生じないように弱められる程度の
光量に設定しておく。このＵ光量は、露光処理の際の解
像度、焦点深度から決定される標準露光量の約７０チ６
−
に設定するのが望ましい。而して、ノ臂ターニングされ
たポジ型レジスト膜２６をマスクにしてその直下のチッ
化シリコン膜２５及び金属被膜２４にエツチング処理を
施し、所望ノｅターンのダート電極及び取出配線を形成
する。次いで、チッ化シリコン膜２５を除去してからｉ
４ッシベチッ化シリコン嗅２５は残存させておいてもよ
い。First, as shown in FIG. 38), on the surface of the semiconductor substrate 2o on which the source and drain impurity regions are formed, c, v, and D are deposited as oxide films for forming the field oxide film 2.
, -5to2 film is formed to a thickness of 5200X. Next item, C
, V, D, - PSG film on the -8i02 film to a thickness of about 700X
After forming, lintaring, and densifying, dart holes 22 are opened by photolithography. Here, the inclination angle (θ) of the inner circumferential surface 22a of the dart hole 22 is 40 to 5
Set within the range of 0°. If the inclination angle (θ) is less than 40°, the amount of reflected light during the exposure process described later is large, and the reverse sink phenomenon described later cannot be prevented. Tilt angle (θ)
If the angle exceeds 50°, wiring such as a dirt electrode formed from above the field oxide film 21 to the dirt region is likely to be cut off. Next, a dirt oxide film 23 with a thickness of about 5-700× is formed in the dirt region by thermal oxidation. Next, a predetermined impurity is ion-implanted into the dirt region and baked to control the threshold voltage. Next, after forming contact openings (not shown) for the source and drain extraction electrodes, as shown in FIG. A metal coating 24 consisting of the following is formed. Next, a silicon oxide film 25 having a high light absorption rate is formed on the metal film 24 by plasma treatment to a thickness of about 30 mm.
Form 0X. Next, a positive resist film 26 containing a dye and having a high light absorption rate is formed on the silicon nitride film 25. After that, exposure is performed using a mask 27 with a predetermined pattern provided above the positive resist film 26 as a shielding plate.
issue? The di-type resist film 26 is subjected to no-leaning. Here, the exposure amount is set to such a level that the light reflection occurring on the inclined surface 22a of the field oxide film 21 is weakened so as not to cause backlashes. This amount of U light is approximately 70 inches, which is the standard exposure amount determined from the resolution and depth of focus during exposure processing.
− It is preferable to set it to . Then, using the turned positive resist film 26 as a mask, the silicon nitride film 25 and the metal film 24 directly under it are etched to form a desired E-turn dirt electrode and lead wiring. Next, after removing the silicon nitride film 25,
The silicon chloride 25 may be left to remain.
このようにこの半導体装置の製造方法によれば、フィー
ルド酸化膜２１の段差面であるダート穴２２の内周面２
２ａの傾斜角（θ）を４０〜５０°に設定したので、ポ
ジ型レジスト膜２６の露光処理の際に、段差面の受光面
積が小さくなシ、ダート電極配線等のパターンに対応す
るレジスト膜部分への光反射が実質上阻止される。As described above, according to this semiconductor device manufacturing method, the inner circumferential surface 2 of the dirt hole 22, which is the step surface of the field oxide film 21,
Since the inclination angle (θ) of 2a is set to 40 to 50°, when exposing the positive resist film 26, a resist film corresponding to a pattern such as a dirt electrode wiring or the like with a small light-receiving area on the stepped surface can be used. Light reflection onto the part is substantially prevented.
その結果、ポジ型レジスト膜２６を逆ひけ現象が起きる
のを防止してノ（ターニングすることができ、ダート電
極配線等の形状精度を高めて素子の信頼性を高めること
ができる。また、逆ひけ現象の防止は、金属被膜２４上
に形成した高光吸収率のチッ化シリコン被膜２６による
光吸収作用、色素を含有したポジ型レジスト膜２４の光
吸収作用及び露光処理の際の露光量を標準露光量の約７
０％に設定したことによって、更に確実に達成すること
ができる。As a result, it is possible to turn the positive resist film 26 while preventing the reverse sink phenomenon, and it is possible to improve the accuracy of the shape of the dirt electrode wiring and the like, thereby increasing the reliability of the device. The sink phenomenon can be prevented by adjusting the light absorption effect of the silicon nitride film 26 with a high light absorption rate formed on the metal film 24, the light absorption action of the positive resist film 24 containing dye, and the standard exposure amount during exposure processing. Approximately 7 of the exposure amount
By setting it to 0%, this can be achieved even more reliably.
なお、露光量を標準露光量の約７０％と小さくしたのは
、少ない露光量では、露光部と未露光部の現像液に対す
る溶解度比が小さくなシ、当然露光されるべき部分の溶
解速度も小さくなる。このため、段差面で少々の光反射
が起きても反射光で露光された部分を、現像後に溶解し
ないで残存させることができるからである。The reason why the exposure amount was reduced to about 70% of the standard exposure amount was because at a small exposure amount, the solubility ratio of the exposed area and the unexposed area in the developer is small, and of course the dissolution rate of the exposed area is also low. becomes smaller. Therefore, even if a small amount of light reflection occurs on the stepped surface, the portion exposed to the reflected light can remain without being dissolved after development.
また、ポジ型レジスト膜２６中に色素を入れるのは、式
Ｉ（ｘｌ＝Ｉ。、１１ ｄｘで表わされる光強度Ｉ（ｘ
）を、色素を入れることによって１゜（入射光強度）を
大きくして増大させることができるので、段差面に到達
する光量を小さくして実質上段差面での光反射を阻止で
きるからである。In addition, the dye is introduced into the positive resist film 26 by the light intensity I(x
) can be increased by increasing 1° (incident light intensity) by adding a dye, so it is possible to reduce the amount of light reaching the stepped surface and virtually prevent light reflection from the stepped surface. .
また、逆ひけ現象の防止は、段差面の傾斜角（のを大き
くする技術手段、高光吸収率の被膜を使用する技術手段
、色素を混入したレジスト膜を使用する技術手段、或は
、露光量を小さくする技術手段のいずれかを単独で採用
しても達成できることは勿論である。In addition, the reverse sink phenomenon can be prevented by increasing the inclination angle of the stepped surface, by using a film with high light absorption rate, by using a resist film containing a dye, or by increasing the amount of light exposure. Of course, this can also be achieved by adopting any one of the technical means for reducing the size.
以上説明した如く、本発明に係る半導体装置の製造方法
によれば、逆ひけ現象の発生を防止して信頼性の高い半
導体装置を容易に得ることができる等顕著な効果を有す
るものである。As described above, the method for manufacturing a semiconductor device according to the present invention has remarkable effects such as preventing the occurrence of the reverse sink phenomenon and easily producing a highly reliable semiconductor device.
第１図は、従来の半導体装置の製造方法にてｙ−ト電ｍ
のパターニングを行っている状態を示す断面図、第２図
は、従来の半導体装置の製造方法によって逆ひけ現象が
起きている状態を示す平面図、第３図（Ａ）及び同図（
Ｂｌは、本発明の実施例を工程順に示す説明図である。
２０・・・半導体基板、２１・・・フィールド酸化膜、
２２・・・ダート穴、２２ａ・・・内周面、２３・・・
ｒ −一９＝
ト酸化膜、２４・・・金属被膜、２５・・・チッ化シリ
コン膜、２６・・・ポジ型レジスト膜、２７・・・マス
ク。
出願人代理人 弁理士 鈴 江 武 彦＝１０−
才１図
６
／
才２図
牙３図
（Ａ）
ＣＢ）
７Figure 1 shows the y-t electric current m
FIG. 2 is a cross-sectional view showing a state in which patterning is being performed, and FIG.
Bl is an explanatory diagram showing an example of the present invention in the order of steps. 20... Semiconductor substrate, 21... Field oxide film,
22...Dart hole, 22a...Inner peripheral surface, 23...
r-19= oxide film, 24...metal coating, 25...silicon nitride film, 26...positive resist film, 27...mask. Applicant's agent Patent attorney Takehiko Suzue = 10- 1 figure 6 / 2 figure 3 figure (A) CB) 7
Claims (5)
工程と、前記絶縁膜上に金属被膜を形成する工程と、該
金属被膜上にレジスト膜を形成し、露光処理によって該
レジスト膜ニパターニングを施す工程と、パターニング
されたレジスト膜をマスクにして前記金属被膜にパター
ニングを施す工程とを具備する半導体装置の製造方法に
おいて、露光処理の際の絶縁膜の段差面から反射する光
量を制御する技術手段を採用したことを特徴とする半導
体装置の製造方法。(1) A step of forming an insulating film in a predetermined pattern on a semiconductor substrate, a step of forming a metal film on the insulating film, forming a resist film on the metal film, and double-patterning the resist film by exposure treatment. and a step of patterning the metal film using a patterned resist film as a mask, in which the amount of light reflected from the step surface of the insulating film during exposure processing is controlled. A method for manufacturing a semiconductor device, characterized in that it employs technical means.
面の傾斜角を４０〜５０°に設定することである特許請
求の範囲第１項記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the means for controlling the elements reflected from the step surface is to set the inclination angle of the step surface to 40 to 50 degrees.
被膜上に光吸収性の被膜を形成することである特許請求
の範囲第１項記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the means for controlling the amount of light reflected from the step surface is to form a light-absorbing film on the metal film.
光吸収率の高いレジスト膜を使用することである特許請
求の範囲第１項記載の半導体装置の製造方法。(4) The means for controlling the light meter reflecting from the stepped surface is
2. The method of manufacturing a semiconductor device according to claim 1, wherein a resist film having a high light absorption rate is used.
スト膜を・母ターニングする際の露光量を減少させるこ
とである特許請求の範囲第１項記載の半導体装置の製造
方法。(5) The method of manufacturing a semiconductor device according to claim 1, wherein the means for controlling the amount of light reflected from the step surface is to reduce the amount of exposure when turning the resist film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14372082A JPS5933827A (en) | 1982-08-19 | 1982-08-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14372082A JPS5933827A (en) | 1982-08-19 | 1982-08-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5933827A true JPS5933827A (en) | 1984-02-23 |
Family
ID=15345418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14372082A Pending JPS5933827A (en) | 1982-08-19 | 1982-08-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5933827A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61274741A (en) * | 1985-05-29 | 1986-12-04 | Mitsubishi Heavy Ind Ltd | Catalytic reactor |
| JPS6219240A (en) * | 1985-07-17 | 1987-01-28 | Mitsubishi Heavy Ind Ltd | Catalytic reactor |
| KR100451041B1 (en) * | 1997-06-27 | 2004-12-04 | 주식회사 하이닉스반도체 | Method for forming metal interconnection of semiconductor device to solve problems arising from step between cell area and peripheral circuit area of semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5259579A (en) * | 1975-11-11 | 1977-05-17 | Toshiba Corp | Photo etching method of semiconductor substrate |
| JPS54111285A (en) * | 1978-02-20 | 1979-08-31 | Nec Corp | Production of semiconductor device |
| JPS5680130A (en) * | 1979-12-05 | 1981-07-01 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5694738A (en) * | 1979-12-28 | 1981-07-31 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| JPS5877228A (en) * | 1981-11-02 | 1983-05-10 | Hitachi Ltd | Photoetching method |
-
1982
- 1982-08-19 JP JP14372082A patent/JPS5933827A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5259579A (en) * | 1975-11-11 | 1977-05-17 | Toshiba Corp | Photo etching method of semiconductor substrate |
| JPS54111285A (en) * | 1978-02-20 | 1979-08-31 | Nec Corp | Production of semiconductor device |
| JPS5680130A (en) * | 1979-12-05 | 1981-07-01 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5694738A (en) * | 1979-12-28 | 1981-07-31 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| JPS5877228A (en) * | 1981-11-02 | 1983-05-10 | Hitachi Ltd | Photoetching method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61274741A (en) * | 1985-05-29 | 1986-12-04 | Mitsubishi Heavy Ind Ltd | Catalytic reactor |
| JPS6219240A (en) * | 1985-07-17 | 1987-01-28 | Mitsubishi Heavy Ind Ltd | Catalytic reactor |
| KR100451041B1 (en) * | 1997-06-27 | 2004-12-04 | 주식회사 하이닉스반도체 | Method for forming metal interconnection of semiconductor device to solve problems arising from step between cell area and peripheral circuit area of semiconductor device |
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