JPH05102059A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing a semiconductor device having an accurate resistance. CONSTITUTION:After a SiO2 film 4, an Si3N4 film 7 arid a CVD SiO2 film 17 are sequentially formed on a p-type Si substrate 1, the film 17 is selectively removed to the surface of the film 7 to form a groove. A polysilicon film 8 is buried in the groove 18. Ions are implanted with an implanting mask 5 having an end at a position separated l-2mum from the film pattern 8 to form a polysilicon resistance layer. Thus, an ion beam amount to irradiate resistance layer 8 is made uniform in the surface of a wafer. Thus, an irregularity in a resistance value can be suppressed to provide an accurate device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a highly accurate resistance.

[0002]

2. Description of the Related Art In recent years, as the degree of integration of analog ICs has increased, more precise resistors have been required. In particular,
It is important to reduce variations in resistance used in differential amplifier circuits, current mirrors and the like. FIGS. 3A to 3C show the conventional n
It is an example of a manufacturing process of a diffusion resistor using a base diffusion layer of a pn bipolar transistor as a resistance layer.

[0003] First, using techniques well known to the p-type Si substrate 1, to form an n ⁺ buried layer 2, n ^over epitaxial layer 3. next,
The SiO ₂ film 4 is formed about 50 nm, for example, a resist 5 as a mask, B ⁺ in 30kev by injecting under conditions of ^1.5E13cm-2, to form a p-type diffusion layer 6. Figure 3
(a) shows a state of ion implantation when forming the p-type diffusion layer 6 as a resistance layer, and the length W in the figure is the width of the resistance layer.

Next, in FIG. 3 (b), the Si ₃ N ₄ film 7 is applied to about 5
After 0 nm deposition, Si is used as a mask, for example.
The O ₂ film 4 and the Si ₃ N ₄ film 7 are dry-etched to form an opening window serving as an electrode portion. Next, the polysilicon film 8 is formed to a thickness of about 300 nm, and the polysilicon film 8 is dry-etched using, for example, a resist as a mask to form a polysilicon film pattern 8 to be an electrode. Next, for example, using a resist as a mask, B ^{+ is formed on the} polysilicon film pattern 8.
Was injected at 40 kev under the condition of 2E16 cm ^-2 , then 90
By heat treatment at 0 ° C. for 60 minutes in N ₂ atmosphere,
A p ⁺⁺ type diffusion layer 9 to be a contact diffusion region is formed.

Next, a CVD SiO ₂ film 10 is formed to a thickness of about 300 n.
m after the deposition, CVDS using the resist as a mask
The iO ₂ film 10 is dry-etched to form an opening window on the upper surface of the polysilicon film pattern 8. Next, for example, after forming a barrier metal 11 made of TiN / Ti having a thickness of about 100 nm / 20 nm, Al having a thickness of about 800 nm is formed.
-Si-Cu film 12 is formed by sputter deposition. afterwards,
For example, using the resist as a mask, the barrier metal 11 and the Al-Si-Cu film 12 are dry-etched to obtain a desired A
The 1-Si-Cu film pattern 12 is formed, and the polysilicon film 8 and the Al-Si-Cu film 12 are electrically connected to each other to complete this semiconductor device. FIG. 3C is a sectional structural view of a p-type diffused resistor having a resistance width W manufactured by a conventional method.

[0006]

However, in such a conventional method of manufacturing a semiconductor device, p as a resistance layer is used.
When the mold diffusion layer 6 is formed by ion implantation, since the incident angle of the ion beam on the semiconductor substrate is not uniform in the wafer surface, part of the ion beam incident on the resistance layer region is struck by the resist serving as the mask. As a result, the amount of beam incident on the resistance layer region within the wafer surface varies, and the resistance value also varies. For example, in FIG.
Shows the state of ion implantation when the resistances of the central portion of the wafer and the peripheral portion of the wafer are considered as the resistances. 13 is an ion implantation source, 5 is an implantation resist mask, W ₁ in the figure,
W ₂ is the width of the resistance formed. Now, assuming that the distance a from the ion implantation source to the wafer is a = 3425.7 mm, and a 6-inch wafer is considered, the distance b between the central portion and the peripheral portion of the wafer is b.
= 76.2 mm, the thickness c of the implantation resist mask is c = 1.
Assuming a size of 5 × 10 ⁻³ mm, the length d of the shaded portion of the resist when the ion beam is incident on the resistance layer in the peripheral portion of the wafer is d to 0.02 μm by a simple calculation. For example, considering a resistance of width W = 1 μm, the resistance value R (= ρ _s × L /
W, ρ _s : sheet resistance value, L: resistance length, approximately 2
% Variation occurs. In this example, a 6-inch wafer was considered, but in an 8-inch wafer, the variation is about 2.7%. From the above, as the device becomes finer and finer in the future, the conventional method has a big problem for improving the accuracy of the device.

In view of the above problems, it is an object of the present invention to provide a method of manufacturing a semiconductor device having a highly accurate resistance.

[0008]

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising a second insulating layer surrounding a first region for forming a resistance layer on one main surface of a semiconductor substrate. Forming a region, a step of forming a mask in which the first region and at least a part of the second region are opened, and a resistance is formed by ion implantation into the first region using the mask. And a step of introducing impurities for

In a more specific method of manufacturing a semiconductor device according to a second aspect, a groove is formed on one main surface of a one-conductivity-type semiconductor substrate in a direction perpendicular to the substrate surface, and the groove is surrounded by the groove. A step of forming an island region, a step of oxidizing the side surface and the bottom of the groove, ion implantation into the bottom of the groove to form a first diffusion layer of the opposite conductivity type on the semiconductor substrate, and a step of forming the groove A step of filling a coating film inside, a step of forming a mask layer so that an end portion is located at a predetermined position on the coating film surface,
Ion implantation into the island region using the mask layer as a mask to form a second diffusion layer of the opposite conductivity type; a step of removing the mask layer and then forming an insulating film; The structure includes a step of selectively removing and forming an opening window, a step of forming a metal film, and electrically connecting the semiconductor film pattern and the metal film.

A more specific method of manufacturing a semiconductor device according to a third aspect is the step of forming a first insulating film on one main surface of a semiconductor substrate, and forming the first insulating film at a constant depth. A step of selectively removing only the above to form a groove having a substantially vertical shape, a step of filling the groove with a semiconductor film, and a step of forming the groove and a mask opened to a predetermined distance from the periphery of the groove. , A step of implanting ions into the semiconductor film by using this mask, a step of forming a second insulating film, selectively removing the second insulating film, and forming an opening window, and forming a metal film And a step of electrically connecting the semiconductor film and the metal film.

[0011]

According to the present invention having the above-mentioned constitution, when the resistance layer is formed, a mask for opening the first region and at least a part of the second region for forming the resistance layer is used. Since the ions are implanted, even in the peripheral portion of the wafer, the ion beam does not become a shadow of the implantation mask and the amount of the beam incident on the resistance layer region does not vary.
As compared with the case of the conventional example, it is possible to suppress variations in the resistance value within the wafer surface.

When the resistance layer is formed, in the invention of claim 2, the mask has an end located at a predetermined position on the surface of the film, and in the invention of claim 2, the groove and the periphery of the groove are opened up to a predetermined distance. Since the ion implantation is performed using the mask, even in the peripheral portion of the wafer, there is no variation in the beam amount of the ion beam incident on the resistance layer region due to the shadow of the implantation mask. It is possible to suppress variations in resistance value within the plane.

[0013]

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

1 (a) and 1 (b) are sectional views of a diffusion resistance manufacturing process showing a first embodiment of the present invention. First, p-type Si
Using techniques well known to the substrate 1, to form an n ⁺ buried layer 2, n ^over epitaxial layer 3. Next, for example, by anisotropic dry etching using a resist as a mask, a groove of about 8 μm is dug in the direction perpendicular to the surface of the p-type Si substrate 1, and the side surface and the bottom surface of the groove are oxidized by about 100 nm to form an oxide film 14. To do. next,
For example, using resist as a mask, B ⁺ is 30 kev and 1.0E
By injecting under the condition of 13 cm ^-2 , p at the bottom of the groove
The mold diffusion layer 15 is formed. Next, the polysilicon film 16 is buried in the groove by the CVD method, and then the SiO ₂ film 4 having a thickness of about 50 nm is formed on the surface of the semiconductor substrate. Next, FIG.
As shown in (a), after forming the resist mask 5 so that the end portion is located near the center of the upper surface of the groove, B ⁺ is 30 kev and 1.5E13c by this resist mask 5.
Implantation is performed under the condition of m ^-2 to form the p-type diffusion layer 6. The length W'in the figure is the width of the p-type diffusion layer, that is, the resistance layer.

Next, in FIG. 1 (b), the Si ₃ N ₄ film 7 is applied to about 5
After 0 nm deposition, Si is used as a mask, for example.
The O2 layer 4 and Si ₃ N ₄ film 7 to form an opening window as an electrode portion is dry-etched. Next, the polysilicon film 8 is formed to a thickness of about 300 nm, and the polysilicon film 8 is dry-etched using, for example, a resist as a mask to form a polysilicon film pattern 8 to be an electrode. Next, for example, using a resist as a mask, B ^{+ is formed on the} polysilicon film pattern 8.
Was injected at 40 kev under the condition of 2E16 cm ^-2 , then 90
By heat treatment at 0 ° C. for 60 minutes in N ₂ atmosphere,
A p ⁺⁺ type diffusion layer 9 to be a contact diffusion region is formed.
Next, after depositing the CVD SiO ₂ film 10, the CVD SiO ₂ film 10 is dry-etched using a resist as a mask to form an opening window on the upper surface of the polysilicon film pattern 8. Next, for example, the thickness is about 100 nm / 20 nm
After the barrier metal 11 made of TiN / Ti is formed, an Al-Si-Cu film 12 having a thickness of about 800 nm is formed by sputter deposition. After that, the barrier metal 11 and the Al-Si-Cu film 12 are dry-etched using a resist as a mask to form a desired Al-Si-Cu film pattern 12, and the polysilicon film 8 and the Al-Si-Cu film are formed. 1
The semiconductor device is completed by electrically connecting the two.

As described above, in the present embodiment, when the p-type diffusion layer 6 as the resistance layer is formed by ion implantation, an implantation resist mask whose end is located near the center of the upper surface of the groove is used. Since it is used, as in the conventional example, it is possible to suppress the variation in the amount of the beam incident on the resistance layer region due to the fogging of the resist in the wafer surface, it is possible to reduce the variation in the resistance value in the wafer surface, and it is possible to achieve high accuracy. It is possible to form various diffusion resistances.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

2 (a) and 2 (b) are sectional views of a polysilicon resistor manufacturing process showing a second embodiment of the present invention. First,
After the SiO ₂ film 4 is formed to a thickness of about 600 nm on the p-type Si substrate 1, the Si ₃ N ₄ film 7 is deposited to a thickness of about 50 nm. Next, CVD
The SiO ₂ film 17 is formed to a thickness of about 300 nm, and the CVD SiO ₂ film 17 is dry-etched to a surface of the Si ₃ N ₄ film 7 by a thickness of about 300 nm using a resist as a mask to form a groove 18 having a predetermined pattern. Next, the polysilicon film 8 is embedded in the groove 18 by the CVD method. Next, the polysilicon film 8
After the end to a position apart 1~2μm was formed a resist mask 5 so as to be positioned from this resist mask 5, for example, As ⁺ is implanted under conditions of ^1.0E16cm-2 at 60 keV. 2 (a) is a cross-sectional structure diagram when ions are implanted into the polysilicon resistance layer 8 having a resistance width W ″.
CV is formed on the Si ₃ N ₄ film 7 including the polysilicon film pattern 8.
The DSiO ₂ film 10 is deposited to a thickness of about 300 nm.

Next, for example, using a resist as a mask, CV
The DSiO ₂ film 10 is dry-etched to form an opening window on the upper surface of the polysilicon film pattern 8. Next, for example, after forming a barrier metal 11 made of TiN / Ti having a thickness of about 100 nm / 20 nm, an Al—Si—Cu film 12 having a thickness of about 800 nm is formed by sputter deposition. After that, for example, using the resist as a mask, the barrier metal 11
And the Al-Si-Cu film 12 are dry-etched to form a desired Al-Si-Cu film pattern 12, and the polysilicon film 8 and the Al-Si-Cu film 12 are electrically connected to each other to obtain this semiconductor device. Is completed. FIG. 2B is a sectional structural view of a polysilicon resistor having a resistance width W ″ manufactured by the above process.

As described above, in this embodiment, when the polysilicon film pattern 8 as the resistance layer is ion-implanted,
The end portion of the implantation resist mask 5 is placed at a position 1 to 2 μm away from the polysilicon film pattern 8 and further CVDSi
By embedding the polysilicon film 8 in the groove 18 of the O ₂ film 17, the amount of ion beams incident on the polysilicon film pattern 8 can be made uniform over the entire surface of the wafer, and variations in the resistance value within the wafer surface can be suppressed. be able to. Further, the polysilicon film pattern 8 is replaced with the CVD SiO2 film 17
To form the trenches 18 in the polysilicon film pattern 8
Even if the CVD SiO ₂ film 10 is further formed on the CVD SiO ₂ film 17 containing, the step due to the polysilicon film pattern 8 can be eliminated, and a device having a structure having flatness can be provided.

[0021]

As is apparent from the above embodiments, according to the present invention, when the resistance layer is formed by ion implantation, the mask edge portion of the ion implantation is placed at a position apart from the resistance layer by a predetermined distance. As a result, it is possible to provide a highly accurate device in which the resistance value does not fluctuate over the entire wafer surface without the ion beam becoming a shadow of the implantation mask and causing fluctuations in the amount of beam incident on the resistance layer region.

[Brief description of drawings]

FIG. 1 is a sectional view of a diffusion resistor manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a manufacturing process of a polysilicon resistor according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a manufacturing process for explaining a conventional example.

FIG. 4 is a schematic diagram for explaining the problems of the conventional embodiment.

[Explanation of symbols]

1 p-type Si substrate 3 n ^over epitaxial layer 5 implanted resist mask 6 p-type diffusion layer 7 Si ₃ N ₄ film 8 polysilicon film 11 a barrier metal 12 Al over Si over Cu film 14 oxide film (the side surface of the groove) 15 p-type Diffusion layer (bottom of groove) 16 Polysilicon (inside groove) 17 CVDSiO ₂ film 18 Groove

Front Page Continuation (72) Inventor Akihiro Kanda 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. A step of forming a second region made of an insulating layer surrounding a first region for forming a resistance layer on a main surface of a semiconductor substrate, the first region and at least a part of the first region. A method of manufacturing a semiconductor device, comprising: a step of forming a mask having an opening in the second region; and a step of introducing an impurity for forming a resistance by ion implantation into the first region using the mask. 2. A step of forming a groove on a main surface of one conductivity type semiconductor substrate in a direction perpendicular to the surface of the substrate to form an island region surrounded by the groove, and a step of forming a side surface and a bottom portion of the groove. After oxidation, ions are implanted into the bottom of the groove to form a first diffusion layer of the opposite conductivity type on the semiconductor substrate, a step of filling a film inside the groove, and a predetermined position on the surface of the film. Forming a mask layer so that an end portion thereof is located, a step of ion-implanting the island region using the mask layer as a mask to form a second diffusion layer of a reverse conductivity type, and the mask layer After removing, a step of forming an insulating film, a step of selectively removing the insulating film to form an opening window, a metal film is formed, and the semiconductor film pattern and the metal film are electrically connected. A method of manufacturing a semiconductor device, the method including: . 3. A step of forming a first insulating film on a main surface of a semiconductor substrate, and a step of selectively removing the first insulating film by a predetermined depth to form a groove having a substantially vertical shape. A step of forming, a step of filling the groove with a semiconductor film, a step of forming a mask opening to a predetermined distance from the groove and the periphery of the groove, and a step of implanting ions into the semiconductor film using the mask Forming a second insulating film, selectively removing the second insulating film to form an opening window, forming a metal film, and electrically connecting the semiconductor film and the metal film A method of manufacturing a semiconductor device, comprising: