JPS63255955A - Input protective circuit - Google Patents
Input protective circuitInfo
- Publication number
- JPS63255955A JPS63255955A JP9117187A JP9117187A JPS63255955A JP S63255955 A JPS63255955 A JP S63255955A JP 9117187 A JP9117187 A JP 9117187A JP 9117187 A JP9117187 A JP 9117187A JP S63255955 A JPS63255955 A JP S63255955A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- semiconductor substrate
- circuit
- film
- resistance element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001681 protective effect Effects 0.000 title abstract 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000011229 interlayer Substances 0.000 abstract description 7
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000005684 electric field Effects 0.000 abstract description 4
- 230000005611 electricity Effects 0.000 abstract description 3
- 230000003068 static effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000035936 sexual power Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〕
本発明は入力保護回路に関し、特に半導体集積回路装置
に用いられる入力保護回路に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an input protection circuit, and particularly to an input protection circuit used in a semiconductor integrated circuit device.
従来半導体集積回路装置に用いられている入力保護回路
としては、多結晶シリコンから成る直列抵抗素子を信号
入力回路に直列に挿入したものが知られている。As an input protection circuit conventionally used in semiconductor integrated circuit devices, one in which a series resistance element made of polycrystalline silicon is inserted in series with a signal input circuit is known.
上述した従来の入力保護回路は、直列抵抗素子としての
多結晶シリコンと半導体基板との間には酸化膜と層間絶
縁膜があるだけであり、信号入力端子に静電気などによ
り高電圧が印加された場合、多結晶シリコン側に電界が
集中するため、ここから絶縁破壊が生じて半導体基板と
多結晶シリコンとが短絡し、半導体集積回路が動作不能
となるという問題点がある。In the conventional input protection circuit described above, there is only an oxide film and an interlayer insulating film between the polycrystalline silicon as a series resistance element and the semiconductor substrate, and high voltage is not applied to the signal input terminal due to static electricity. In this case, since the electric field is concentrated on the polycrystalline silicon side, dielectric breakdown occurs from there, shorting the semiconductor substrate and the polycrystalline silicon, and the semiconductor integrated circuit becomes inoperable.
本発明の目的は、入力端子に高電圧が印加されたときに
直列抵抗素子としての多結晶シリコンと半導体基板との
短絡が発生しにくい入力保護回路を提供することにある
。An object of the present invention is to provide an input protection circuit in which short circuits between polycrystalline silicon as a series resistance element and a semiconductor substrate are less likely to occur when a high voltage is applied to an input terminal.
し問題点を解決するための手段〕
本発明の入力保護回路は、半導体集積回路装置の信号入
力回路に直列に挿入された多結晶シリコンから成る直列
抵抗素子を有する入力保護回路において、前記直列抵抗
素子と半導体基板との間に前記直列抵抗素子の幅よりも
広く前記半導体基板および電源線その他いかなる信号線
にも接続されていない浮遊状態の多結晶シリコン膜を設
けて構成されている。Means for Solving Problems] The input protection circuit of the present invention is an input protection circuit having a series resistance element made of polycrystalline silicon inserted in series in a signal input circuit of a semiconductor integrated circuit device. A polycrystalline silicon film in a floating state, which is wider than the width of the series resistance element and is not connected to the semiconductor substrate, the power supply line, or any other signal line, is provided between the element and the semiconductor substrate.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の平面図、第２図はそのＡ−
Ａ’断面図である。半導体基板１上には酸化膜２が形成
され、その上に電気的にどこにも接続されていない浮遊
状態の多結晶シリコン膜３が形成されている。多結晶シ
リコン膜３の上には層間絶縁膜４があり、その上に入力
回路に直列に挿入されている多結晶シリコンから成る直
列抵抗素’：ｉ’−５が設けられている。この直列抵抗
素子５にはコンタクト孔６が設けられ、金属配線（アル
ミニウム）７を介して信号入力端子に接続するための入
力パッド８に接続されている。多結晶シリコン膜３の幅
りは直列抵抗素子５の幅ｄに対して十分広く選定されて
いる。なお、参照番号９は初段回路を構成する拡散層で
ある。Fig. 1 is a plan view of one embodiment of the present invention, and Fig. 2 is its A-
It is an A' sectional view. An oxide film 2 is formed on a semiconductor substrate 1, and a floating polycrystalline silicon film 3 that is not electrically connected to anything is formed thereon. An interlayer insulating film 4 is provided on the polycrystalline silicon film 3, and a series resistor element ':i'-5 made of polycrystalline silicon and inserted in series with the input circuit is provided on the interlayer insulating film 4. This series resistance element 5 is provided with a contact hole 6 and is connected via a metal wiring (aluminum) 7 to an input pad 8 for connection to a signal input terminal. The width of the polycrystalline silicon film 3 is selected to be sufficiently wider than the width d of the series resistance element 5. Note that reference number 9 is a diffusion layer that constitutes the first stage circuit.
上述の構成によれば、静電気などにより信号入力端子に
高電圧が加わった場合、直列抵抗素子５の付近に電界が
集中して絶縁破壊が発生したとしても、眉間絶縁膜４が
破壊して多結晶シリコン膜３との間が短絡するだけで止
まり、半導体基板１に達しないで済むため致命傷とはな
らない、すなわち、多結晶シリコン膜３と金属配線７と
が短絡状態となった場合でも、多結晶シリコ膜３は幅が
広く面積も大きいため電界の集中が少なく、酸化膜２に
は絶縁破壊が発生しにくいため、多結晶シリコン膜３と
半導体基板１との間隔が小さくてもほぼ同等の耐圧を持
たせることが可能である。従って、直列抵抗素子５と多
結晶シリコン膜３が短絡した場合は、入力容量は大きく
なるが耐圧としては従来とほぼ同等の値を持たせること
かで・きる。According to the above configuration, when a high voltage is applied to the signal input terminal due to static electricity or the like, even if the electric field concentrates near the series resistive element 5 and dielectric breakdown occurs, the glabella insulating film 4 is destroyed and many The short-circuit between the polycrystalline silicon film 3 and the metal wiring 7 is sufficient, and the short-circuit does not reach the semiconductor substrate 1, so there is no fatal damage. Since the crystalline silicon film 3 has a wide width and a large area, there is less concentration of electric field, and dielectric breakdown does not easily occur in the oxide film 2. Therefore, even if the distance between the polycrystalline silicon film 3 and the semiconductor substrate 1 is small, the distance between the polycrystalline silicon film 3 and the semiconductor substrate 1 is almost the same. It is possible to provide pressure resistance. Therefore, when the series resistance element 5 and the polycrystalline silicon film 3 are short-circuited, the input capacitance increases, but the breakdown voltage can be kept approximately the same as the conventional one.
（発明の効果）
以上説明したように、本発明は、入力保護回路の直列抵
抗素子としての多結晶シリコンと半導体基板との間に、
浮遊状態の幅の広い多結晶シリコン膜を有することによ
り、高電圧の印加によって直列抵抗素子としての多結晶
シリコン付近から絶縁破壊を起こすことがあっても、半
導体基板との短絡を防止でき、信頼性が向上するという
効果を有する。(Effects of the Invention) As explained above, the present invention provides the following advantages: between polycrystalline silicon as a series resistance element of an input protection circuit and a semiconductor substrate
By having a wide polycrystalline silicon film in a floating state, even if dielectric breakdown occurs near the polycrystalline silicon as a series resistance element due to the application of high voltage, short circuits with the semiconductor substrate can be prevented, making it reliable. It has the effect of improving sexual performance.
第１図は本発明の一実施例の平面図、第２図はその断面
図である。
１・・・・・・半導体基板、２・・・・・・酸化膜、３
・・・・・・多結晶シリコン膜、４・・・・・・層間絶
縁膜、５・・・・・・直列抵抗素子、６・・・・・・コ
ンタクト孔、７・・・・・・金属配線、８・・・・・・
入力パッド、９・・・・・・拡散層。
箔 １ 目
フ紘敞層FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a sectional view thereof. 1... Semiconductor substrate, 2... Oxide film, 3
...Polycrystalline silicon film, 4...Interlayer insulating film, 5...Series resistance element, 6...Contact hole, 7... Metal wiring, 8...
Input pad, 9... Diffusion layer. Foil 1st layer
Claims (1)
た多結晶シリコンから成る直列抵抗素子を有する入力保
護回路において、前記直列抵抗素子と半導体基板との間
に前記直列抵抗素子の幅よりも広く前記半導体基板およ
び電源線その他いかなる信号線にも接続されていない浮
遊状態の多結晶シリコン膜を設けたことを特徴とする入
力保護回路。In an input protection circuit having a series resistance element made of polycrystalline silicon inserted in series in a signal input circuit of a semiconductor integrated circuit device, the distance between the series resistance element and the semiconductor substrate is wider than the width of the series resistance element. An input protection circuit characterized by providing a polycrystalline silicon film in a floating state that is not connected to a semiconductor substrate, a power supply line, or any other signal line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9117187A JPS63255955A (en) | 1987-04-13 | 1987-04-13 | Input protective circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9117187A JPS63255955A (en) | 1987-04-13 | 1987-04-13 | Input protective circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63255955A true JPS63255955A (en) | 1988-10-24 |
Family
ID=14019021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9117187A Pending JPS63255955A (en) | 1987-04-13 | 1987-04-13 | Input protective circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63255955A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0511667A (en) * | 1991-07-02 | 1993-01-22 | Mitsubishi Electric Corp | Electrophotographic image forming device |
-
1987
- 1987-04-13 JP JP9117187A patent/JPS63255955A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0511667A (en) * | 1991-07-02 | 1993-01-22 | Mitsubishi Electric Corp | Electrophotographic image forming device |
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