JP3052462B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device provided with a protection circuit for preventing electrostatic breakdown.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit device,
In order to prevent electrostatic breakdown, PN junction diodes are respectively connected in a forward direction between the higher voltage source and the lower voltage source and the signal input terminal.

FIG. 5 is a sectional view showing a conventional semiconductor integrated circuit device. N-type buried layers 2 a and 2 b are selectively formed on P-type silicon substrate 1. N-type epitaxial layers 4a and 4b are selectively formed on P-type silicon substrate 1 including N-type buried layers 2a and 2b, respectively.
a and 2b are N-type epitaxial layers 4a and 4b, respectively.
Has been pulled out to the surface. The N-type epitaxial layers 4a and 4b are separated from each other by an oxide film 11 formed on the surface of the P-type silicon substrate 1. P-type diffusion layer 15
Reference numerals a and 15b are formed on the surfaces of the N-type epitaxial layers 4a and 4b, respectively. An interlayer insulating film 9 is applied on the entire surface of the P-type silicon substrate 1, and after a predetermined contact port is provided in the interlayer insulating film 9, a wiring layer 10 is pattern-formed on the entire surface. Thus, the P-type diffusion layer 15a and the N-type buried layer 2b are connected to the signal input terminal 8 via the wiring layer 10, and the N-type buried layer 2a is connected to the higher voltage source 6 via the wiring layer 10. The P-type diffusion layer 15b is connected to the lower voltage source 7 via the wiring layer 10.

In the above-described conventional semiconductor integrated circuit device, a PN junction comprising a P-type diffusion layer 15a, an N-type epitaxial layer 4a and an N-type buried layer 2a is provided between a signal input terminal 8 and a higher voltage source 6. Diodes are connected in the forward direction,
An N-type buried layer 2b, an N-type epitaxial layer 4b, and a P-type diffusion layer 15b are provided between the signal input terminal 8 and the lower voltage source 7.
Are connected in the forward direction, and this pair of diodes constitutes a protection circuit.
Therefore, when a positive charge is applied to the signal input terminal 8,
This positive charge is absorbed by the higher voltage source 6, and when a negative charge is applied to the signal input terminal 8, the negative charge is absorbed by the lower voltage source 7. Thereby, the semiconductor integrated circuit device can be protected, and electrostatic breakdown can be prevented.

Incidentally, the diode as a protection element must be formed larger than an element used for another circuit configuration in order to prevent its own electrostatic destruction.

[0006]

However, in the above-described conventional semiconductor integrated circuit device, since a pair of diodes serving as protection elements are arranged in the plane direction of the P-type silicon substrate 1, the semiconductor integrated circuit device is not used. In this case, there is a problem that the area of the protection circuit becomes significantly large and the chip size becomes large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor integrated circuit device capable of reducing the area of a protection circuit as compared with the related art.

[0008]

A semiconductor integrated circuit device according to the present invention comprises an N-type buried layer formed on a P-type semiconductor substrate, and the P-type semiconductor substrate formed on the N-type buried layer. And a N-type layer formed on the P-type buried layer, the N-type buried layer and the P-type buried layer being connected to a signal input terminal. The P-type semiconductor substrate is connected to a lower voltage source, and the N-type layer is connected to a higher voltage source.

[0009]

In the present invention, the N-type buried layer is formed on a P-type semiconductor substrate, and the N-type buried layer and the P-type semiconductor substrate form a first diode. On the other hand, the P-type buried layer is formed on the N-type buried layer, the N-type layer is formed on the P-type buried layer, and the P-type buried layer and the N-type layer are formed on the second diode. Is formed. The first diode is connected in a forward direction between the signal input terminal and the lower voltage source, and the second diode is connected in a forward direction between the signal input terminal and the higher voltage source. You. Therefore, when a positive or negative charge is applied to the signal input terminal, the charge is absorbed by the higher voltage source or the lower voltage source. Therefore, the semiconductor integrated circuit device can be protected and electrostatic breakdown can be prevented.

According to the present invention, since the first and second diodes are vertically stacked in the direction perpendicular to the plane direction of the P-type semiconductor substrate, the area of the protection circuit can be reduced as compared with the related art. it can. Thus, the chip size of the semiconductor integrated circuit device can be reduced.

[0011]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a sectional view showing a semiconductor integrated circuit device according to a first embodiment of the present invention. The N-type buried layer 2 is selectively formed on the P-type silicon substrate 1 by an ion implantation method or a thermal diffusion method. The P-type buried layer 3 is selectively formed on the N-type buried layer 2 by an ion implantation method. The N-type epitaxial layer 4 is selectively formed on the P-type silicon substrate 1 including the N-type buried layer 2 by an epitaxial growth method. It is drawn out to the surface of the type epitaxial layer 4. The N-type epitaxial layer 4 is isolated by an oxide film 11 formed on the surface of the P-type silicon substrate 1. N-type layer 5
Is formed on the surface of the N-type epitaxial layer 4 by ion implantation or thermal diffusion. An interlayer insulating film 9 is provided on the entire surface of the P-type silicon substrate 1. After a predetermined contact hole is provided in the interlayer insulating film 9, a wiring layer 10 is formed on the entire surface.
Are patterned. Thereby, the N-type buried layer 2
And P-type buried layer 3 is connected to signal input terminal 8 via wiring layer 10.
The N-type layer 5 is connected to a higher voltage source 6 via a wiring layer 10, and the P-type silicon substrate 1 is connected to a lower voltage source 7 via a wiring layer 10.

FIG. 2 is a circuit diagram showing the above-described semiconductor integrated circuit device. As shown in FIG. 2, a PN junction diode 13 composed of a P-type buried layer 3, an N-type epitaxial layer 4, and an N-type layer 5 is connected between a signal input terminal 8 and a higher voltage source 6 in a forward direction. A PN junction diode 12 composed of an N-type buried layer 2 and a P-type silicon substrate 1 is connected between the signal input terminal 8 and the lower voltage source 7 in the forward direction. 13 constitutes a protection circuit. Therefore, when a positive charge is applied to the signal input terminal 8, the positive charge is absorbed by the higher voltage source 6, and when a negative charge is applied to the signal input terminal 8, the negative charge becomes It is absorbed by the lower voltage source 7. Therefore, the semiconductor integrated circuit device including the input circuit (or the output circuit or the like) 14 connected to the signal input terminal 8 can be protected, and electrostatic breakdown can be prevented.

According to the present embodiment, the diodes 12, 13 serving as protection elements are vertically stacked in a direction perpendicular to the plane direction of the P-type silicon substrate 1, so that the area of the protection circuit is reduced as compared with the prior art. can do. Thus, the chip size of the semiconductor integrated circuit device can be reduced.

FIG. 3 is a sectional view showing a semiconductor integrated circuit device according to a second embodiment of the present invention. In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description of those portions will be omitted. That is, in this embodiment, after the N-type epitaxial layer 4 is formed, a P-type layer (resistance) 16 reaching the P-type buried layer 3 is formed on the surface of the N-type epitaxial layer 4 by ion implantation. I have. The P-type layer 16 is connected to the signal input terminal 8 via the wiring layer 10. Note that the N-type buried layer 2 and the P-type buried layer 3 are
0 are connected to each other.

FIG. 4 is a circuit diagram showing the above-mentioned semiconductor integrated circuit device. In this case, unlike the first embodiment,
A resistor 16 is connected between the signal input terminal 8 and the cathode of the diode 12 and the anode of the diode 13. For this reason, electrostatic breakdown of the semiconductor integrated circuit device can be prevented, and a steep pulse input to the signal input terminal 8 can be smoothed.

According to the present embodiment, as in the first embodiment, the diodes 12, 13 are vertically stacked in the direction perpendicular to the plane of the P-type silicon substrate 1, so that the area of the protection circuit is reduced. It can be reduced to about 1/2 of the conventional size.

[0018]

As described above, according to the present invention, N
A first diode composed of a p-type buried layer and a p-type semiconductor substrate and a second diode composed of a p-type buried layer and an n-type layer in a direction perpendicular to the plane direction of the p-type semiconductor substrate , The area of the protection circuit can be reduced as compared with the conventional case. Thus, the chip size of the semiconductor integrated circuit device can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a semiconductor integrated circuit device according to a first example of the present invention.

FIG. 3 is a sectional view showing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 5 is a sectional view showing a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 Reference Signs List 1: P-type silicon substrate 2, 2a, 2b; N-type buried layer 3: P-type buried layer 4, 4a, 4b; N-type epitaxial layer 5; N-type layer 6; higher-side voltage source 7; Source 8; Signal input terminal 9; Interlayer insulating film 10; Wiring layer 11; Oxide films 12, 13; Diode 14; Input circuit 15a; 15b; P-type diffusion layer 16; P-type layer (resistance)

Claims (1)

(57) [Claims] An N-type buried layer formed on a P-type semiconductor substrate; a P-type buried layer formed on the N-type buried layer and insulated from the P-type semiconductor substrate; An N-type layer formed on the N-type buried layer, wherein the N-type buried layer and the P-type buried layer are connected to a signal input terminal, and the P-type semiconductor substrate is connected to a lower voltage source. Wherein the N-type layer is connected to a higher voltage source.