JPS63237573A - Manufacture of mis semiconductor device - Google Patents

Abstract

PURPOSE:To avoid increase of degradation and variation of Vt of an SOI type MOS-FET by forming a 2nd oxide film in the region of a semiconductor film except an element isolation region by subjecting the semiconductor film to an oxidizing treatment. CONSTITUTION:A semiconductor film 8 is removed by etching until its thickness becomes less than a half of the initial thickness with a resist layer 9, a nitride film 12 and a 1st oxide film 11 as a mask and impurity ions are implanted into the semiconductor film 8. After the resist later 9 is removed and the semiconductor film 8 is subjected to an oxidizing treatment to convert the semiconductor film 8 except an element isolation region into a 2nd oxide film 10, the nitride film 12 and the 1st oxide film 11 are removed and the semiconductor film 8 is polished to level the substrate surface and isolate the element. As the SiO2 film 10 as this exists, the gate SiO2 film of the 2nd MOS-FET is thicker than the gate SiO2 film of the 1st MOS-FET. With this constitution, degradation and variation of Vt of an SOI type MOS-FET composed of the 2nd MOS-FET can be avoided.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing an MIS type semiconductor device.

[Conventional technology]

MIS type semiconductor device formed on a semiconductor film on an insulating film, so-called SOI (Semiconductor on I)
MIS type semiconductor devices with n5ulator) structure have smaller junction capacitance than conventional MIS type semiconductor devices, and element isolation is complete and simple, making them suitable for high-speed large-scale integrated circuits (LSIs). It is said that there is.

Conventionally, in a method of manufacturing a MIS type semiconductor device having an SOI structure, one of the element isolation methods is a method of removing all unnecessary portions of a semiconductor film on an insulator and forming the semiconductor film in an island shape. For example, Nis de Nis Malhi (S, D, S, Malhi) et al. 1982
1982Symposium on VLST T-
Technology Digest of Technology
This method is reported on page 107 of Nical PaperS). FIG. 2 is a schematic cross-sectional view of an SOI-type MIS-type semiconductor device in which element isolation is performed using this island method. Here, FIG. 2(b) is a cross section taken along plane B-8 in FIG. 2(a). In the figure, 1 is SL board, 2 is Sin,
3 is a source/drain diffusion layer in the Si film, 4 is a gate SiO□ film, and 5 is a gate electrode.

6 is a first channel region, and 7 is a second channel region.

[Problem that the invention seeks to solve]

However, the M
In the case of an isi semiconductor device (MIS type semiconductor device/5OI), as shown in FIG. 2(b), in addition to the usual first channel region 6 on the SL pattern film, a second channel region 7 is formed on the side wall of the Si film. is formed. These first and second channel regions 6 and 7 are connected to the first MiSi semiconductor device and the second MiSi semiconductor device, respectively.
semiconductor devices are formed, and these first and second MIS
type semiconductor devices are equivalent to being connected in parallel. In this case, the second channel region 7. similar to the first channel region. There is also a voltage applied to the gate electrode 5 (threshold voltage, v) at which a current begins to flow between the source and drain. Therefore, lVt of the first MIS type semiconductor device 6
, l and the second MIS type semiconductor device 717) l V t
If the relationship with 21 is 1vtzl<Ivtl, then M
Vt of the IS type semiconductor device/SOI becomes equal to Vt2 of the second MIS type semiconductor device. However, in general V
t depends on the gate film thickness, impurity concentration and crystallinity of the channel region, and it is very difficult to control Vt2 in the second MIS type semiconductor device 7 where these are difficult to control.

Therefore, if lVt, l<1vt11, the MIS type semiconductor device/SOI c7) Vt is the first
The vtl of the MIS type semiconductor device 6 is lower than that of the MIS type semiconductor device 6, and the variation is also increased.

The object of the present invention is to solve the above-mentioned conventional problems by
An object of the present invention is to provide a method for manufacturing an MIS type semiconductor device having an I structure.

[Means for solving problems]

The present invention provides a method for forming an MIS type semiconductor device on a semiconductor thin film formed on an absolute M film, in which a first oxide film and a nitride film are formed on the semiconductor thin film, a resist is applied to the surface of the first oxide film and a first nitride film, and a resist is applied to the surface of the first oxide film and a nitride film. After patterning the resist so that it remains on the element region where the MIS type transistor is to be fabricated, etching the nitride film and the first oxide film using the resist as a mask, etching the resist, the nitride film, The semiconductor + using the first oxidation monomer as a mask
11!1 by etching until its film thickness becomes less than half, impurity ions are implanted into the semiconductor film, and then the resist is removed and an oxidation treatment is performed to remove the semiconductor film in areas other than the element region. after forming the semiconductor film into a second oxide film, removing the nitride film and the first oxide film, and then polishing the semiconductor film to flatten the surface of the saw plate to perform element isolation. This is a method for manufacturing a type semiconductor device.

〔Example〕

The present invention will be explained below using examples.

In this embodiment, a Si film is used as the semiconductor film, a Si0□11 film is used as the insulating film, and an n-channel MO3FET is used as the MIS type semiconductor device.

FIG. 1 is a schematic cross-sectional view showing the manufacturing process of an n-channel MO5FET having an SOI structure. The SOI structure substrate is the first
As shown in FIG.
n.

Membrane 2. Film thickness 0.5. A Si film 8 formed in sequence is used. On this Si film, as shown in FIG.
, N4 film 12 are sequentially formed. Next S13 N411
A resist 9 is applied onto the screen 12 as shown in FIG. 1(c), and patterned so that the resist 9 remains on the MOSFET element region. Thereafter, using the resist 9 as a mask, the Si3N4 film 12 and 5iOz III 11 are dry-etched, and 5i11 and 8 are further removed by dry etching to a film thickness of 0.3 mm. After that, Figure 1 (d
), boron ions are implanted into region 13 of Si film 8 using resist 9 as a mask. The implantation conditions were an acceleration voltage of 150 eV and a dose of 5 x 101:'low 2.
It is. Thereafter, the Si film 8 in the region 13 is oxidized under the conditions necessary for all oxidations, and the SiO□ film 10 is obtained. At this time, the oxidation rate of Si III into which boron ions were implanted was about three times faster than that of the Si film into which no ions were implanted.

Therefore, when the Si film 8 (film thickness 0.2p) in region 13 is oxidized, the side surfaces of 5illi other than region 13 are oxidized by 0.07 μm from the surface, and the test oblique cross section is shown in FIG.
It becomes as shown in e). Next, after removing the Si3N4 film 12, the 5in2 film was 0.07. Wet etching of the Sin film is performed for the time necessary to remove the remaining amount. As a result, as shown in Figure 1), 5ilf18 is 5in.
A substrate in which about 0, t3IlvI protrudes from the surface of the 2 film 10 is obtained. Thereafter, the 5it FJ8 is made into a thin one by borizing. As the thickness of the Si film 8 and the SiO□ film 10 become the same, the rate of boring progress for the 5in2 film is much slower than that of Si, so the Si film 1
The area of 0 serves as a polishing stopper, and polishing does not proceed any further. As a result, a substrate having an SOI structure as shown in FIG. 1 (phantom) with a flat substrate surface and with the Si film 8 separated into elements is obtained.

SOI structure MOSFE produced using this substrate
A schematic cross-sectional view of T is shown in FIGS. 1(b) and 1(i). Here, FIG. 1G) is a sectional view taken along the line II in FIG. 1(h). In the figure, 3 is the source/drain diffusion layer of MOSFET,
4 is a gate 5in2 film, 5 is a gate electrode, 6 is a first channel region, and 7 is a second channel region.

The SOI type MO3FET of the present invention also uses Si
A first M formed in the first channel region on the upper surface of the membrane 8
i)9.
It is constructed by joining into columns. However, in the case of the present invention, since the 5j02 film IO exists, the second MOSF
ET gate S10. The film is thicker than the gate 5in2 film of the first MOSFET.

Here, Vt for n-channel MO3FI<T is 5i-3j,
Assuming that the interface level at the 02 interface is small, VtyV, B+2V, + □ Ci= - where VFn is the flat band voltage, ψ8 is the Fermi level of Si, and Ks' and Ki are the relative permittivity of silicon and silicon oxide film, respectively. rate, ε. is the dielectric constant, q is the charge amount of electrons + NA is the density of acceptor impurities per unit volume, C1 is the capacitance per unit area of the gate oxide film, and d is the thickness of the gate oxide film.

As the gate oxide film becomes thicker, v becomes higher according to the above equation. In the case of the present invention, since the gate oxide film of the second MOSFET is thicker than the gate oxide film of the first MOSFET, the gate oxide film of the second MOSFET is thicker than the gate oxide film of the first MOSFET. Second MOSFET (1) Threshold voltage vt,
The relationship between Vt and Vt is Vtl<Vt. In addition, generally the channel width of the first MOSFET is the same as that of the second MOSFET.
I: larger than that of T.

Therefore, number one. The relationship between the source-drain current ID11 and ID2 of the second MOSFET is always Ir)i > I
Dz, and the source-drain current of the MOSFET with the 5(II structure) can be approximated by the source-drain current of the first MOSFET.

That is, the static characteristics of the MOSFET having the SOI structure are almost equal to the static characteristics of the first MOSFET. Therefore, the decrease or variation in Vt of the SOi structure MOSFET caused by the second MOSFET, which was a problem in the conventional method, does not occur.

In the above embodiments, the semiconductor film is a Si film, the insulating film is a 5in2 film, and the MIS type semiconductor device is a MOSFET.
Although ET is used, there is no problem even if other semiconductor films, insulating films, or channel type MIS semiconductor devices are used.
It is possible to suppress a decrease in Vt, an increase in variation, and an increase in leakage current.

Further, it has the effect that a thin film SDI type MO5FET can be manufactured by polishing.

[Brief explanation of the drawing]

FIG. 1(a) to ■ are SOI type MO3FETs according to the present invention.
A schematic cross-sectional view showing an example of the manufacturing process in the order of steps, (1
) is a cross-sectional view taken along the line I-I of (Xun), FIG. 6 1...Si substrate 2,10.11.
...5iO7ll'! 3...MOSFET source
Drain diffusion layer 4...Gate 5io21 model
-... Gate resistance structure 6... First channel region
7... Second channel region 8... Si film
9...Regis 1-12...Si3N4
Membrane 13...A region (a) where boron ions are implanted in the silicon layer 8.
Figure 3-5 Source/drain diffusion layer 4--Gate 5
February Moxibustion 5--Cate electrode 6--First channel deposit 7--Second channel deposit 1 Figure R)) Diagram 2 Procedural amendment (voluntary) 63.2. 18 Showa year month day

Claims (1)

[Claims] (1) In a method for forming an MIS type semiconductor device on a semiconductor thin film formed on an insulating film, a first oxide film and a nitride film are formed on the semiconductor thin film, a resist is applied to the surface thereof, and the resist After patterning the nitride film and the first oxide film so as to remain on the element region for manufacturing the MIS type transistor, etching the nitride film and the first oxide film using the resist as a mask, and then patterning the resist,
using a nitride film and a first oxide film as a mask, removing the semiconductor film by etching until the film thickness becomes less than half, implanting impurity ions into the semiconductor film, and then removing the resist; After performing oxidation treatment to turn the semiconductor film other than the element region into a second oxide film, the nitride film and the first oxide film are removed, and then the semiconductor film is polished to planarize the substrate surface to form the element. A method for manufacturing an MIS type semiconductor device characterized by performing separation.