JPS63237569A - Manufacture of mis type semiconductor device - Google Patents

Abstract

PURPOSE:To increase Vt of a transistor corresponding to the sidewall of an element region larger than that of a transistor at the top of the element region by forming a semiconductor film which contains in high concentration the same impurity as that of a substrate only at the sidewall of the region, and increasing the thickness of the oxide film of the sidewall of the region. CONSTITUTION:A polysilicon film 6 on a surface is etched to retain the film 6 diffused in high concentration with boron only on the sidewall of a silicon film 3, and the films 3, 6 are partly thermally oxidized. An Si3N4 film 4 prevents the top of an element region from being oxidized at this time. As a result, a thick oxide film 2' is formed only on the sidewall of the region. Thus, the film 6 in which boron is diffused in high concentration and the film 2' are formed on the sidewall of the region of an MOS semiconductor device of SOI structure. Thus, Vt of the transistor of second channel region corresponding to the sidewall of the region is increased larger than that of a transistor of a first channel region to remove the influence of the transistor of the sidewall.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing an MIS type semiconductor device.

[Conventional technology]

MIS type semiconductor device formed on a semiconductor film on an insulating film, so-called SOI (Semiconductor on I)
MIS type semiconductor devices with n5ulator) structure have smaller junction capacitance than conventional MIS type semiconductor devices, and element isolation is complete and simple, making them suitable for high-speed large-scale integrated circuits (LSIs). It is said that

Conventionally, in the manufacturing process of MIS type semiconductor devices with SOI structure, one of the element isolation methods is a process of removing all unnecessary parts of the semiconductor film on the insulator and forming the semiconductor film in an island shape. 1982 Symposium on Technical Papers (1982S)
Symposium on VLSI Technology
geyDigeSt of Technical Pa
pers), page 107 describes this method (island method).
is reported. FIG. 2(a) is a schematic cross-sectional view of an IS type semiconductor device having an SOI structure in which element isolation is performed using this island method. Figure 2 (b) is B-8 in Figure 2 (a).
This is the cut surface of the surface. In the figure, 1 is a silicon substrate, 2 is a sin
, a film, 7 a gate Sin, a film 8 a gate electrode, 9 a source/drain diffusion layer in the silicon film, 10 a first channel region, and 11 a second channel region.

[Problem that the invention seeks to solve]

However, the M
In the case of an IS type semiconductor device, in addition to the usual first channel region lO on the silicon film, as shown in FIG.
A second channel region 11 is formed on the sidewall of the ItA.

This channel region 11 is the first M of the channel region IO.
It can be considered as a channel region of a second MIS type semiconductor device coupled in parallel to the IS type semiconductor device. Therefore, in the second channel region 11 as well as in the first channel region 10, there is a voltage applied to the gate electrode 7 (threshold voltage, Vt) at which a current begins to flow between the source and drain. Therefore, lVt□1 of the first MIS type semiconductor device
The relationship between Ivtzl and the second MIS type semiconductor device is I
If Vfzl<IVttl, the Vt of the MIS type semiconductor device/SOI is equal to the Vt of the second MIS type semiconductor device.
It becomes equal to t2. However, in general, Vt depends on the gate film thickness, the impurity concentration and crystallinity of the channel region, and since it is difficult to control these, it is very difficult to control Vt2 in the second MIS type semiconductor device. Therefore, l vtx There is a case where I < l Vtz l, and therefore, the Vt of the MIS type semiconductor device/SOI is lower than the vtl of the first MIS type semiconductor device which is the purpose of manufacturing, and the variation also increases.

The purpose of the present invention is to solve the above-mentioned problems of the conventional SOI
An object of the present invention is to provide a method for manufacturing an MIS type semiconductor device having a structure.

[Means for solving problems]

The gist of the present invention is to form a Si, N4 film on a first semiconductor film on an insulator substrate in the element region isolation step in the manufacturing process of a MIS type semiconductor device on an insulator substrate, and then to After forming a photoresist pattern corresponding to the element area by exposing and developing the resist film,
Using this as a mask, the Si, N4 and semiconductor films are etched, and then the photoresist film is peeled off, and impurities of the first conductivity type are diffused to form a second semiconductor film, which is then etched. The second semiconductor film is left on at least the side wall of the first semiconductor film, and
After forming an element region made of a semiconductor film, thermal oxidation is performed to form a thick oxide film only on the side walls of the element region, and then the Si, N, and films on the first semiconductor film are etched away. This is a method for manufacturing an MIS type semiconductor device.

[Principle/effect]

Generally, the threshold voltage Vt of a MIS type semiconductor device is Si-
Sin, assuming that the interface state at the interface is small, $51 is - Vtl: 1lIV, B+2ma, + □Ci== - where VFR is the flat band voltage, ψB is the Fermi level of Si, Ks, Ki are Relative permittivity and ε of silicon and silicon oxide film, respectively. is the dielectric constant, 9 is the electron charge, N^ is the density of acceptor impurity per unit volume, C
1 is the capacitance per unit area of the gate oxide film,
d is the gate oxide film thickness.

As can be seen from the above equation, the threshold voltage (Vt) of a KISIS type semiconductor device increases in proportion to the gate insulating film thickness or the square root of the substrate impurity concentration. The device region isolation method of the present invention is characterized by forming a semiconductor film containing a high concentration of the same impurity as the substrate impurity only on the sidewalls of the device region, and increasing the thickness of the oxide film only on the sidewalls of the device region. . Therefore, according to the present invention, in the finally formed MIS type semiconductor device as shown in FIG. 2(b), the second channel region 1
The Vt of one transistor can be greater than the Vt of the transistor in the first channel region.

〔Example〕

Examples of the present invention are shown below.

Regarding the manufacturing method of the present invention, an n-channel MOS (Me
A description will be given based on an example of a semiconductor device of the tal oxide semiconductor type.

FIGS. 1A to 1G are schematic cross-sectional views showing the main steps of the present manufacturing method. In the figure, 1 is a silicon substrate, 2 is S
3 is a silicon film, 4 is a Si/N4 film, 5 is a photoresist film, 6 is a boron-diffused polysilicon film, 7 is a gate 5in2 film, and 8 is a gate electrode.

First, as shown in FIG. 1(a), an SL and N4 film 4 is formed on a silicon film 3 laminated on a silicon substrate 1, and then a photoresist film 5 is applied, and the element area is coated with a photoresist film 5 by normal exposure and development steps. A photoresist film pattern corresponding to the pattern is formed. Here, 5in2 film 2, Si.

N4 film 4 is made by CVD method, each +500 people, 100
Form 0 people. Moreover, the silicon film 3 is formed by CVD method.
This is formed into a single crystal by laser annealing.

Further, the film thickness of the photoresist film 5 is 1.0. It is.

Next, as shown in FIG. 1(b), the lower layer 5L3N, film 4 and silicon film 3 are etched using the photoresist film 5 as a mask. Here, dry etching using CF4 gas is used for etching.

Next, as shown in FIG. 1(c), after the photoresist film 5 is peeled off, a polysilicon film 6 in which boron is diffused is formed on the surface. Here, the polysilicon film 6 is formed by forming a 500% linon-doped polysilicon film by the CVD method, and then diffusing boron to a sheet resistance of 20Ω/hole. Further, Si3N4[4 serves as a mask to prevent impurities such as boron from diffusing into the upper part of the element region.

Next, as shown in FIG. 1(d), the polysilicon film 6 on the surface is etched to leave the polysilicon film 6 in which boron is diffused at a high concentration only on the side walls of the silicon film 3. Here, the polysilicon film 6 is etched using dry etching using CF4 gas, which etches in a direction perpendicular to the substrate.

Furthermore, as shown in FIG. 1(e), a portion of the silicon film 3 and polysilicon film 6 is thermally oxidized. At this time, 5
The L3N4 film 4 prevents the upper part of the element region from being oxidized,
As a result, the oxide film 2' is formed only on the side surfaces of the element region. The oxide film thickness is 400.

Finally, as shown in FIG. 1, after the Si and N4 films 4 are removed by etching, patterns of a gate 5in2 film 7 and a gate electrode 8 are formed. Here, the gate SiO2 film 7
is formed by thermal oxidation. Further, the gate electrode 8 is a polysilicon electrode, and after 5,000 layers are formed by the CVD method, it is patterned by an exposure and development process using a photoresist film and an etching process using the photoresist film as a mask.

As described above, a polysilicon film 6 in which boron is diffused at a high concentration and a thick oxide film 2' are formed only on the side walls of the element region of an MO5 type semiconductor device having an SOI structure, thereby forming a thick oxide film 2' as shown in FIG.
As shown in b), the second
The effect of the transistor on the sidewall is eliminated by making the Vt of the transistor in the first channel region larger than the Vt of the transistor in the first channel region.

In this way, problems such as a decrease in Vt, an increase in variation, and an increase in leakage current due to sidewall transistors are solved. Furthermore, the present invention is effective in reducing disconnections in aluminum wiring layers, etc., since the step difference in the element region is alleviated by forming the polysilicon film 6 on the side walls of the element region.

In the above embodiments, the present invention was explained using an SOI structure n-channel MOS semiconductor device in which a 5in2 film and a silicon film were formed on a silicon substrate, but other SOI structure M
It is obvious that the present invention can also be applied to IS type semiconductor devices. Therefore, the SOI structure substrate may be a SOI structure substrate in which a semiconductor film is formed on another insulating substrate such as a quartz substrate. Also S
Although the L and N films were formed by CVD, thermal nitride films may also be used. In addition, C
Although dry etching using F4 gas was used, other etching methods may be used. In addition, a polysilicon film in which boron is diffused is used as the semiconductor film left on the side walls of the element region, but in the case of an n-channel, a semiconductor film in which other p-type impurities are diffused or a p-type semiconductor film is used.
In the case of a channel, a semiconductor film in which n-type impurities such as phosphorus are diffused may be used. Although dry etching using CF or gas was used to etch the boron-diffused polysilicon, any other etching method that etches in a direction perpendicular to the substrate may be used.

〔Effect of the invention〕

As explained above, according to the present invention, MI of SOI structure
In an S-type semiconductor device, the Vt of the transistor corresponding to the sidewall of the element region is equal to the Vt of the transistor above the element region.
It can be made larger than t, there is no variation, and according to the present invention, by forming a semiconductor film on the sidewalls of the element region, it is possible to reduce the step difference in the element region.

[Brief explanation of drawings]

Figure 1 (a), (b), (c), (d)
, (e) and (f) are schematic cross-sectional views of an n-channel MO3 type semiconductor device with an SOI structure showing the process order for explaining an embodiment of the present invention, and FIG.
A schematic cross-sectional view of an NIS type semiconductor device with the structure (b) is (
It is a BB sectional view of a). 1... Relicon board 2... SiS1021
I...Silicon film 4...Sia N4
Film 5...Photoresist film 6...Polysilicon film with boron diffused 7...Gate 5in2 film 8...Gate electrode 9...Source/drain diffusion layer in silicon film 10...No. 1 channel region 11...λth channel region (Q,'
) (b) (C) Figure 1 (d) (e) (f) Figure 1 (α) (b') Figure 2 procedural amendment (voluntary) Date e3.5.18, Showa lcM t ,,,,・1, Indication of the case 1988 Patent Application No. 0732502, Name of the invention Method for manufacturing MIS type semiconductor device 3, Person making the amendment Relationship to the case Applicant Shibago, Minato-ku, Tokyo Chome 33-1 No. 423 NEC Corporation Representative Tadahiro Sekimoto 4, Agent 5, Detailed explanation of the invention column 6 of the specification subject to amendment, Contents of amendment (1) Specification, page 2, 14 From line to line 18 r 1982 Symposium...Papers
) J and r 1982 International Electron Device Meeting Technical Digest,
(1982 International Elect
ron Devices Meeting Techn.
icalDigest) J and Shinichi Masaru6・
,+:', ,-,Representative Patent Attorney Susumu Uchihara,;,・,,,,=ノ＼,-1l

Claims (1)

[Claims] (1) A Si_3N_4 film is formed on the first semiconductor film on the insulating substrate in the element region separation step in the manufacturing process of the MIS type semiconductor device on the insulating substrate, and then a photoresist film is exposed and developed. After forming a photoresist pattern corresponding to the element region, using this as a mask, the Si_3N_4 film and the semiconductor film are etched, and after peeling off the photoresist film, impurities of the first conductivity type are diffused to form a second conductivity type. After forming a semiconductor film and etching it to leave the second semiconductor film on at least a side wall of the first semiconductor film to create an element region made of the first and second semiconductor films, thermal oxidation is performed. A method for manufacturing an MIS type semiconductor device, characterized in that a thick oxide film is formed only on the sidewalls of the element region, and then the Si_3N_4 film on the first semiconductor film is removed by etching.