JPS63237574A - Manufacture of mis semiconductor device - Google Patents

Abstract

PURPOSE:To make Vt of a transistor corresponding to the side wall of an element region larger than Vt of a transistor above the element region by forming a semiconductor film doped with a high concentration impurity which is the same impurity as that contained in a substrate on the side wall of the element region only. CONSTITUTION:With a photoresist film 5 as a mask, an Si3N4 film 4 and a silicon film 3 below the photoresist film 5 are etched. After the photoresist film 5 is removed, a polycrystalline silicon film 6 doped with high concentration boron is formed over the surface. The polycrystalline silicon film 6 is etched to leave the polycrystalline silicon film 6 doped with high concentration boron on the side wall of the silicon film 3 only. Then the Si3N4 film is removed by etching. With this constitution, Vt of a 2nd channel region transistor corresponding to the side wall of the element region can be made to be larger than Vt of a 1st channel region transistor to eliminate the influence of the side wall transistor so that the increase of degradation and variation of Vt and the increase of a leakage current caused by the side wall transistor can be avoided.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method of manufacturing an elbow S-type semiconductor device.

[Conventional technology]

MIS type semiconductor device formed on a semiconductor film on an insulating film, so-called SOI (Semiconductor on I)
MIS type semiconductor devices with n5ulator) structure have smaller junction capacitance than conventional MIS type semiconductor devices, and element isolation is complete and simple, making them suitable for high-speed large-scale integrated circuits (LSIs). It is said that

Conventionally, in the manufacturing process of a MIS type semiconductor device having an SOI structure, one of the element isolation methods is a process of removing all unnecessary portions of a semiconductor film on an insulator to form the semiconductor film in an island shape. For example, S.D.Malhi et al. 1982 Symposium on Technical Papers (1982S
Symposium on VLSI Technology
geyDigest of Technical Pa
pers), page 107 describes this method (island method).
is reported. FIG. 2(a) is a schematic cross-sectional view of an MIS type semiconductor device having an SOI structure in which element isolation is performed using this island method. Figure 2 (11) is B- in Figure 2 (a).
There are 8 cut surfaces. In the figure, 1 is a silicon substrate, 2 is a Si
7 is a gate SiO□ film, 8 is a gate electrode, 9 is a source/drain diffusion layer in the silicon film, 10 is a first channel region, and 11 is a second channel region.

[Problem that the invention seeks to solve]

However, the SO structure M
In the case of an IS type semiconductor device, in addition to the usual first channel region 10 on a silicon film, as shown in FIG.
A second channel region 11 is formed on the sidewall of the membrane. This channel region 11 is the first MIS of the channel region 10.
This can be considered as a channel region of a second MIS type semiconductor device coupled in parallel to the MIS type semiconductor device. Therefore, in the second channel region 11 as well as in the first channel region 10, there is a voltage applied to the gate electrode 7 (threshold voltage, Vt) at which a current begins to flow between the source and drain.

Therefore, 1Vti of the first MIS type semiconductor device and the second
The relationship between the MIS type semiconductor device and 1vttl is lvt,
When L<lVt 1, MIS type semiconductor device/
The Vt of the SOI becomes higher than the Vt2 of the second MIS type semiconductor device. However, in general, Vt depends on the gate film thickness, impurity concentration and crystallinity of the channel region, and in the second MIS type semiconductor device where these are difficult to control, Vt2
very difficult to control. Therefore, IVt, I<
In the case of lvt process 1, the Vt of the MIS type semiconductor device/SOI is the Vt□ of the first MIS type semiconductor device that is the purpose of fabrication.
This results in a further decrease and an increase in dispersion.

The purpose of the present invention is to solve the above-mentioned problems of the conventional SOI
An object of the present invention is to provide a method for manufacturing an MIS type semiconductor device having a structure.

[Means for solving problems]

The gist of the present invention is to form a Si and N4 film on a first semiconductor film on an insulator substrate in the element region isolation step in the manufacturing process of a MIS type semiconductor device on an insulator substrate, and then to form a Exposure of resist film.

After forming a photoresist pattern corresponding to the element region through a developing process, the Si3N
After etching the photoresist film and the semiconductor film, and then peeling off the photoresist film, etching the first conductivity type film to leave the second semiconductor film on at least the sidewall of the first semiconductor film, and then removing the photoresist film. Si, N4 on the semiconductor film of 1
This is a method for manufacturing an MIS type semiconductor device characterized by removing a film by etching.

[Principle/effect]

Generally, the threshold voltage Vt of a MIS type semiconductor device is Si-
Assuming that the interface level of the 5in2 interface is small.

Here, VFR is the flat band voltage, VB is the Fermi level of Si, Ks and Ki are the relative permittivity of silicon and silicon oxide film, respectively, and ε. is the dielectric constant, q is the electron charge 3N^ is the density of acceptor impurity per unit volume, C
1 is the capacitance per unit area of the gate oxide film, and d is the thickness of the gate oxide film.

As can be seen from the above equation, it increases in proportion to the square root of the concentration of the MIS type semiconductor device. The device region isolation method of the present invention is characterized in that a semiconductor film containing a high concentration of the same impurity as the substrate impurity is formed only on the sidewalls of the device region.

Therefore, according to the present invention, in the finally formed MIS type semiconductor device as shown in FIG. 2(b), the Vt of the transistor in the second channel region 11 is made larger than the Vt of the transistor in the first channel region. can do.

〔Example〕

Examples of the present invention are shown below.

Regarding the manufacturing method of the present invention, Siowl on a silicon substrate
An n-channel MOS (Met
A description will be given based on an example of an (Al Oxide Sem1 conductor) type semiconductor device.

FIGS. 1(a) to 1(e) are schematic cross-sectional views showing the main steps of the present manufacturing method. In the figure, 1 is a silicon substrate, 2 is 5
in2 film, 3 a silicon film, 4 a 5i3N41 film, 5 a photoresist film, 6 a boron-diffused polysilicon film, 7 a gate 5i02[, 8 a gate N, and a pole.

First, as shown in FIG. 1(a), a SiN4 film 4 is formed on a silicon film 3 laminated on a silicon substrate 1, and then a photoresist film 5 is applied. Form a corresponding photoresist film pattern. Here 5in2v42, Si.

The N4 film 4 is formed by the CVO method in 500 and 1000 layers, respectively. In addition, the silicon film 3 is formed with a thickness of 5000 by CVD method.
This is formed into a single crystal by laser annealing. Further, the film thickness of the photoresist film 5 is 1.0 uIn.

Next, as shown in FIG. 1(b), the underlying Si, N4 film 4 and silicon film 3 are etched using the photoresist film 5 as a mask. Here, dry etching using CF4 gas is used for etching.

Next, as shown in FIG. 1(c), after the photoresist film 5 is peeled off, a polysilicon film 6 in which boron is diffused is formed on the surface. Here, the polysilicon film 6 is formed by forming 5,000 non-doped polysilicon films by the CVD method, and then diffusing boron to a sheet resistance of 20Ω/hole. Further, the SL, N, and film 4 serve as a mask to prevent impurities such as boron from diffusing into the upper part of the element region.

Next, as shown in FIG. 1(J), the polysilicon film 6 on the surface is etched to leave the polysilicon film 6 in which boron is diffused at a high concentration only on the side walls of the silicon film 3. Here, the polysilicon film 6 is etched using dry etching using CF4 gas, which etches in a direction perpendicular to the substrate.

Finally, as shown in FIG. 1(e), after the Si, N4 film 4 is removed by etching, patterns of a gate SiO□ film 7 and a gate electrode 8 are formed. Here gate SiO□
Film 7 is formed by thermal oxidation. Further, the gate electrode 8 is a polysilicon electrode, and after 5000 layers are formed by the CVD method, it is patterned by an exposure and development process using a photoresist film, and an etching process using the photoresist film as a mask.

As described above, a polysilicon film 6 in which boron is diffused at a high concentration is formed only on the sidewalls of the element region of an MO5 type semiconductor device having an SOI structure. to eliminate sidewall transistor effects. In this way, problems such as a decrease in Vt, an increase in variation, and an increase in leakage current due to sidewall transistors are solved. Furthermore, the present invention is effective in reducing disconnections in aluminum wiring layers, etc., since the step difference in the element region is alleviated by forming the polysilicon film 6 on the side walls of the element region.

In the above embodiments, the present invention was explained using an SOI structure n-channel MO5 type semiconductor device in which a SiO□ film and a silicon film were formed on a silicon substrate, but other SOI structure M
It is obvious that the present invention can also be applied to IS type semiconductor devices. Therefore, the SOI structure substrate may be an SOI structure substrate in which a semiconductor film is formed on another insulating substrate such as a stone board. Furthermore, although the SL3N4 film was formed by the CVD method, it may also be a thermal nitride film. Although dry etching using CF4 gas was used to etch the SL, N4 film, and silicon film, other etching methods may be used. In addition, a polysilicon film in which boron was diffused was used as the semiconductor film left on the side wall of the element region, but n
In the case of a channel, a semiconductor film in which other p-type impurities are diffused may be used, and in the case of a p-channel, a semiconductor film in which n-type impurities such as phosphorus are diffused may be used. In addition, dry etching using CF4 gas was used to etch polysilicon with boron diffused.
An etching method that etches in a direction perpendicular to other substrates may be used.

〔Effect of the invention〕

As explained above, according to the present invention, MI of SOI structure
In an S-type semiconductor device, the vtt! of the transistor corresponding to the sidewall of the element region! : Vt can be made larger than the Vt of the transistor in the upper part of the element region, and there is no variation, and according to the present invention, by forming a semiconductor film on the side wall of the element region, the step difference in the element region can be reduced. have

[Brief explanation of drawings]

Figure 1 (a), (b), (c), (d)
, (e) is a schematic cross-sectional view of an n-channel MO5 type semiconductor device with an SOI structure showing the process order for explaining an embodiment of the present invention, and FIG. 2(a) is a schematic cross-sectional view of a conventional SOI structure MI semiconductor device.
FIG. 2 is a schematic cross-sectional view of an S-type semiconductor device. (b) is a sectional view taken along the line B-B in (a). 1...Silicon substrate 2...Sin, film 3.
...Silicon film 4...5iiN4 film 5...
・Photoresist film

Claims (1)

[Claims] (1) A Si_3N_4 film is formed on the first semiconductor film on the insulating substrate in the element region separation step in the manufacturing process of the MIS type semiconductor device on the insulating substrate, and then a photoresist film is exposed and developed. After forming a photoresist pattern corresponding to the element region, using this as a mask, the Si_3N_4 film and the semiconductor film are etched, and after peeling off the photoresist film, impurities of the first conductivity type are diffused to form a second conductivity type. forming a semiconductor film, etching it to leave the second semiconductor film on at least the sidewalls of the first semiconductor film, and then etching the second semiconductor film on the first semiconductor film;
A method for manufacturing an MIS type semiconductor device, characterized in that an i_3N_4 film is removed by etching.