JPS62268163A - Mis type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the reproducibility of electrical characteristics by forming a gate electrode to the lower section of a channel section through a gate insulating film and each connecting the gate electrode, source/drain diffusion layers and the channel section to a wiring layer separately. CONSTITUTION:A molybdenum gate electrode 9, a gate SiO2 film 10 and an silicon film 11 are shaped onto a quartz substrate 8 in succession, boron is implanted to the silicon film ll, and a positive type resist film 12 is applied. The back of the quartz substrate 8 is exposed and developed, the positive type resist film 12 is peeled off, an interlayer SiO2 film 13 is formed onto source drain diffusion layers 6, and a negative type resist film 14 is applied. The back of the quartz substrate 8 is exposed and developed, the negative type resist film 14 is peeled off, a polycrystalline silicon film 15 is shaped and boron is implanted, and the polycrystalline silicon film 15 is etched and a channel section 5 and a polycrystalline silicon film 15 are formed onto a channel section 5. Lastly, an inter-layer SiO2 film 13 is shaped, and an aluminum wiring layer 16 pattern is formed. Accordingly, leakage currents are prevented, and electrical characteristics can be realized with excellent reproducibility.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a MIS type semiconductor device and its manufacturing method.

[Conventional technology]

MIS type semiconductor device formed on a semiconductor film on an insulating film, so-called SOI (Semiconductor on')
The MIS type semiconductor device with the In5ulator structure has a smaller junction capacitance than the conventional MIS type semiconductor device, and element isolation is complete and simple, making it a semiconductor device suitable for high-speed large-scale integrated circuits (LSI). It is said that

However, in the case of a MIS type semiconductor device having an SOI structure, since the channel portion cannot be connected to an external electrode, the so-called substrate floating effect adversely affects the electrical characteristics of the MIS type semiconductor device.

As a structure that solved this problem, Malhi et al.
siumon VLSI Technology Di
gest of Technical Paper-rs
) proposes the following method on pages 36 to 37.

As shown in FIG.
This structure has a structure in which a part of the channel portion 5 of the MIS type semiconductor device with the SOI structure formed above is connected to the lower layer semiconductor substrate 22. In the figure, 6 is a source/drain diffusion layer, 3 is a gate insulating film, 2 is a gate electrode, and 7 is a wiring layer. In this way, according to the structure shown in FIG. S, by removing the external electrode from the semiconductor substrate 22, it is possible to create a MIS-type semiconductor device in which the channel portion 5 is connected to the external electrode, although it is basically an MIS-type semiconductor device with an SOI structure. Can be formed.

[Problem that the invention seeks to solve]

However, when using such a structure, the substrate 22
must be a semiconductor substrate of the same conductivity type as the channel portion 5. Therefore, according to this structure, a CMIS (Comp
The semiconductor device with the elementary MIS) configuration is the fourth
It will look like the figure. In the figure, 18 is a first conductivity type (n type or p type) MIS type semiconductor device, 19 is a second conductivity type (p type or n type) MIS type semiconductor device, and 20 is a second conductivity type semiconductor diffusion. Layer 21 is a semiconductor substrate of a first conductivity type. Here, the second conductivity type semi-quaternary diffusion layer 20 is a conventional CMI
It is the same as the diffusion layer called n-well or p-well in an S-configuration MIS type semiconductor device, and in this structure, the first
The substrates of the conductive MIS type semiconductor device are connected via a pn junction.

Further, referring to FIG. 5, since there is a semiconductor substrate below the source/drain diffusion layer 6 of each 1S type semiconductor device which is maintained at a certain potential through the interlayer insulating film 4, the source/drain diffusion layer 6 of each 1S type semiconductor device is
Drain diffusion layer 6 has parasitic capacitance. Although this structure allows formation of a MIS type semiconductor device with an SOI structure in which the channel portion 5 is connected to an external electrode, there are problems such as incomplete element isolation and parasitic capacitance under the source/drain diffusion layer. A point occurs.

The object of the present invention is to solve the above-mentioned conventional problems by
An object of the present invention is to provide a structure of an MIS type semiconductor device having an I structure and a manufacturing method thereof.

[Means for solving problems]

The gist of the present invention is to provide a MIS type semiconductor device formed on an insulating substrate, which has a gate electrode under a channel part via a gate insulating film, and connects the gate electrode, source/drain diffusion layer, and channel. MIS type semiconductor device characterized in that the channel parts are connected to wiring layers independently, and the MIS type semiconductor device has a gate electrode under the channel part.
In a method for manufacturing a type semiconductor device, a gate electrode pattern, a gate insulating film, and a semiconductor film pattern containing a first conductivity type impurity are sequentially formed on an insulating substrate, and a positive resist is applied thereon. and exposing and developing the positive resist from the back side of the insulating substrate with light having a wavelength that passes through at least the insulating substrate, the gate insulating film, and the semiconductor film, but does not pass through the gate electrode. forming a source/drain diffusion layer by forming a pattern and ion-implanting a second conductivity type impurity into the semiconductor film using the pattern of the positive resist as a mask; and after peeling off the positive resist. forming an insulating film and then applying a negative resist;
A pattern is formed on the negative resist by exposing and developing the insulating substrate from the back surface with light that passes through at least the insulating substrate, the gate insulating film, the semiconductor film, and the insulating film, but does not pass through the gate electrode. and then etching the insulating film using the negative resist pattern as a mask until the channel portion of the semiconductor film is exposed, and removing impurities contained in the channel portion after peeling off the negative resist. A process of forming a semiconductor film pattern containing impurities of the same conductivity type on the exposed channel part, and after forming an insulating film, forming a semiconductor film pattern on the gate electrode, the source/drain diffusion layer, and the semiconductor film in contact with the channel part, respectively. This is a method of manufacturing an MIS type semiconductor device, characterized by performing a step of forming independently connected wiring layers.

[Principle/effect]

FIGS. 1(a) and 1(b) show schematic cross-sectional views of a MIS type semiconductor device according to the present invention. Figure 1(b) is the same as Figure 1(b).
FIG. 3 is a schematic cross-sectional view taken along the line BB in a).

In the figure, 1 is an insulator substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is an interlayer insulating film, 5 is a channel part, and 6 is a source
7 is a drain diffusion layer and a wiring layer.

A feature of the MIS type semiconductor device according to the present invention is that although it is a MIS type semiconductor device having an SOI structure, the wiring layer 7 can be independently connected to the gate electrode 2, the source/drain diffusion M6, and the channel portion 5. According to this structure, CMIS
Even if the semiconductor device has this structure, the problems of the conventional structure shown in FIG. 4 do not occur.

That is, according to the structure of the present invention, since the substrate is an insulating substrate 1 as shown in FIG. 1, each MIS type semiconductor device can be completely isolated, and there is no parasitic capacitance under the source/drain diffusion layer 6. . Further, according to this structure, there is no need to form the second conductive type semiconductor diffusion layer 20 unlike the conventional structure shown in FIG. 4, so that the degree of integration is improved.

Note that the gate electrode 2 may be made of either a semiconductor or a high melting point metal. Furthermore, the gate insulating film 3 and the interlayer insulation film 4 are CV
Any of the SiO□ film, Si, N4 film, thermal 5in2 film, thermal Si, N4 film formed by the D method may be used.

Further, the wiring layer 7 may be either a semiconductor or a metal.

By the way, when attempting to manufacture the structure of the MIS type semiconductor device according to the present invention using the conventional method, the following problems arise. The problem is shown in Figure 3(a).

This will be explained using the schematic cross-sectional view in (b).

In the figure, 1 to 7 are the same as the constituent parts 1 to 7 in FIG. 1, and 17 is a contact diffusion layer in the channel portion.

The manufacturing process using the conventional method is as follows. That is, as shown in FIG. 3(a), first the insulator substrate 1 is
A gate electrode 2, a gate insulating film 3, and a semiconductor film are formed on top, and then a channel part 5 and a source/drain diffusion layer 6 are formed in the semiconductor film by an exposure/development process using a resist and an impurity ion implantation process. . Next, the channel part 5
After forming a contact diffusion layer 17 for the channel portion containing a high concentration of impurities of the same conductivity type as the channel portion 5, and then forming an interlayer insulating film 4, the gate electrode 2 and the source/drain diffusion M! Contact diffusion layer 17 of J6 and channel portion 5
Wiring layers 7 are formed which are independently connected to each other. Here, the contact diffusion layer 17 in the channel portion is formed to obtain an ohmic connection between the channel portion 5 containing a low concentration of impurity and the wiring layer 7. The contact diffusion layer 17 in this channel portion must not be in contact with the source/drain diffusion layer 6.

This is because when the contact diffusion layer 17 in the channel part and the source/drain diffusion layer 6 come into contact, a pn junction containing high concentration of n-type and n-type impurities is formed at the contact surface, and the source/drain
From the drain diffusion layer 6 to the contact diffusion layer 1 in the channel part
This is because it causes a leakage flow to 7. However, as the MIS type semiconductor device is miniaturized and the gate length becomes shorter, as shown in FIG. It is impossible to make the contact size between the contact diffusion layer 17 and the source/drain diffusion layer 6 smaller than the width of the contact diffusion layer 17 in the channel portion.

On the other hand, it is generally desirable that the end of the source/drain diffusion layer 6 be located at the end of the gate electrode 2, but when using the conventional manufacturing method, the position of the end of the source/drain diffusion layer 6 is set by an exposure/development process using a resist. Therefore, the accuracy of the position must depend on the mechanical accuracy of the exposure device. Therefore, the position of the end of the source/drain diffusion layer 6 relative to the end of the gate electrode 2 is shifted, and the characteristics of the MIS type semiconductor device are deteriorated. This deterioration of characteristics becomes greater as the gate length becomes shorter. As described above, the conventional manufacturing method is not suitable for manufacturing the MIS type semiconductor device of the present invention.

For this reason, in the present invention, a patterning process is used to form a diffusion layer on the channel part that is ohmically connected to the channel part, and the contact between this diffusion layer and the source/drain diffusion layer is minimized to realize the above structure. It makes it seem possible.

〔Example〕

Examples of the present invention are shown below.

About the manufacturing method of the present invention n-channel MOS (Me
A description will be given based on an example of a semiconductor device of the tal oxide semiconductor type.

Figure 2 (a), (b), (c), (d)
, (e) and (f) are schematic cross-sectional views showing the main steps of the present manufacturing method. In the figure, 5 is a channel part, 6 is a source/drain diffusion layer, 8 is a quartz substrate, 9 is a molybdenum gate electrode, 10 is a gate SiO□ film, 11 is a silicon film, 12 is a positive resist film, 13 is a 5in2 interlayer film,
14 is a negative resist film, 15 is a polycrystalline silicon film, 1
6 is an aluminum wiring layer.

First, as shown in FIG. 2(a), a pattern of a molybdenum gate electrode 9, a gate SiO□ film 10, and a silicon film 11 for the active layer are sequentially formed on a quartz substrate 8, and then boron is applied to the silicon film 11. 5X at 100KeV
After implanting 10"■-2, apply a positive resist @12. Here, the molybdenum gate electrode 9 and the gate 5in2
Membrane 10 has a thickness of 4000 mm by CVD method,
Formed to 400 people. Further, the silicon film 11 has a thickness of 40 mm.
00 people, and is formed by converting a polycrystalline silicon film formed by a CVD method into a single crystal by laser annealing. The positive resist film 12 is made of MP-1400-27 and has a thickness of 1.0-.

Next, as shown in FIG. 2(b), by exposing and developing the quartz substrate 8 from the back side, a pattern of the positive resist film 12 identical to that of the underlying molybdenum gate electrode 9 is formed, and this is then used as a mask. The n+ type source/drain diffusion layer 6 is formed by injecting 5 x 10'' all-2 of phosphorus into the silicon film 11 at 60 KeV.The light source used for exposure here was a 350 W high pressure mercury lamp with a wavelength of Therefore, at this wavelength, sufficient light to expose the positive resist film 12 on the front surface of the substrate passes through the quartz substrate 8, the Goo 1-3iO2 film 10, and the silicon film 11 from the back surface, but the molybdenum The gate electrode 9 does not pass through.In this step, a p-type channel portion 5 is formed in the silicon film 11, separated from the source/drain diffusion layer 6.

Next, as shown in FIG. 2(c), after peeling off the pattern of the positive resist film 12, an interlayer 5in2 film 13 is formed on the source/drain diffusion layer 6, and the negative resist film 1
Apply 4. Here, the interlayer SiO□ film 13 is formed to a thickness of 5000 mm using the CVD method. Further, the negative resist film 14 is OMR-85 and has a thickness of 1.0p.

Next, as shown in FIG. 2(d), by exposing and developing the quartz substrate 8 from the back side, a pattern of the negative resist film 14 is formed which is inverted with respect to the molybdenum gate electrode 9 in the lower layer. Using the pattern as a mask, the underlying interlayer Sin film 13 is etched until the underlying channel portion 5 is exposed.

The light source used for exposure here was a 350 W high pressure mercury lamp, and its wavelength was 4360 mm. At this wavelength, f is reduced.
Similarly to the above, sufficient light to expose the negative resist film 14 on the front surface of the substrate passes through the quartz substrate 8, the gate SiO□ film 10, and the silicon film 11 from the back surface, but does not pass through the molybdenum gate electrode 9.

Next, as shown in FIG. 2(e), after peeling off the negative resist film 14, a polycrystalline silicon film 15 is formed, and 5xto15(1)-2 boron is implanted at 60 KeV. A positive resist film pattern is formed by a normal exposure and development process from the surface of the substrate using a resist and the light source, and then, using this as a mask, the polycrystalline silicon film 15 is etched to form the channel part 5L.
A pattern of a polycrystalline silicon film 15 which is ohmically connected to the polycrystalline silicon film 15 is formed. Here, the polycrystalline silicon film 15 is formed to a thickness of 5000 mm using the CVD method.

Finally, as shown in FIG. 2 (0), after forming the interlayer 5in2 film 13, a positive resist film pattern is formed by the normal exposure and development process in the same manner as described above, and then using this as a mask, the interlayer SiO2 film 13 is formed. □The film 13 is etched to form holes in the contacts 1 for the molybdenum gate electrode 9, the source/drain diffusion layer 6, and the polycrystalline silicon film 15, and then the aluminum wiring layer 16 is formed, and then the usual etching process is performed in the same manner as described above. A positive resist film pattern is formed through an exposure and development process, and then the aluminum wiring layer 16 is formed using this as a mask.
A pattern of the aluminum wiring layer 16 for the molybdenum gate electrode 9, the source/drain diffusion layer 6, and the polycrystalline silicon film 15 is formed by etching. Here, the interlayer 5in2 film 13 has a thickness of 5000 mm and is formed by the CVD method.

Further, the aluminum wiring layer 16 is formed to a thickness of 1 μm by a vapor deposition method.

As described above, according to one aspect of the present invention, in an n-channel MOS type semiconductor device having a gate electrode at the lower part of the channel portion of the present invention, the lower gate electrode end and the source/drain diffusion layer end are located at the same position. It can also be manufactured in such a way as to minimize the contact between the source/drain diffusion layer and the diffusion layer formed to obtain an ohmic connection between the channel portion and the wiring layer.

Further, according to the present invention, a structure in which the source/drain diffusion layer and the channel portion are completely flat as shown in FIG. 1(a) can be manufactured by adding one step to the above embodiment. That is, in FIG. 2(a), after forming the pattern of the molybdenum gate electrode 9 on the stone board 8, the thickness of the molybdenum gate electrode 9 is 1-5.
An in2 film was deposited by the CVD method, and it was planarized by applying a resist with a thickness of 1.51 s, and then a resist and SjO□ were applied until the molybdenum gate electrode was exposed.
Etching is performed under conditions where the etching rate of the pancreas is the same.

Next, Figure 2 (a), (b), (c), (
By performing steps similar to d), (e), and (f), a structure in which the source/drain diffusion layer and the channel portion are completely flat can be manufactured.

In this embodiment, a quartz tin plate is used as the substrate, but other insulating substrates may be used. Further, although a molybdenum gate electrode formed by CVD method was used in the gate electron microscope, any other high melting point metal material or semiconductor material formed by CVD method or vapor deposition method may be used. Furthermore, although the SiO□ film formed by the CVD method is used as the gate insulating film, other insulating films such as Si3N film formed by the CVD method may be used. Furthermore, although a silicon film obtained by laser annealing a polycrystalline silicon film formed by a CVD method is used as the semiconductor film, it is also possible to use a silicon film or a polycrystalline silicon film annealed by another method, or another semiconductor film such as GaAs. Also, CVD is applied to the interlayer insulation film.
Although a 5in2 film formed by the CVD method is used, other insulating films such as a 5i1N4 film formed by the CVD method may be used. Further, although a polycrystalline silicon film is used as the material for establishing an ohmic connection between the channel portion and the wiring layer, any other semiconductor film may be used as long as it is a material that can establish an ohmic connection. Further, although an aluminum wiring layer is used as the wiring layer, any other metal or high melting point metal may be used. Further, a positive resist and a negative resist may be used, and the light source used for exposure may be another positive resist, a negative resist, or a light source of another wavelength may be used. Also in this example. Although the explanation has been given using a channel MO3 type semiconductor device as an example, it is also possible to use a p channel MO3 type semiconductor device or a general -I type semiconductor device.
It is clear that the present invention can also be implemented in S-type semiconductor devices.

〔Effect of the invention〕

As described above, according to the MIS type semiconductor device of the present invention, external electrodes can be provided independently in the gate electrode, the source/drain diffusion layer, and the channel region, and element isolation is complete and parasitic This has the effect of making it possible to form a MIS type semiconductor device with an SOI structure without any capacitance. Further, the manufacturing method of the present invention as described above has the effect that the MIS type semiconductor device of the present invention described above can be realized with good reproducibility without causing deterioration of electrical characteristics such as generation of leakage current.

[Brief explanation of drawings]

FIG. 1(a) is a schematic cross-sectional view for explaining a MIS type semiconductor device with an SOI structure according to the present invention, and FIG.
8-11 line sectional view of Figure 2 (a), (b),
(c), (d), (e), and (f) are schematic cross-sectional views showing main steps for explaining an embodiment of the manufacturing method of the present invention for realizing the MIS type semiconductor device of the present invention. , FIGS. 3(a) and 3(b) show the MIS of the present invention.
FIG. 4 is a schematic cross-sectional view for explaining the problems when manufacturing a type semiconductor device by a conventional method, and FIG. FIG. 5 is a schematic cross-sectional view for explaining a conventional MIS type semiconductor device having an improved SOT structure.

Claims (2)

[Claims] (1) In a MIS type semiconductor device formed on an insulating substrate, a gate electrode is provided below a channel part via a gate insulating film, and then the gate electrode, source/drain diffusion layer, and channel part are separated from each other. An MIS type semiconductor device characterized in that the MIS type semiconductor device is connected to a wiring layer. (2) In a method for manufacturing an MIS type semiconductor device having a gate electrode at the bottom of a channel part, a pattern of a gate electrode, a gate insulating film, and a pattern of a semiconductor film containing impurities of a first conductivity type are formed on an insulating substrate. sequentially forming and applying a positive resist thereon, and light having a wavelength that passes through at least the insulator substrate, the gate insulating film, and the semiconductor film from the back side of the insulator substrate, but does not pass through the gate electrode. A pattern is formed in the positive resist by exposure and development, and a source/drain diffusion layer is formed by ion-implanting impurities of a second conductivity type into the semiconductor film using the pattern of the positive resist as a mask. forming an insulating film after peeling off the positive resist, and then applying a negative resist; and removing at least the insulating substrate, the gate insulating film, and the semiconductor film from the back side of the insulating substrate. A pattern is formed in the negative resist by exposing and developing light that passes through the insulating film but does not transmit the gate electrode, and then using the pattern of the negative resist as a mask, the insulating film is exposed to light that does not pass through the gate electrode. a step of etching until the channel portion is exposed; a step of peeling off the negative resist and forming a semiconductor film pattern containing an impurity of the same conductivity type as an impurity contained in the channel portion on the exposed channel portion; After forming an insulating film, a step of forming wiring layers each independently connected to the gate electrode, the source/drain diffusion layer, and the semiconductor film in contact with the channel portion is performed. Production method.