JPH0524658B2 - - Google Patents
Info
- Publication number
- JPH0524658B2 JPH0524658B2 JP58112843A JP11284383A JPH0524658B2 JP H0524658 B2 JPH0524658 B2 JP H0524658B2 JP 58112843 A JP58112843 A JP 58112843A JP 11284383 A JP11284383 A JP 11284383A JP H0524658 B2 JPH0524658 B2 JP H0524658B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- opening
- insulating film
- conductive layer
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims 3
- 238000000151 deposition Methods 0.000 claims 1
- 239000007769 metal material Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 229910052814 silicon oxide Inorganic materials 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 229910017305 Mo—Si Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は、半導体製造技術に係わり、特に電気
的接続をとるためのコンタクトホール形成方法の
改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to semiconductor manufacturing technology, and particularly to improvements in a method for forming contact holes for establishing electrical connections.
近年、半導体装置の小形化及び高集積化がはか
られ、いわゆる集積回路（IC）、大規模集積回路
（LSI）、さらには超LSIが試作開発されるに至つ
ている。半導体装置、特に集積回路の集積密度を
向上させるためには、その回路を構成する素子の
寸法を益々小さくしていく必要がある。このた
め、微細加工技術の進歩にはめざましいものがあ
り、ステツプアンドリピート方式の縮小露光、さ
らには電子線露光方式やＸ線露光方式等の開発が
進んでいる。
In recent years, efforts have been made to make semiconductor devices smaller and more highly integrated, leading to the development of prototypes of so-called integrated circuits (ICs), large-scale integrated circuits (LSIs), and even ultra-LSIs. In order to improve the integration density of semiconductor devices, especially integrated circuits, it is necessary to further reduce the dimensions of the elements constituting the circuits. For this reason, there has been remarkable progress in microfabrication technology, and the development of step-and-repeat reduction exposure, electron beam exposure, X-ray exposure, etc. is progressing.
しかしながら、微細なパターンを正確に形成
し、これを半導体素子構造に置き換えていくこと
は容易ではなく、種々の解決すべき問題が残つて
いる。一例として加工寸法の縮小は、その精度及
び信頼性の意味において重大な困難をもたらして
おり、特に微細な開孔パターン（コンタクトホー
ル）の形成はその形状かいつても最も困難なもの
とされている。すなわち、線幅１〔μｍ〕程度の
溝パターンを解像可能な10：１縮小投影型露光装
置を用いたとしても、装置限界のパターンの解像
は実用上困難であり、特に１回の露光面積を10
〔mm〕×10〔mm〕程度とした場合には露光領域周辺
部における解像度の低下が激しく、実用上使用可
能な開口パターンは大きくなよてしまう。 However, it is not easy to accurately form fine patterns and replace them with semiconductor element structures, and various problems remain to be solved. For example, the reduction of processing dimensions has brought serious difficulties in terms of accuracy and reliability, and in particular, the formation of fine opening patterns (contact holes) is considered to be the most difficult due to its shape. There is. In other words, even if a 10:1 reduction projection type exposure device capable of resolving a groove pattern with a line width of about 1 [μm] is used, it is practically difficult to resolve a pattern that is at the limit of the device, especially in one exposure. area to 10
When the size is about [mm]×10 [mm], the resolution at the periphery of the exposure area is severely degraded, and the aperture pattern that can be used in practice becomes large and fluctuates.
これに対してコンタクト面積を（Photo
Engraving Process）工程で形成したものから減
少させる方法として次のものが知られている。 For this, the contact area (Photo
The following methods are known as methods for reducing the amount formed in the engraving process.
第１図はその方法を示す断面図である。即ち、
半導体基板表面に絶縁層を設け、これを穴開けし
て不純物をイオン注入して逆導電型層を形成す
る。しかる後アニールと同時に基板表面に薄く熱
酸化膜を形成し、全体に多結晶シリコンを堆積し
てイオンエツチングし、開孔の内側にこれを残置
し、アルミニウム配線を設けるものである。 FIG. 1 is a sectional view showing the method. That is,
An insulating layer is provided on the surface of a semiconductor substrate, holes are made in the insulating layer, and impurity ions are implanted to form an opposite conductivity type layer. Thereafter, at the same time as annealing, a thin thermal oxide film is formed on the surface of the substrate, polycrystalline silicon is deposited over the entire surface and ion etched, and this is left inside the opening to provide aluminum wiring.
しかしながらこの方法には次の様な問題があ
る。 However, this method has the following problems.
第１にこの方法をMOS型トランジスタのゲー
トやソース、ドレインコンタクトに適用した場
合、マスク合わせずれにより第１の開孔がゲート
境界を含むようになると前記熱酸化を施しても酸
化速度の相異によりゲート上に存在する絶縁膜端
部、ゲート絶縁膜部でくびれた絶縁膜となるのみ
で多結晶シリコンを介してここでリークし易い。 First, when this method is applied to the gate, source, and drain contacts of a MOS transistor, if the first hole comes to include the gate boundary due to mask misalignment, there will be a difference in the oxidation rate even if the thermal oxidation is performed. This results in a constricted insulating film at the ends of the insulating film existing on the gate and at the gate insulating film portion, where leakage is likely to occur through the polycrystalline silicon.
又、多結晶シリコンを残しておくことによりゲ
ートと、ソース、ドレイン電極間に寄生容量が発
生し、素子特性が低下するという問題がある。従
つて自己整合膜は絶縁膜とする事が望ましい。 Further, by leaving polycrystalline silicon, there is a problem that parasitic capacitance is generated between the gate, source, and drain electrodes, and device characteristics are deteriorated. Therefore, it is desirable that the self-aligned film be an insulating film.
又、第２にコンタクト抵抗ρcが著しく増加して
しまい、動作速度が低下する事である。例えば、
開孔が1μｍ口であればρcは50Ω・cm2程度にすぎな
いが、自己整合膜によつて0.4μｍ口程度になると
一挙に300Ω・cm2に増加してしまう。 Moreover, the second problem is that the contact resistance ρ c increases significantly, and the operating speed decreases. for example,
If the opening is 1 μm, ρ c is only about 50 Ω·cm 2 , but if the opening is about 0.4 μm due to the self-aligned film, it suddenly increases to 300 Ω·cm 2 .
本発明の第１の目的は、セルフアラインコンタ
クトを用いる際の歩留り、素子特性の向上を図る
ことができる半導体装置の製造方法を提供する事
を目的とする。
A first object of the present invention is to provide a method of manufacturing a semiconductor device that can improve yield and device characteristics when using self-aligned contacts.
又、本発明の第２の目的は、セルフアラインコ
ンタクトのコンタクト抵抗を大幅に低下させる事
ができる半導体装置の製造方法を提供する事を目
的とする。 A second object of the present invention is to provide a method for manufacturing a semiconductor device that can significantly reduce the contact resistance of self-aligned contacts.
本発明は、リングラフイによつて開けた開孔下
に予め金属膜をその端部がフイールド絶縁領域上
に延在するまで選択成長させておき、しかる後、
多結晶シリコンに代えて絶縁膜をその内周に異方
性エツチングで残置するようにした事を骨子とす
る。
In the present invention, a metal film is selectively grown in advance under an opening made by a ring graphie until its end extends over a field insulating region, and then,
The main idea is to leave an insulating film on the inner periphery of the polycrystalline silicon by anisotropic etching instead of polycrystalline silicon.
本発明によれば絶縁膜をコンタクト内周に埋め
込むようにしたので、そのマスク合わせがずれて
も隣接するゲートト等導体パターンとのリークが
生ずる事もなくなり、またその結合容量の発生も
防止する事ができる。
According to the present invention, since the insulating film is embedded in the inner periphery of the contact, even if the mask alignment is misaligned, leakage with adjacent conductor patterns such as gates will not occur, and the generation of coupling capacitance can also be prevented. I can do it.
又、コンタクト部においては金属−金属コンタ
クトとなるのでコンタクト抵抗が大幅に低減化さ
れ高動作速度が得られる様になる。さらにまた、
半導体基板に形成した第１の導電層の表面に金属
膜を、その端部がフイールド絶縁領域上に延在す
るまで形成膜厚を増して選択成長させるので、第
１の絶縁層の前記コンタクト部がマスク合わせず
れして形成されてしまう場合でも、該コンタクト
部をエツチングにより形成したり該コンタクト部
内周に異方性エツツチングにより第２の絶縁層を
残置させる際に、前記フイールド絶縁領域がエツ
チングされることを防止することができ、このエ
ツチングによる前記フイールド絶縁領域の素子分
離能力の低下や前記半導体基板の接合端部の露出
を防止することが可能となる。 Further, since the contact portion is a metal-to-metal contact, the contact resistance is significantly reduced and a high operating speed can be obtained. Furthermore,
Since a metal film is selectively grown on the surface of the first conductive layer formed on the semiconductor substrate by increasing the film thickness until the end portion thereof extends over the field insulating region, the contact portion of the first insulating layer Even if the field insulating region is formed by misalignment of the mask, the field insulating region is not etched when forming the contact portion by etching or leaving the second insulating layer on the inner periphery of the contact portion by anisotropic etching. This makes it possible to prevent deterioration of the element isolation ability of the field insulating region and exposure of the junction end of the semiconductor substrate due to this etching.
第２図ａ〜ｄは本発明の一実施例に係わる
MOS型トランジスタ製造工程を示す断面図であ
る。
Figures 2a to 2d relate to one embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a MOS transistor manufacturing process.
まず、第２図ａに示す如く比抵抗５〜50〔Ω−
cm〕のＰ型（100）シリコン基板１を用意し、こ
の基板１の素子分離領域に絶縁膜２を埋め込み形
成した後、MOSFETの絶縁膜を介して、ゲート
電極（図示せず）を形成し、ついで拡散層３をイ
オン注入法により形成した。 First, as shown in Figure 2a, the specific resistance is 5 to 50 [Ω-
cm] P-type (100) silicon substrate 1 is prepared, an insulating film 2 is buried in the element isolation region of this substrate 1, and a gate electrode (not shown) is formed through the insulating film of the MOSFET. Then, a diffusion layer 3 was formed by ion implantation.
次に、第２図ａの後に第２図ｂに示す如く、
WF6ガスを主成分とする気相成長法200〜500
〔℃〕でＷをSi上に選択的に形成する。その場合
第２図ａの工程後、絶縁膜を薄く堆積した後、異
方性ドライエツチングを行ない自己整合的にゲー
ト側壁を覆つておく。選択成長の際、膜厚が薄け
れば拡散層の上のみにＷ膜が形成されるがＷ形成
膜膜厚を増すと酸化膜上にもＷ膜が第２図ｂの如
くのびてくる。続いて第２図ｃに示す如く上記試
料の上面にシリコン酸化膜５を5000〔Å〕低温気
相成長技術を用いて形成した後、この上にレジス
ト６の。この開孔パターンの寸法は必要とするコ
ンタクトホールの寸法より0.6μｍ程度大きい径と
した。続いて、上記レジスト６をマスクとして用
い、シリコン酸化膜５を選択エツチングし該膜５
に開孔を形成した。この時のエツチング技術とし
ては、サイドエツチングの少ない異方性ドライエ
ツチングを用いた。 Next, as shown in Figure 2b after Figure 2a,
Vapor phase growth method with WF6 gas as the main component 200-500
W is selectively formed on Si at [°C]. In that case, after the step shown in FIG. 2a, a thin insulating film is deposited and anisotropic dry etching is performed to cover the gate sidewalls in a self-aligned manner. During selective growth, if the film thickness is thin, the W film is formed only on the diffusion layer, but if the thickness of the W formed film is increased, the W film also extends over the oxide film as shown in FIG. 2b. Subsequently, as shown in FIG. 2c, a silicon oxide film 5 of 5000 Å was formed on the upper surface of the sample using low temperature vapor phase growth technology, and then a resist 6 was formed on this. The dimensions of this opening pattern were approximately 0.6 μm larger than the dimensions of the required contact holes. Next, using the resist 6 as a mask, the silicon oxide film 5 is selectively etched to remove the silicon oxide film 5.
An opening was formed in the hole. As the etching technique at this time, anisotropic dry etching with less side etching was used.
ここで、第３図に示す如く開孔パターン１４が
フイールド上にかかつてもＷ膜４′をのばして形
成することが可能な為、下部のSiやシリコン酸化
膜５がエツチングされないのでコンタクト孔とフ
イールドの重ね合わせ余裕をさらに小さくでき素
子の微細化に有効である。しかも接合端部がエツ
チングで露出する事もない。次いで、レジスト６
を除去した後、試料上面にシリコン酸化膜（第２
の絶縁膜）を減圧気相成長法で3000オングストロ
ーム形成した。 Here, as shown in FIG. 3, since the opening pattern 14 can be formed by extending the W film 4' over the field, the Si or silicon oxide film 5 at the bottom is not etched, so that it can be formed as a contact hole. The overlapping margin of fields can be further reduced, which is effective in miniaturizing elements. Furthermore, the joint ends are not exposed due to etching. Next, resist 6
After removing the silicon oxide film (second
An insulating film of 3000 angstroms was formed by low pressure vapor phase epitaxy.
次に、CF4とH2との混合ガスによるリアクテイ
ブイオンエツチチング法を用い、上記シリコン酸
化膜（第２の絶縁膜）をその膜厚相当分だけ全面
エツチングした。これにより、このシリコン酸化
膜を上記開孔の側壁にのみ残存させることがで
き、該シリコン酸化膜で囲まれる開孔の寸法を必
要とするコンタクトホール寸法と略等しくするこ
とができた。つまり、上記シリコン酸化膜（第２
の絶縁膜）を上記開孔の側壁に0.3μｍ幅程度残す
ことができ、シリコン酸化膜５に予め形成された
開孔の寸法を0.6μｍ程度小さくすることができ
た。 Next, using a reactive ion etching method using a mixed gas of CF 4 and H 2 , the entire surface of the silicon oxide film (second insulating film) was etched by an amount corresponding to its film thickness. Thereby, this silicon oxide film could be left only on the side wall of the opening, and the dimensions of the opening surrounded by the silicon oxide film could be made approximately equal to the dimensions of the required contact hole. In other words, the silicon oxide film (second
(insulating film) with a width of about 0.3 μm on the side wall of the opening, and the size of the opening previously formed in the silicon oxide film 5 could be reduced by about 0.6 μm.
なお、この後上記試料上にAl合金膜を被着し、
このAl合金膜をパターニングすることにより、
ＮチヤネルMOSトランジスタが形成されること
になる。なお本発明は上述した実施例に限定され
るものではない。例えば、第１の絶縁膜はシリコ
ン酸化膜に限るものではく、シリコン窒化膜その
他の絶縁膜で代替できる。同様に第２の絶縁膜と
してはシリコン窒化膜を用いてよいのは、勿論の
ことである。また、第２の導電膜はMo−Si膜、
Ｗ膜に限るものではなく、その他の高融点金属膜
やPt−Si膜でも代替できる。また、第１の絶縁膜
に形成する開孔の寸法は、所望するコンタクトホ
ール寸法及び第２の絶縁膜の残存幅等の条件に応
じて適宜定めればよい。 Note that after this, an Al alloy film was deposited on the above sample,
By patterning this Al alloy film,
An N-channel MOS transistor will be formed. Note that the present invention is not limited to the embodiments described above. For example, the first insulating film is not limited to a silicon oxide film, and may be replaced with a silicon nitride film or other insulating film. Similarly, it goes without saying that a silicon nitride film may be used as the second insulating film. Moreover, the second conductive film is a Mo-Si film,
It is not limited to the W film, and other high melting point metal films or Pt-Si films can be used instead. Further, the dimensions of the opening formed in the first insulating film may be determined as appropriate depending on conditions such as the desired contact hole size and the remaining width of the second insulating film.
以上、本発明は、その要旨を逸脱しない範囲
で、種々変形して実施することができる。 As described above, the present invention can be implemented with various modifications without departing from the gist thereof.
第１図は従来例を説明する断面図、第２図ａ〜
ｄは本発明の実施例に係わるMOSトランジスタ
製造工程を示す断面図、第３図は、本発明の実施
例を説明する平面図である。
図において、１…シリコン基板（半導体基板）、
３，３ａ，３ｂ…拡散層、４′…Ｗ膜（第２の導
電膜）、５…シリコン酸化膜（第１の絶縁膜）、６
…レジスト、１２，１３…Ａ配線膜、１４…開
孔パターン。
Fig. 1 is a sectional view explaining a conventional example, Fig. 2 a~
d is a cross-sectional view showing the manufacturing process of a MOS transistor according to an embodiment of the present invention, and FIG. 3 is a plan view illustrating the embodiment of the present invention. In the figure, 1... silicon substrate (semiconductor substrate),
3, 3a, 3b...diffusion layer, 4'...W film (second conductive film), 5...silicon oxide film (first insulating film), 6
...Resist, 12, 13... A wiring film, 14... Opening pattern.
Claims (1)
隣接するフイールド絶縁領域を形成する工程と、
前記第１の導電層の表面に金属膜を、その端部が
前記フイールド絶縁領域上に延在するまで選択成
長させる工程と、前記金属膜上に開孔部を有する
第１の絶縁層を形成する工程と、前記開孔部を覆
うように第２の絶縁層を被着し、全体を異方性エ
ツチングして前記第２の絶縁層を前記開孔部の内
周に残置させる工程と、この開孔部でコンタクト
する金属材料からなる第２の導電層を形成する工
程とを備えたことを特徴とする半導体装置の製造
方法。1. forming a first conductive layer and a field insulation region adjacent to the conductive layer on a semiconductor substrate;
selectively growing a metal film on the surface of the first conductive layer until an end thereof extends over the field insulation region; and forming a first insulation layer having an opening on the metal film. depositing a second insulating layer so as to cover the opening, and anisotropically etching the entire surface to leave the second insulating layer on the inner periphery of the opening; A method for manufacturing a semiconductor device, comprising the step of forming a second conductive layer made of a metal material that makes contact at the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11284383A JPS605514A (en) | 1983-06-24 | 1983-06-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11284383A JPS605514A (en) | 1983-06-24 | 1983-06-24 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS605514A JPS605514A (en) | 1985-01-12 |
| JPH0524658B2 true JPH0524658B2 (en) | 1993-04-08 |
Family
ID=14596917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11284383A Granted JPS605514A (en) | 1983-06-24 | 1983-06-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS605514A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63190357A (en) * | 1987-02-02 | 1988-08-05 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPH02135584U (en) * | 1989-04-17 | 1990-11-09 | ||
| JPH04127523A (en) * | 1990-09-19 | 1992-04-28 | Nec Corp | Manufacture of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5772321A (en) * | 1980-10-24 | 1982-05-06 | Toshiba Corp | Manufacture of seiconductor device |
| JPS5818965A (en) * | 1981-07-28 | 1983-02-03 | Toshiba Corp | Manufacture of semiconductor device |
-
1983
- 1983-06-24 JP JP11284383A patent/JPS605514A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5772321A (en) * | 1980-10-24 | 1982-05-06 | Toshiba Corp | Manufacture of seiconductor device |
| JPS5818965A (en) * | 1981-07-28 | 1983-02-03 | Toshiba Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS605514A (en) | 1985-01-12 |
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