JPH08130309A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To obtain a semiconductor device which reduces a contact resistance without increasing the junction capacitance of a source region to a drain region. CONSTITUTION: An N-channel MOS transistor is formed. After that, an interlayer insulating film 17 is formed, and a contact hole 21 is opened in a source.drain region. At this time, the surface of a diffusion layer 15 is overetched in a range on the upper side from the junction of the diffusion layer 15. Phosphorus or arsenic ions are implanted into the whole face from the side of the contact hole 21, and an N-type layer 20 is formed at the lower part of the contact hole 21 through the contact hole 21. After that, an electrode interconnection 18 is formed by a known technique.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a contact with an electrode wiring and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the miniaturization of MOS transistors constituting a semiconductor integrated circuit device has progressed, and a so-called deep sub-micron generation has begun to be introduced. Along with this, high integration and high performance of integrated circuits are achieved. It is being promoted more and more. Then, with the miniaturization of the element as described above, the parasitic resistance and the parasitic capacitance of the MOS transistor have become major factors that hinder the improvement of the circuit operation.

Under these circumstances, when the contact hole is formed on the source region and the drain region as shown in FIG. 1 for the purpose of reducing the parasitic resistance of the MOS transistor, the bottom surface of the contact hole is the source region. Alternatively, in order to make the depth deeper than the drain region and prevent leakage from the contact hole to the substrate, impurities of the same conductivity type as the source region and the drain region are tilted at an angle of 15 °.
It has been proposed to form a high-concentration impurity region on the side and bottom surfaces of a contact hole by oblique ion implantation (June 11-12, 1991 VMIC Conference, pp. 209-
212).

In FIG. 1, 1 is a diffusion region for source / drain, 1'is a diffusion region formed by oblique ion implantation, 2 is an AlSi electrode wiring, 3 is a TiN barrier layer, and 4 is a contact hole. The tungsten layers 5 are SiO ₂ interlayer insulating films. The depth of the diffusion region 1 is about 0.1
μm, the contact hole is 0.2-0.4μ
It is dug deep.

[0005]

The proposed contact shown in FIG. 1 is expected to have the effect of reducing the contact resistance by increasing the contact area. However, in FIG. 1, since the contact hole is dug deeper than the junction position of the source / drain diffusion region and the diffusion region is formed in the contact hole, the junction area of the diffusion region also increases at the same time and the junction capacitance is increased. Increase.
Parasitic capacitance, particularly junction capacitance of the drain diffusion layer, has a significant influence on circuit operation (see Technical Report SDM92-137 of the Institute of Electronics, Information and Communication Engineers). When reducing the parasitic resistance, it is important to consider not to increase the parasitic capacitance.

It is an object of the present invention to provide a MOS type semiconductor device and a method of manufacturing the same which can improve the circuit operation by reducing the contact resistance without increasing the junction capacitance of the source region and the drain region. It is what

[0007]

According to the first aspect of the MOS semiconductor device of the present invention, the bottom surface of the contact hole does not include a plane having the same height as the surface of the substrate and includes a region other than the source region and the drain region. I'm out. In a second aspect of the MOS type semiconductor device of the present invention, the bottom surface of the contact hole is below a plane flush with the substrate surface, and the junction position between the source region or the drain region and the substrate semiconductor portion existing therebelow. Located on top. In this case, it is preferable that the impurity concentration of the bottom surface of the contact hole is higher than the impurity concentrations of the source region and the drain region.
In either case, the area of the bottom surface of the contact hole is increased and the contact resistance is reduced. However, the junction capacitance does not increase.

A first aspect of the method of manufacturing a semiconductor device of the present invention includes the following steps for forming a contact with an electrode wiring. (A) a step of depositing an interlayer insulating film on the entire surface of the substrate from above the gate electrode, (B) setting a contact hole region in a region extending over the source region and the isolation insulating film, and a region extending over the drain region and the isolation insulating film,
A step of forming a contact hole by selectively etching the interlayer insulating film in the contact hole region and exposing the substrate in the source region and the drain region and the substrate under the isolation insulating film, (C) through the contact hole A step of ion-implanting an impurity of the same conductivity type as that of the source region and the drain region into the substrate, (D) and then forming an electrode wiring connected to the source region or the drain region through the contact hole.

A second aspect of the method for manufacturing a semiconductor device of the present invention includes the following steps for forming a contact with an electrode wiring. (A) a step of depositing an interlayer insulating film on the entire surface of the substrate from above the gate electrode, (B) setting a contact hole region in the source region and drain region, and selectively etching the interlayer insulating film in the contact hole region, and A step of forming a contact hole by etching to a position below a junction of a source region or a drain region and a substrate semiconductor existing below each of the source region or the drain region below the surface of the substrate, and (C) through the contact hole Forming an electrode wiring connected to the region or the drain region. In the second aspect of the manufacturing method, it is preferable that a step of ion-implanting an impurity of the same conductivity type as the source region and the drain region into the substrate through the contact hole is provided between the steps (B) and (C).

[0010]

FIG. 2 shows an embodiment corresponding to claim 1 together with a method corresponding to claim 4 which is a manufacturing method thereof. (A) An N-channel MOS transistor is formed in the active region. P on the surface of the silicon substrate 11
The well 12 is formed, and in the active region separated by the field oxide film 16 in the well 12, a gate electrode 14 made of phosphorus-doped polycrystalline silicon is formed on the channel region through the gate oxide film 13. ing. On the surface of the well 12, a source region and a drain region 15 made of an N ⁺ diffusion layer are formed across the channel region. The "well surface" in this example is one aspect of the "substrate surface". The well is sometimes used synonymously with the substrate.

To form the MOS transistor in this state, the P-type well 12 is formed on the surface of the P-type silicon substrate 11 by a known technique, and the selective oxidation method (LOCOS) is used.
The active region is separated by a thick thermal oxide film (field oxide film) 16 having a thickness of 4500 to 6000Å formed by the method). A thermal oxide film 13 to be a gate oxide film having a thickness of 100 to 150Å is formed on the active region, and a thickness of about 35 is further formed on the thermal oxide film 13.
A polycrystalline silicon film 14 of 00Å is formed. The polycrystalline silicon film 14 is finally in a state of being doped with phosphorus. The polycrystalline silicon film 14 may be formed by forming a polycrystalline silicon film not doped with impurities and then introducing phosphorus by a diffusion method or an ion implantation method, or a polycrystalline silicon film by a CVD method. It is also possible that phosphorus is introduced into the reaction gas when depositing, and a phosphorus-doped polycrystalline silicon film is formed in the deposited state. Finally, the phosphorus-doped polycrystalline silicon film 14 is patterned into a gate electrode shape by lithography and etching.

In the active region, the channel region 1 is formed by implanting N-type impurities using the gate electrode as a mask.
A source region and a drain region 15 of the N ⁺ type layer formed by sandwiching 9 are formed. The N ⁺ type layer 15 can be formed, for example, by implanting arsenic ions under the conditions of a dose amount of 6 × 10 ¹⁵ / cm ² and an implantation energy of 50 KeV and performing a heat treatment at 850 ° C. for 20 minutes. A diffusion layer with a depth of about 0.15 μm is obtained.

(B) Next, CV is formed on the entire surface from above the gate electrode.
NSG film of about 3000 Å (silicon oxide film not doped with impurities) by D method, and 50
The interlayer insulating film 17 is formed by depositing a BPSG film (boron phosphorus silicon glass film) of about 00Å. Contact holes 21 are formed in the interlayer insulating film 17 on the source region and the drain region by lithography and etching.

At this time, as shown in the enlarged sectional view (b) of the contact hole portion, the contact hole 2
1 is set so that the region where 1 is opened extends over the source / drain diffusion region 15 and the end of the field oxide film 16, and the thermal oxide film 16 ′ existing at the bottom of the contact hole is over-etched by several tens of percent. Is removed and the surface of the silicon substrate underneath is exposed. The amount of over-etching is based on the amount of just-etching of the interlayer insulating film for forming the contact hole, and a numerical value indicates what percentage of the amount is over-etching. The amount of overetch is, for example, a contact hole diameter of 0.4 μm.
When the aspect ratio (depth / diameter of the contact hole) of the contact hole is about 2, it is appropriate to set it to about 50%.

(C) After that, phosphorus or arsenic is ion-implanted into the entire surface of the substrate surface. As a result, the N-type layer 2 is formed below the contact hole 21 through the contact hole 21.
0 is formed. As the implantation impurity, if it is desired not to heat much in the subsequent process, it is preferable to select phosphorus that can be activated at a lower temperature than arsenic, but under the same implantation energy, phosphorus has a larger projection range than arsenic. Therefore, it is necessary to adjust the implantation energy. For example, the N-type layer 20
If it is desired to make the impurity distribution of the same as that of the N ⁺ type layer 15, the implantation energy of phosphorus may be set to about 30 KeV. In order to suppress the junction capacitance in the N-type layer 20 below the contact hole 21, it is preferable to control the impurity distribution so as to be deep and gentle. However, the implantation and activation conditions may be set together with other requirements. . After that, the electrode wiring 18 is formed by a known technique.

The M of FIG. 2C formed in this way
In the OS transistor, the field oxide film in the contact hole is completely removed at the bottom surface of the contact hole to expose the surface of the well 12 therebelow, and the surface height of the source / drain region is also high. It is lower than the height of the original substrate surface (the surface of the well 12 in this embodiment). Further, since the field oxide film is removed, there is a step in the bottom surface of the contact hole. Therefore, the contact area is increased as compared with the conventional case where the contact hole is formed only on the diffusion region, and each contact hole is The contact resistance of is reduced.

In addition, since the N-type layer 20 due to the impurities injected through the contact hole is present at the bottom of the contact hole, it is possible to prevent the leak from the electrode wiring 18 to the substrates 12 and 11, and to some extent to prevent misalignment. You can give a margin of.

Since the contact hole extends to the outside of the source / drain diffusion region 15, the effective diffusion region expands accordingly, but the layout rule regarding the distance from the end of the contact hole to the end of the gate electrode is changed. If not, the area of the diffusion region can be reduced as a whole, so that the overall junction capacitance is reduced.

FIG. 3 shows the effect of reducing the area of this diffusion region. When the conventional MOS transistor and the MOS transistor to which the present invention is applied are created according to the respective layout rules, the diffusion region in the gate width direction is not reduced so as to have the same gate width, but the diffusion region 15 according to the conventional layout rule is used. It can be seen that the area of the diffusion region 15 is considerably reduced because the boundary between the diffusion region 15 and the field oxide film in the layout rule applied to the present invention is set at a position crossing the contact hole, as compared with “.

In the embodiment of FIG. 2, an example of a thick thermal oxide film formed by a selective oxidation method is shown as an insulating film for isolating an active region, but a semiconductor substrate is used as an insulating film for isolating an active region. Any material or any method may be used as long as the contact surface shape with and has a step with respect to the plane of the diffusion region surface. For example, selective oxidation is performed by using a conventionally used nitride film as a mask. Other than the above LOCOS method, various improved LOCOS methods or trench isolation methods may be used. It goes without saying that the effects shown in the embodiment of FIG. 2 can be obtained by applying a predetermined etching condition to the insulating films when opening the contact holes.

FIG. 4 shows an embodiment corresponding to claim 2 together with a manufacturing method corresponding to claim 5 which is a manufacturing method thereof. The same reference numerals are used for the portions corresponding to the respective portions in the embodiment of FIG. (A) The state in which the N-channel MOS transistor is formed is the same as that of the embodiment of FIG. However, here, the diffusion layer 15 in the source / drain region is formed to a depth of about 0.3 μm. Therefore, the ion implantation conditions for forming the diffusion layer 15 are the same as in the embodiment of FIG. 2 with arsenic ions at a dose of 6 × 10 ¹⁵ / cm ² and an implantation energy of 50K.
eV, but the heat treatment condition thereafter is 900 ° C. for 60 minutes to form a diffusion layer 15 deeper than that in the embodiment of FIG.

(B) Similar to the embodiment of FIG. 2, an interlayer insulating film 17 is formed and a contact hole 21 is opened by photolithography and etching. In this embodiment, the position where the contact hole 21 is opened is only on the diffusion region 15, and is 0.3 μm from the end of the field oxide film 16.
It has a margin M1 and the bottom of the contact hole is 0.1 to the junction position between the diffusion layer 15 and the well 12.
The contact hole is different in position and depth from the contact hole in FIG. 2 in that the surface of the diffusion layer 15 is removed by overetching so that it exists in the diffusion layer 15 with a margin M2 of 5 μm or more.

(B) is an enlarged view of the contact hole portion of (B), showing the surface portion 1 of the diffusion layer 15.
5'is removed, and yet the diffusion layer 15 remains at the bottom of the contact hole with a margin M2 of 0.15 μm or more. The contact hole is formed in the diffusion layer 15 so as to have a margin of 0.15 μm or more in order to secure reliability such as leak resistance.

When the depth of the diffusion layer 15 is about 0.3 μm,
In order to leave a margin M2 of 15 μm or more, the surface of the diffusion layer may be etched by about 0.1 μm. As for this etching method, if it is attempted to perform overetching as it is under the etching conditions of the interlayer insulating film 17, 2
Since an over-etch amount of about 00% is required and the operating rate of the etching apparatus is reduced, the interlayer insulating film 17
Is selectively etched to form a contact hole reaching the surface of the diffusion layer 15, and then the surface of the diffusion layer 15 may be removed by changing the flow rate ratio of the etching gas.

(C) Thereafter, the electrode wiring 18 is formed by a known technique. MO obtained in the example of FIG.
In the S transistor (C), the contact area is increased as compared with the case where the position of the bottom surface of the contact hole is formed on the diffusion region plane as in the conventional case.
The contact resistance per piece can be reduced. Moreover, there is some margin from the bottom surface of the contact hole to the junction position between the diffusion layer and the well, and leakage from the electrode wiring to the semiconductor substrate is suppressed.

In the embodiment of FIG. 4, when the depth of the diffusion region is deep and a large margin can be secured from the bottom surface of the contact hole to the junction surface between the diffusion region and the semiconductor substrate, for example, as in the embodiment, there is a margin in the N ⁺ diffusion region. Is particularly effective when it is 0.15 μm or more, and there is an advantage that the conventional manufacturing process can be used as it is.

FIG. 5 shows an embodiment of claim 3 together with a manufacturing method corresponding to claim 6. (A) The state in which the N-channel MOS transistor is formed is the same as that of the embodiment of FIG. (B) Similar to the embodiment of FIG. 4, the interlayer insulating film 17 is formed, and the contact hole 21 is opened by photolithography and etching.

(C) Phosphorus or arsenic is ion-implanted over the entire surface from the contact hole side to form the N-type layer 20 below the contact hole 21 through the contact hole 21. As the implantation impurity, phosphorus, which can be activated at a temperature lower than that of arsenic, may be selected as in the embodiment of FIG. After that, thereafter, the electrode wiring 18 is formed by a known technique.

In the embodiment shown in FIG. 5, since the N-type layer 20 injected through the contact hole exists at the bottom of the contact hole, it is possible to prevent the leak from the electrode wiring 18 to the well 12 and to prevent misalignment to some extent. You can give a margin. Even if the contact hole 21 is formed deviating to the side of the field oxide film 16 and a part of the field oxide film 16 is removed by etching when forming the contact hole and the well 12 is exposed beyond the source / drain region 15, the contact Since the diffusion layer 20 is formed by ion implantation through the holes, leakage into the well 12 is suppressed.

In this embodiment, the depth of the diffusion region 15 is shallow,
If there is not enough room from the bottom surface of the contact hole to the joint surface between the diffusion region 15 and the well 12, for example, N ⁺
It is particularly effective when the margin in the diffusion region 15 is 0.15 μm or less.

In the MOS transistor of FIG. 5C, the N-type layer 2 is provided only under the contact hole.
Although 0 may swell toward the substrate side and slightly increase the junction capacitance, the impurity concentration and distribution of the N-type layer 20 are controlled by ion implantation conditions and heat treatment (activation) conditions after implantation, and Below the diffusion region 15, a diffusion layer having the same conductivity type as the diffusion region and a concentration lower than that of the diffusion region, or a diffusion layer having the same conductivity type as the well 12 (P type in this case) and a concentration lower than that of the well 12 are formed. By doing so, conversely, the junction capacitance can be reduced. Such control can be realized without introducing any special technique.

In the above embodiments, the N-channel type MOS transistor having the single drain structure has been described as an example. However, the present invention is not limited to the P-channel type MOS transistor, and the MOS having the LDD structure or the gate overlap structure. The present invention can be applied to a transistor and other insulated gate type transistors, and in those cases, the same effect as in the case of the above embodiment can be obtained.

[0033]

According to the present invention, the bottom surface of the contact hole does not include a plane having the same height as the plane of the diffusion region, and includes the regions other than the source region and the drain region, so that the insulating film bottom portion for separating the active region is formed. By utilizing the fact that the surface of the substrate has an angle with respect to the diffusion area plane, the bottom surface of the contact hole extending from the diffusion area to the active area separation is larger than the bottom surface of the contact hole when it exists only in the diffusion area plane. It is possible to improve the circuit operation by reducing the contact resistance that affects the circuit operation without increasing the junction capacitance of the diffusion layers in the source / drain regions. When a layout rule is applied that allows the contact hole to protrude from the source / drain diffusion region, the distance from the contact end to the gate electrode end does not change, so the area of the diffusion region itself can be reduced, and the junction capacitance of the diffusion region can be reduced. Rather decreases.

The bottom surface of the contact hole is located below the plane flush with the surface of the substrate and above the junction position between the source region or the drain region and the substrate semiconductor portion located below them, thereby forming a junction. The contact resistance can be reduced without increasing the capacitance. There is some margin from the bottom surface of the contact hole to the junction position between the diffusion layer and the well, and leakage from the electrode wiring to the semiconductor substrate is suppressed. By making the impurity concentration of the bottom surface of the contact hole higher than the impurity concentration of the source region and the drain region, it is possible to prevent leakage from the electrode wiring to the substrate, and to give a certain margin to misalignment.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a conventional contact portion.

2A to 2C are process cross-sectional views showing a manufacturing method corresponding to claim 4 for manufacturing an embodiment corresponding to claim 1, and FIG. 2B is a contact hole portion in FIG. It is an expanded sectional view showing.

FIG. 3 is a plan view of a diffusion region showing an area reduction effect of the diffusion region in the embodiment of FIG.

4A to 4C are process sectional views showing a manufacturing method corresponding to claim 5 for manufacturing an embodiment corresponding to claim 2, and FIG. 4B is a contact hole portion in FIG. It is an expanded sectional view showing.

5A to 5C are process cross-sectional views showing a manufacturing method corresponding to claim 6 for manufacturing an embodiment corresponding to claim 3. FIGS.

[Explanation of symbols]

11 P-type silicon substrate 12 P-type well 13 Gate oxide film 14 Polycrystalline silicon gate electrode 15 Source / drain region diffusion layer 15 ′ Overetched diffusion layer 16 Field oxide film 16 ′ Field oxide film removed by overetching 17 interlayer insulating film 18 electrode wiring 19 channel region 20 N-type layer formed by ion implantation through a contact hole

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 29/78 301 S (72) Inventor Yasuyuki Shindo 1-3-6 Nakamagome, Ota-ku, Tokyo Stock company Ricoh

Claims (6)

[Claims] 1. A MOS type semiconductor device in which contact holes are provided on a source region and a drain region of a semiconductor substrate, and electrode wiring is connected to the source region and the drain region through the contact holes, respectively. A semiconductor device characterized in that the bottom surface of the hole does not include a plane having the same height as the surface of the source / drain diffusion region, and does not include a region other than the source region and the drain region. 2. A MOS type semiconductor device in which contact holes are provided on a source region and a drain region of a semiconductor substrate, and electrode wiring is connected to the source region and the drain region through the contact holes, respectively. A semiconductor device, wherein a bottom surface of the hole is located below a plane having the same height as the source / drain diffusion region and above a junction position between the source region or the drain region and a substrate semiconductor portion existing thereunder. 3. The semiconductor device according to claim 2, wherein the impurity concentration of the bottom surface of the contact hole is higher than the impurity concentrations of the source region and the drain region. 4. An isolation insulating film for isolating an active region is formed on a surface of a first conductivity type semiconductor substrate, and a gate is formed on a portion of the active region, which is to be a channel region, on the substrate via a gate insulating film. An electrode is formed, a source region and a drain region of the second conductivity type are formed on the surface of the substrate in the active region so as to sandwich the channel region, and then a contact with an electrode wiring is formed by the following steps. Of manufacturing a semiconductor device. (A) a step of depositing an interlayer insulating film on the entire surface of the substrate from above the gate electrode, (B) setting a contact hole region in a region extending over the source region and the isolation insulating film, and a region extending over the drain region and the isolation insulating film, Forming a contact hole by selectively etching the interlayer insulating film in the contact hole region and exposing the substrate in the source region and the drain region and the substrate under the isolation insulating film, (C) through the contact hole A step of ion-implanting a second conductivity type impurity into the substrate, (D) and then forming an electrode wiring connected to the source region or the drain region through the contact hole. 5. An isolation insulating film for isolating an active region is formed on a surface of a first conductivity type semiconductor substrate, and a gate insulating film is formed on a portion of the active region, which is to be a channel region, on the substrate via a gate insulating film. An electrode is formed, a source region and a drain region of the second conductivity type are formed on the surface of the substrate in the active region so as to sandwich the channel region, and then a contact with an electrode wiring is formed by the following steps. Of manufacturing a semiconductor device. (A) a step of depositing an interlayer insulating film on the entire surface of the substrate from above the gate electrode, (B) setting a contact hole region in the source region and drain region, and selectively etching the interlayer insulating film in the contact hole region, and A step of etching a contact hole below a surface of a substrate and a position above a junction between a source region or a drain region and a substrate semiconductor existing below the drain region to form a contact hole, (C) a source through the contact hole Forming an electrode wiring connected to the region or the drain region. 6. An isolation insulating film for isolating an active region is formed on a surface of a first conductivity type semiconductor substrate, and a gate is provided on a portion of the active region, which is to be a channel region, on the substrate via a gate insulating film. An electrode is formed, a source region and a drain region of the second conductivity type are formed on the surface of the substrate in the active region so as to sandwich the channel region, and then a contact with an electrode wiring is formed by the following steps. Of manufacturing a semiconductor device. (A) a step of depositing an interlayer insulating film on the entire surface of the substrate from above the gate electrode, (B) setting a contact hole region in the source region and drain region, and selectively etching the interlayer insulating film in the contact hole region, and A step of etching a contact hole below a surface of a substrate and a position above a junction position between a source region or a drain region and a substrate semiconductor existing below each of them to form a contact hole; (2) A step of ion-implanting a conductivity type impurity, and (D) a step of forming an electrode wiring connected to the source region or the drain region through the contact hole.