JPH0322528A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the removal of the ion-implanted regions at the highest concentration even in case the parts beneath contact windows are removed by overetching process by a method wherein the first heattreatment process expanding ion implanted regions to some extent is performed before making contact windows and then the contact windows are made in an insulating film. CONSTITUTION:Before or after the formation of an insulating layer 12 such as SiO2, etc., on the whole surface, the first heat treatment process is performed e.g. in N2 atmosphere at 850 deg.C for 60 minutes meeting the requirements which will not suffice for the activation of ion implanted in the ion-implanted regions 11 but will be effective for expanding the ion-implanted regions 11 deeper than the etching depth (d) in the surface of a semiconductor substrate 21 in case of making contact windows 13. Next, the contact windows 13 are made in the insulating layer 12 corresponding to the respective regions 11 simultaneously forming recessions 25 by the depth (d) on the surface of the semiconductor substrate 21. Next, the whole surface of the insulating layer 12 is coated with semiconductor 14 e.g. polycrystal silicon and etched back so as to be buried in the contact windows 13 e.g. by low pressure CVD process so that the surface of the semiconductor 14 may be almost flush with the surface of the insulating film 12. Next, the semiconductor 14 is doped with an impurity and the second heat treatment is performed. Finally, e.g. metal wirings 26 striding over the buried in semiconductor 14 are formed after a specific pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device including a step of forming a required semiconductor region by implanting impurity ions.

[Summary of the invention]

The present invention relates to a method for manufacturing a semiconductor device, and includes an impurity ion implantation step, an insulating layer forming step, a first heat treatment step performed before or after the insulating layer forming step, and a contact window opening for the insulating layer. a process of embedding a semiconductor in the contact window, and a second heat treatment process, the first heat treatment process being an ion implantation process deeper than the depth of the overetch that occurs in the contact window opening. The second heat treatment step is performed under heat treatment conditions that activate the ion implantation region to function as a component region of the intended semiconductor device, thereby expanding the region. To enable good contact with a semiconductor embedded in a shallow contact window on this structure region.

[Conventional technology]

As the degree of integration in semiconductor devices, especially semiconductor integrated circuits, increases, the area of contact of electrode wiring to the component area of the semiconductor circuit element is also reduced, and as a result, an insulating layer is formed to cover the area. The aspect ratio (thickness/width) of the contact window becomes large. When the aspect ratio of the contact window becomes large in this way, it is difficult to insert, for example, an Al electrode wiring into this structure area through this contact window and make it an ohmic contact, resulting in poor coverage. , it becomes difficult to make good contact, resulting in a decrease in reliability.

In order to avoid such inconveniences, a structure is adopted in which, for example, polycrystalline silicon is buried in the contact window of the insulating layer, the surface is flattened, and Affi wiring is provided over the insulating layer, including over the buried semiconductor. something is proposed. However, with this structure, heat treatment is required to activate impurities doped into the polycrystalline silicon in order to improve the conductivity of the buried polycrystalline silicon.

On the other hand, in order to achieve finer patterns as semiconductor integrated circuits become more highly integrated, it is necessary to make their constituent regions, for example, the source and drain regions of MOS transistors, shallower. Therefore, the ion-implanted impurity activation process for forming these source and drain regions and the impurity activation process in the polycrystalline buried in the contact hole described above, that is, high-temperature heat treatment, should be performed simultaneously as much as possible. and suppress the expansion of the drain region.

In other words, there is a need to avoid the occurrence of defects in breakdown voltage between the source and drain due to the reduction in the effective channel due to the expansion of the pn junction in the source and drain regions.

In addition, by using semiconductor crystals in this type of contact window,
In addition, a proposal for a method of diffusing impurities from semiconductor regions such as source and drain regions (Japanese Patent Application Laid-Open No. 103646/1986)
However, in this case, along with the diffusion, the semiconductor region, that is, the junction, also expands, resulting in problems such as the reduction of the effective channel described above.

On the other hand, in order to form a shallow semiconductor region, that is, a shallow junction, it is necessary to lower the implantation energy of ion implantation for introducing impurities into the semiconductor substrate, and the peak position of the impurity introduction distribution is biased toward the surface of the semiconductor substrate. It's coming. For this reason, in order to form a contact window for the above-mentioned insulating layer, if a certain amount of overetching is performed in order to form a reliable contact window, for example, 60% Hard etching (60% over-etching means over-etching corresponding to about 60% of the just etching time until the etching corresponding to the thickness of the insulating layer is completed), but in this case, for example, as shown in Fig. 2. As shown, for example, a silicon semiconductor substrate (
1) RIE on the upper Sin and insulating layer (2) using CHF
When etching is performed using 3 gases, etching progresses on the silicon semiconductor substrate (1), and a portion of the surface of the substrate is scraped off to form a recess (3), thereby etching the semiconductor element formed on the surface of the semiconductor substrate. There may be cases where the peak position of the ion implantation concentration distribution in the controlled region (4) is scraped off.

Therefore, a semiconductor (6) such as polycrystalline silicon is buried in this contact window (5), and a structural region (4) is embedded in this contact window (5).
) side into the semiconductor (6), even if the method disclosed in JP-A-60-103646 is used, the diffusion from the bottom of the buried semiconductor (6) is insufficient. As a result, impurity diffusion occurs from the side, and as shown by the broken line in FIG. 3, the deposited part of the semiconductor (6) substantially penetrates through the region (4), or the contact becomes insufficient. There is an inconvenience in that the reliability of the contact decreases.

Incidentally, looking at the relationship between overetching and impurity concentration distribution in Figure 3, the horizontal axis in Figure 3 is the distance in the depth direction from the semiconductor substrate surface, and the solid line curve (3
l) is 20 KeV through a 100-layer Sing film.
In the initial concentration distribution of BF2'' ion-implanted with a dose of 3XIO'S/cd, each dashed curve corresponds to the curve (
31) in an N2 atmosphere for those with a distribution of
The concentration distribution after heat treatment at 00°C for 10 seconds,
Curve (32) is the concentration distribution when no Oher etching is performed, and curves (33), (34), and (35) are the concentration distribution when Oher etching is performed from the substrate surface with 100, 150, and 200 pieces, respectively. It can be seen that the concentration distribution decreases as the Oher etching increases.

(Problems to be Solved by the Invention) As described above, the present invention is to form a constituent region sufficiently shallow with respect to the constituent region of the intended semiconductor device, and to form a perforation in an insulating layer thereon. In order to obtain a semiconductor device in which electrode wiring contacts are made by embedding a semiconductor in a contact window with a large aspect ratio, it is necessary to make the structure area, that is, the junction, sufficiently shallow and to reliably lead out the electrode wirings, that is, make ohmic contacts. To obtain a highly reliable semiconductor device that can be used in various ways.

[Means to solve the problem]

As shown in FIG. 1A, for example, the present invention includes a step of ion-implanting impurities to form an impurity implantation region (1l) for forming a certain region of a target semiconductor device, such as a source and drain region; As shown in Figure 1B, an insulating layer (
12), a first heat treatment step performed before or after the step of forming the insulating layer (12), and a step of opening a contact window (13) for the insulating layer (12), as shown in FIG. 1D. As shown, a semiconductor (1
4) and a second heat treatment step.

In particular, the first heat treatment step does not require activation of impurities, and is performed under heat treatment conditions that extend the ion implantation deeper than the depth of overetching that occurs when opening the contact window (13). The heat treatment step is performed under heat treatment conditions that activate impurities so that the ion implantation region (II) functions as a target region of the semiconductor device.

[Effect]

According to the method of the present invention described above, although it is not sufficient to sufficiently activate the implanted impurities in the ion-implanted region (11) prior to opening the contact window (13), the region (11) is After applying the first heat treatment step to widen the insulation layer (12) to a certain extent, the contact l/window (13) is formed on the insulating layer (12).
), even if the bottom of the contact window (13) is scraped off due to over-etching in the process of opening the contact window (13), the peak concentration position of the ion implantation region (11) will be scraped off. This avoids problems such as low concentration in the contact area with the semiconductor (14) formed in the contact window (13) or the semiconductor (14) eventually penetrating through the region (11). Not only this, but also the effect of sucking up impurities from this high impurity concentration region (11) to the semiconductor (14) is produced, and together with good ohmic contact, a highly reliable semiconductor device is obtained. Moreover, since the heat treatment for activating the impurity, that is, the heat treatment at high temperature in general, can be performed in one heat treatment step, the final structure of the semiconductor device formed by the impurity implanted region (1l) can be improved. The region can be formed as a shallow region, which makes it possible to reduce the overall area and therefore increase the degree of integration in integrated circuits, and also to avoid short channel effects in circuit elements such as MOS transistors. .

〔Example〕

An example in which the method for manufacturing a semiconductor device according to the present invention is applied to obtaining a Mos transistor will be described with reference to FIG. In the figure, (21) is a semiconductor substrate, which is more powerful than a semiconductor silicon substrate of conductivity type 1, for example, n-type. As shown in FIG. 1A, a thick insulating layer (22), so-called TOCOS, is formed on the entire surface of the substrate (21) by thermal oxidation, etc. in the field area other than the area where the semiconductor element (MOS in this example) is formed.
form. Then, the gate insulating layer (23) is formed in the element formation region where the thick insulating layer (22) is not formed.
) is formed by thermal oxidation etc., and a gate electrode (
24) as an example? For example, it is formed by a polycrystalline silicon layer with low resistivity. Using the thick insulating layer (22) and the gate electrode (24) as a mask, the impurity implanted region (11), which will eventually function as the source and drain regions, that is, the structural region of the MOS transistor, is formed to a thickness of, for example, 100 mm. 3×1 at 20 KeV through human Si02 gate insulating layer
BF2+ is ion-implanted at a dose of 0'5/cJ to form an ion-implanted region (11>).

As shown in FIG. 1B, an insulating layer (12) of SiO2, etc., and an interlayer insulating layer of SiO2, for example, are formed by CVD on the entire surface.
For example, it is formed over the entire surface to a thickness of about 8,000 people using a method. Before or after forming this insulating layer (12),
Particularly in the present invention, a first heat treatment is performed.

This first heat treatment is carried out at 850°C6 in a N2 atmosphere, for example.
Although the implanted ions in the ion implantation region (1l) cannot be sufficiently activated by etching the ion implantation region (1l) for 0 minutes, the ion implantation region (1l) is etched deeper than the etching depth d of the semiconductor substrate surface when opening a contact window, which will be described later. 1l) is carried out under conditions that have the effect of widening.

Next, as shown in FIG. 1C, contact windows (13) are formed on each region (11) of the insulating layer (12) by, for example, RIE (reactive ion etching).

This RIE is performed by 60% over-etching using C113 gas, for example. In this case, at the same time as the contact window (13) is formed, a recess (25) having a depth of about 400 mm, for example, is formed by penetrating into the surface of the semiconductor substrate (21) by a depth d. In other words, this recess (25
) The depth of the ion implantation region (11) is expanded by the first heat treatment step described above.

Next, as shown in FIG. 1D, the entire surface is covered with a semiconductor (14), such as polycrystalline silicon, by, for example, low-pressure CVD (low-pressure chemical vapor deposition) so as to bury the inside of the contact window (13). The semiconductor (14) is deposited and etched back to embed the semiconductor (14) in the contact window (13) so that its surface almost coincides with the surface of the insulating layer (12).Next, this semiconductor (14), for example, polycrystalline silicon Impurity doping is performed on the substrate, and then a second heat treatment is performed.

This second heat treatment can simultaneously activate the impurity in the semiconductor (14) embedded in the contact window (13) and the impurity in the ion implantation region (l1).
RTA (Rapid Therma) for CIO minutes
l Annealing). After that, for example, metal wiring, for example, AI! ．． A wiring (26) is formed in a predetermined pattern across the buried semiconductor (14), and the wiring is led out from each region (l1). In this way, the region (l1) forms a region having a predetermined function, that is, a source and a drain, and the conductive semiconductor (
In the example 14), the wiring (26) is electrically led out through semiconductor silicon.

In the above example, the present invention has been described for the case of obtaining a MOS transistor, but the present invention can be applied to the case of obtaining a semiconductor device having various other semiconductor elements.

〔Effect of the invention〕

According to the above-mentioned method of the present invention, Konkuku 1/Window (l3)l
2. Prior to opening the window in step 2, the ion implanted region (l1) is subjected to a first heat treatment step which is sufficient to expand the region (l1) to some extent, although it is not sufficient to sufficiently activate the implanted impurity. Contact window (l) to insulating layer (l2)
Since the drilling process of 3) is performed, this contact window (13)
Even if the bottom of the contact window (13) is scraped off due to over-etching in the window opening process, the peak concentration position of the ion implantation region (l1) is prevented from being scraped off. Not only is it possible to avoid problems such as lowering the concentration in the contact area with the formed semiconductor (14) or the semiconductor (l4) eventually passing through the region (1l), but also to avoid this high impurity concentration region (11). The effect of sucking up impurities from the semiconductor (14) to the semiconductor (14) is also produced, and good over-the-wall contact is achieved, which together make it possible to obtain a highly reliable semiconductor device. Moreover, since the heat treatment for activating the impurity, that is, the heat treatment at high temperature in general, can be performed in one heat treatment process, the impurity implanted region (
11) It is possible to form a certain region of the structure of a semiconductor device as a shallow region, thereby reducing the overall area and therefore increasing the degree of integration in integrated circuits.
Furthermore, it is possible to avoid short channel effects in circuit elements such as MOS+- transistors.

[Brief explanation of the drawing]

1A to 1D are schematic cross-sectional views of each step of an example of the manufacturing method of the present invention, FIG. 2 is a concentration distribution diagram of an ion implantation region, and FIG. 3 is an explanatory diagram of main parts of a conventional semiconductor device. . (21) is a semiconductor substrate, (11) is an impurity implanted region, (
23) is a gate insulating layer, (13) is a contact window, (l
4) is a buried semiconductor within the contact window.

Claims (1)

[Claims] An impurity ion implantation step, an insulating layer forming step, a first heat treatment step performed before or after the insulating layer forming step, a contact window opening step for the insulating layer, and the contact. a step of embedding a semiconductor in the window; and a second heat treatment step; the first heat treatment step is performed under heat treatment conditions that extend the ion implantation region deeper than the depth of the overetch that occurs in the contact window opening; A method for manufacturing a semiconductor device, wherein the second heat treatment step is performed under heat treatment conditions that activate impurities so that the ion implantation region functions as a component region of the intended semiconductor device.