JP2007088432A - Transistor and display device using the same, electronic equipment, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transistor having a low contact resistance. <P>SOLUTION: This transistor comprises: a semiconductor film containing impurity elements imparting P-type or N-type; an insulating film disposed thereon; and an electrode or a wiring electrically connected to the semiconductor film through at least a contact hole formed in the insulating film, wherein in the semiconductor film, the concentration of the impurity elements contained in a deeper region than a predetermined depth is in a first range (1×10<SP>20</SP>/cm<SP>3</SP>or less) and the concentration of the impurity elements contained in a shallower region than a predetermined depth is in a second range (more than 1×10<SP>20</SP>/cm<SP>3</SP>); and in a deeper region than a portion of the semiconductor film which is contacted with the electrode or the wiring, the concentration of the impurity elements is in a first range. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The invention disclosed in this specification relates to a transistor (eg, a thin film transistor) which is a semiconductor element, a display device using the transistor, and the like. Further, the present invention relates to manufacture of the transistor.

  When a thin film transistor is manufactured, a contact hole for connecting a wiring or an electrode with a semiconductor film or a conductive film covered with an insulating film such as an interlayer insulating film or a gate insulating film is dry-etched with respect to the insulating film. It is formed in a predetermined shape (see, for example, paragraph 34 of Patent Document 1).

Dry etching is a method of etching using a gas instead of using an acidic or alkaline liquid, and a pattern having almost the same dimensions as a mask such as a resist mask can be formed. This etching is called anisotropic etching and is suitable for fine processing.
Japanese Patent Laid-Open No. 10-189481

  At the time of forming the contact hole, the insulating film is obtained by performing dry etching on the bottom of the contact hole under the condition that the semiconductor film or the conductive film existing in contact with (underneath) the insulating film is slightly etched. Can be completely removed. However, excessive etching that causes the semiconductor film or the conductive film to be thinned to a thickness less than half the thickness before etching or disappears is not intended. Overetching refers to etching of a film, a substrate, or the like existing in contact with an etching target deeper than the thickness of the etching target (corresponding to an insulating film in this specification).

  When the semiconductor film or the conductive film disappears at the bottom of the contact hole, there is a problem that even when a wiring or an electrode is formed in the contact hole, the contact resistance is extremely high and the manufactured transistor does not operate normally. This problem becomes more serious as the film thickness immediately before the contact hole of the semiconductor film or conductive film is formed is thinner.

  If the semiconductor film or the conductive film disappears completely at the bottom of the contact hole, a wiring or an electrode formed later in the contact hole comes into contact with only the side surface of the semiconductor film or the conductive film. The thickness of the semiconductor film in which the source region or drain region of the thin film transistor is formed is generally 100 nm or less. For example, in the case of a thin semiconductor film having a thickness of 30 nm to 40 nm, the contact area between the wiring or electrode and the semiconductor film is extremely small, which causes the contact resistance to increase.

  In order to solve the above problem, the inventors tried to prevent unintentional excessive etching by devising conditions for dry etching, but it was difficult to obtain appropriate conditions.

  When the above-described case where excessive etching occurs is investigated, it has been found that excessive etching occurs when an impurity element imparting a predetermined conductivity type such as phosphorus is contained in a high concentration in the semiconductor film of the transistor. Moreover, it has been found that the etching depth of the semiconductor film changes depending on the doping condition that changes the concentration distribution of the impurity element in the semiconductor film.

  It is known that when the acceleration voltage, which is one of the conditions for doping an impurity element, changes, the depth direction distribution of the concentration of the impurity element also changes. Usually, by increasing the acceleration voltage, the maximum value of the concentration of the impurity element appears in a deeper portion in the distribution of the concentration of the impurity element in the depth direction. It should be noted that the etching rate of the semiconductor film changes depending on the concentration of the impurity element imparting a predetermined conductivity type contained in the semiconductor film. The etching rate is obtained by dividing the thickness or depth of the etching target by the etching time.

A gas used for dry etching for forming a contact hole in an insulating film formed over a semiconductor film is CHF ₃ , CF _4, or the like (and rare gas such as helium and argon) that selectively etches the insulating film. Gas may be included). By using the gas, the etching rate for the insulating film is larger than the etching rate for the semiconductor film, but the semiconductor film is not completely etched. The ratio between the etching rate “a” of the etching object and the etching rate “b” of the material (e.g., corresponding to a semiconductor film in this specification) in contact with the etching object, and a / b is referred to as an etching selectivity. . However, “a” and “b” are positive numbers.

The invention disclosed in this specification includes a semiconductor film including an impurity element imparting P-type or N-type, an insulating film formed over the semiconductor film, and at least a contact hole formed in the insulating film. An electrode or a wiring electrically connected to the semiconductor film, wherein the semiconductor film has a concentration of the impurity element contained in a region deeper than a predetermined depth in a first range, and the predetermined film The concentration of the impurity element contained in the region shallower than the depth is a second range higher than the first range, and is deeper than the portion of the semiconductor film that is in contact with the electrode or the wiring (the bottom of the contact hole) In the region (first region), the concentration of the impurity element is in the first range. For example, the first range is 1 × 10 ²⁰ / cm ³ or less, and the second range is more than 1 × 10 ²⁰ / cm ³ and 1 × 10 ²¹ / cm ³ or less. The semiconductor film is used as a source, drain, gate electrode, or the like of a transistor.

Another invention disclosed in this specification includes a source region and a drain region containing an impurity element imparting P-type or N-type, an insulating film formed over the source region and the drain region, and at least the insulating film. An electrode or a wiring electrically connected to one of the source region and the drain region through the formed contact hole, and the source region and the drain region are included in a region deeper than a predetermined depth The concentration of the impurity element in the first range and the concentration of the impurity element contained in the region shallower than the predetermined depth is a second range higher than the first range, and the source region A region (first region) deeper than a portion (bottom portion of the contact hole) in contact with the electrode or wiring in either one of the drain region and the drain region is a concentration of the impurity element. Wherein a first range. For example, the first range is 1 × 10 ²⁰ / cm ³ or less, and the second range is more than 1 × 10 ²⁰ / cm ³ and 1 × 10 ²¹ / cm ³ or less. The source region and the drain region are formed by introducing the impurity element into a partial region of the semiconductor film.

  The thickness of the first region is thinner than the second region of the semiconductor film (or one of the source region and the drain region) excluding the first region (for example, 1 nm or more thinner), The lower limit is 50%, preferably 60%, and more preferably 65% of the thickness of the second region. This is to prevent the insulating film from remaining at the bottom of the contact hole and to prevent the contact resistance between the semiconductor film and the electrode or wiring from increasing. Even when the thickness of the semiconductor film is 45 nm or less and the lower limit is 30 nm, the semiconductor film does not disappear at the bottom of the contact hole.

  The predetermined depth needs to be 1 nm or more, and is 50% or less, preferably 40% or less, more preferably 35% or less of the thickness of the second region of the semiconductor film. In this specification, the depth is a value when an arbitrary point on the surface of the object (semiconductor film, source region, drain region, etc.) that is not over-etched is a reference, that is, a depth of 0 nm.

  As the semiconductor film, a film containing silicon as its main component, a film containing silicon and germanium, or the like can be used. The semiconductor film may contain hydrogen. The semiconductor film may be any of a polycrystalline semiconductor film, a single crystal semiconductor film, a microcrystalline semiconductor film, and an amorphous semiconductor film. Instead of the semiconductor film, a single crystal or polycrystalline semiconductor substrate, typically a silicon substrate, may be used, and a field effect transistor may be manufactured by applying the invention disclosed in this specification. In this case, the depth of the source region (drain region) formed in the semiconductor substrate corresponds to the thickness of the semiconductor film.

  The impurity element is typically phosphorus when the conductivity type is N-type, but may be an impurity element other than phosphorus such as arsenic. When the conductivity type is P-type, it is typically boron but boron. Other impurity elements may be used.

  Even when the semiconductor film is thin, the semiconductor film can be prevented from disappearing at the bottom of the contact hole. Furthermore, at the bottom of the contact hole, the semiconductor film can remain 50% or more of the thickness of the portion where the contact hole is not formed. Therefore, an increase in contact resistance between the semiconductor film connected via the contact hole and the wiring or electrode is suppressed.

  When the contact hole is formed by dry etching the insulating film, overetching can be stopped at a desired depth. Therefore, a transistor free from contact failure is obtained in which the insulating film is completely removed at the bottom of the contact hole.

(Embodiment 1)
An example of manufacturing a thin film transistor (hereinafter referred to as a TFT in this specification) will be described below.

  First, as illustrated in FIG. 1A, a base insulating film 112 is formed with a thickness of 100 nm to 300 nm over a substrate 111. As the substrate 111, a glass substrate, a quartz substrate, a plastic substrate, an insulating substrate such as a ceramic substrate, a metal substrate, a semiconductor substrate, or the like can be used.

The base insulating film 112 includes silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxide containing nitrogen (SiO _x N _y ) (x>y> 0) (also referred to as silicon oxynitride), and nitride containing oxygen A single-layer structure of an insulating film containing oxygen or nitrogen such as silicon (SiN _x O _y ) (x>y> 0) (also referred to as silicon nitride oxide) or a stacked structure thereof can be used. In particular, in the case where impurities contained in the substrate 111 such as alkali metal or contaminants attached to the substrate 111 become a problem, the base insulating film 112 is preferably formed.

A glass substrate is used as the substrate 111 and is excited by microwaves. The electron temperature is 0.5 eV or more and 1.5 eV or less, the ion energy is 5 eV or less, and the electron density is 1 × 10 ¹¹ / cm ³ or more and 1 × 10 ¹³ / cm ^3. The surface of the glass substrate may be directly plasma-treated with the following plasma having a high electron density and a low electron temperature. Plasma generation can be performed using a microwave-excited plasma processing apparatus using a radial slot antenna. At this time, when a nitride gas such as nitrogen (N ₂ ), ammonia (NH ₃ ), or nitrous oxide (N ₂ O) is introduced, the surface of the glass substrate can be nitrided. Since the nitride layer formed on the surface of the glass substrate is mainly composed of silicon nitride, it can be used as a blocking layer for impurities diffusing from the glass substrate. A silicon oxide film or a silicon oxide film containing nitrogen may be formed over the nitride layer by a plasma CVD method to form the base insulating film 112.

  In addition, by performing the above plasma treatment on the surface of the base insulating film 112 formed of silicon oxide or silicon oxide containing nitrogen, the surface and the depth from the surface to 1 nm to 10 nm can be nitrided. Can do. By this extremely thin nitrided layer, the base insulating film 112 can be used as a blocking layer without affecting the semiconductor film formed later on the base insulating film 112.

  The base insulating film 112 in contact with the semiconductor film is preferably a silicon nitride film or a silicon nitride film containing oxygen having a thickness of 0.01 nm to 10 nm, preferably 1 nm to 5 nm. When crystallizing a semiconductor film using a metal element, it is necessary to getter the metal element. At this time, if the base insulating film 112 is a silicon oxide film, a metal element in the semiconductor film reacts with oxygen in the silicon oxide film at the interface between the silicon oxide film and the semiconductor film to become a metal oxide. In some cases, the metal element is difficult to getter. Therefore, a silicon oxide film is preferably not used for a portion of the base insulating film 112 that is in contact with the semiconductor film.

Subsequently, in this embodiment, a film containing silicon as a main component is formed as a semiconductor film with a thickness of 60 nm to 70 nm. As the semiconductor film, a crystalline semiconductor film in which an amorphous semiconductor film or a microcrystalline semiconductor film is formed by a CVD method and crystallized by a laser crystallization method using an excimer laser or the like can be used. The microcrystalline semiconductor film can be obtained by glow discharge decomposition of a gas composed of a silicon compound such as SiH ₄ . By diluting and using a gas composed of a silicon compound, the microcrystalline semiconductor film can be easily formed. Since a semiconductor film formed by a CVD method contains a large amount of hydrogen, heat treatment for dehydrogenation is performed as necessary before crystallization. When laser crystallization is performed, it is preferable to perform heat treatment for dehydrogenation in advance. An amorphous semiconductor film may be used instead of the crystalline semiconductor film.

  Further, as a crystallization technique, a rapid thermal annealing method (RTA method) using a halogen lamp or a technique for crystallization using a heating furnace can be applied. Further, a method may be used in which a metal element such as nickel is used and the amorphous semiconductor film is solid-phase grown using the element as a crystal nucleus.

Next, a film containing silicon as a main component is formed into a predetermined shape through a photolithography process. In this embodiment mode, the predetermined shape is an island shape, and the film 113 containing island-shaped silicon as a main component is formed. Boron (B) may be added as an impurity element to the island-shaped silicon 113 film. At that time, the concentration of boron in the film 113 containing island-shaped silicon as a main component is 1 × 10 ¹⁵ / cm ³ to 1 × 10 ¹⁸ / cm ³ (preferably 1 × 10 ¹⁶ / cm ^{3 to} 5 × 10 ¹⁷ / cm ³ ).

  A first insulating film 114 is formed to a thickness of 5 to 50 nm by a CVD method or a sputtering method so as to cover the film 113 containing island-shaped silicon as a main component. The first insulating film 114 is in contact with the film 113 containing island-shaped silicon as a main component and functions as a gate insulating film.

As the first insulating film 114, silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxide containing nitrogen (SiO _x N _y ) (x>y> 0), silicon nitride containing oxygen (SiN _x) Any structure such as O _y ) (x>y> 0) may be appropriately combined to form a stacked structure. In this embodiment mode, the first insulating film 114 has a stacked structure of a SiN _x O _y film and a SiO _x N _y film. The surface of the first insulating film 114 may be densified by oxidation or nitridation treatment with the above-described plasma having a high electron density and a low electron temperature. This treatment may be performed prior to the formation of the first insulating film 114. That is, plasma treatment is performed on the surface of the film 113 containing island-shaped silicon as a main component. At this time, the substrate temperature is set to 300 ° C. to 450 ° C., and plasma treatment is performed in an oxidizing atmosphere (O ₂ , N ₂ O, etc.) or a nitriding atmosphere (N ₂ , NH _3, etc.), so that island-like silicon is a main component A favorable interface can be formed with the insulating film deposited on the film 113 to be formed.

Subsequently, a conductive film to be a gate electrode is formed over the first insulating film 114. As the conductive film, an aluminum (Al) film, a copper (Cu) film, a film containing aluminum or copper as a main component, a chromium (Cr) film, a tantalum (Ta) film, tantalum nitride (TaN _x ) (x> 0) ) Film, titanium (Ti) film, tungsten (W) film, tungsten nitride (WN _x ) (x> 0) film, molybdenum (Mo) film, a laminated film in which any two or more of the above films are laminated, for example, A laminate of an Al film and a Ta film, a laminate of an Al film and a Ti film, a laminate of a TaN _x film and a W film, or the like can be used. In this embodiment mode, the conductive film is a stacked film of about 30 nm of tantalum nitride (TaN _x ) and about 370 nm of tungsten (W).

Subsequently, an electrode 116 having a predetermined shape is formed from the conductive film through a photolithography process (FIG. 1A). In this embodiment mode, first etching is selectively performed on tungsten (W) in the stacked film included in the conductive film. At that time, it is preferable to perform etching under a condition where the etching selectivity of tungsten (W) to tantalum nitride (TaN _x ) is high so that tantalum nitride (TaN _x ) is not etched. An example of the first etching condition is as follows. A mixed gas of CF ₄ , Cl ₂ , and O ₂ is used, and the mixing ratio is CF ₄ / Cl ₂ / O ₂ = 60 sccm / 50 sccm / 45 sccm, and power of 2000 W is supplied to the coil-type electrode at a pressure of 0.67 Pa. To generate plasma. A power of 150 W is applied to the substrate side (sample stage). The temperature of the sample stage is −10 ° C.

  As the resist mask used in the photolithography process, a resist mask having a vertical shape can be used. When the resist mask is removed after the first etching, the reaction product by etching is attached to the side wall of the obtained tungsten (W) pattern 116a. The reaction product is removed by immersing in a chemical solution (trade name: SPR301) containing oxalic acid as a main component at 60 ° C. for 10 minutes.

Subsequently, second etching is selectively performed on tantalum nitride (TaN _x ) (x> 0) using the tungsten (W) pattern 116 a as a mask. At this time, it is preferable to perform etching under a condition where the etching selectivity between tantalum nitride (TaN _x ) and the first insulating film 114 is high so that the first insulating film 114 is not etched. Furthermore, it is preferable to perform etching under an etching condition having a high etching selectivity between tantalum nitride (TaN _x ) and tungsten (W) so as not to etch tungsten (W). An example of the second etching condition is as follows. Using Cl ₂ gas, a power of 1000 W is supplied to the coil-type electrode at a pressure of 2.00 Pa to generate plasma. A power of 50 W is applied to the substrate side (sample stage). The temperature of the sample stage is −10 ° C.

By the second etching, a tantalum nitride (TaN _x ) pattern 116 b is obtained, and the pattern 116 b and the tungsten (W) pattern 116 a are combined to form an electrode 116 having a substantially vertical shape. The electrode 116 functions as a gate electrode or a gate wiring. The shape of the electrode 116 is not limited to a vertical shape when a sidewall is not formed later, and one or both of a tungsten (W) pattern 116a and a tantalum nitride (TaN _x ) pattern 116b are tapered. It may be formed.

  The etching in this embodiment mode is performed by dry etching, and can be performed using an ICP (Inductively Coupled Plasma) etching method.

Next, doping with an impurity element imparting P-type or N-type is performed on the island-shaped silicon 113 film (FIG. 1B). In this embodiment mode, phosphorus (P), which is an impurity element imparting N-type conductivity, is added to the film 113 containing island-shaped silicon as a main component through the first insulating film 114, so that the low-concentration impurity region 113a is added. Form. The concentration of the impurity element imparting N-type in the low-concentration impurity region 113a is 1 × 10 ¹⁵ / cm ³ to 1 × 10 ¹⁸ / cm ³ (preferably 1 × 10 ¹⁶ / cm ^{3 to} 5 × 10 ¹⁷ / cm. ³ ). As a doping method of the impurity element, an ion doping method or an ion implantation method can be used. Arsenic (As) may be used instead of phosphorus (P).

Next, a second insulating film is formed so as to cover the first insulating film 114 and the electrode 116. In this embodiment, as the second insulating film, a silicon oxide film containing nitrogen (SiO _x N _y ) (x>y> 0) is formed to a thickness of about 100 nm by plasma CVD, and then oxidized by thermal CVD. A silicon film (SiO _x ) (x> 0) is formed to a thickness of about 200 nm.

  Next, the second insulating film is selectively etched by anisotropic etching mainly in the vertical direction to form an insulator 117 in contact with the side surface of the electrode 116 (FIG. 1C). In the step of forming the insulator 117, the upper surface of the electrode 116 is exposed. However, in the case where an insulating film used as a mask is formed over the electrode 116, the upper surface of the electrode 116 may not be exposed. The insulator 117 on the side surface of the electrode 116 serves as a sidewall and can be formed with a width of 10 nm to 300 nm.

  This insulator 117 is formed in order to provide both a low-concentration impurity region 113a and a high-concentration impurity region, which will be described later, in the film 113 containing island-shaped silicon as a main component. The insulator 117 is not necessarily formed, and may be formed as necessary. If the low-concentration impurity region 113a is not formed, the insulator 117 is unnecessary.

  Through the step of forming the insulator 117, the first insulating film 114 is also partially removed, so that the insulating film 118 as illustrated in FIG. 1C is formed, and a part of the film 113 containing island-shaped silicon as a main component ( A part of the low concentration impurity region 113a) is exposed. This exposed portion will later become a source region and a drain region. The insulating film 118 functions as a gate insulating film. When the etching selectivity between the first insulating film 114 and the low-concentration impurity region 113a is low, the exposed portion of the low-concentration impurity region 113a is thinned by overetching.

  Then, as shown in FIG. 1D, using the electrode 116, the insulator 117, and the insulating film 118 as a mask, a film 113 (low-concentration impurity region 113a) containing island-shaped silicon as a main component has a P-type or N-type. Doping of an impurity element imparting a mold is performed to form a high concentration impurity region 113b. This high concentration impurity region 113b corresponds to a source region and a drain region. In this embodiment mode, phosphorus is used as the impurity element.

FIG. 2 shows the concentration distribution (depth profile) in the depth direction of phosphorus in silicon, where the horizontal axis represents the depth from the surface of the doped silicon and the vertical axis represents the concentration of phosphorus. The doping conditions for obtaining FIG. 2 are as follows: gas used: PH ₃ (phosphine) diluted to a concentration of 5%, gas flow rate: 40 sccm, acceleration voltage: 10 kV, current density: 5.0 μA, dose amount: 3 0.0 × 10 ¹⁵ / cm ² (hereinafter referred to as “condition A” in the present specification) and gas used: PH ₃ (phosphine) diluted to a concentration of 5%, gas flow rate: 40 sccm, acceleration voltage: 20 kV , Current density: 5.0 μA, dose amount: 3.0 × 10 ¹⁵ / cm ² (hereinafter referred to as “condition B” in this specification).

In FIG. 2, “Condition A” where the acceleration voltage is 10 kV is represented by a solid line, and “Condition B” where the acceleration voltage is 20 kV is represented by a broken line. As the depth becomes deeper than 20 nm, the concentration of phosphorus is markedly lower in the case of “Condition A” than in the case of “Condition B”. In the case of “Condition A”, the phosphorus concentration is 1 × 10 ²⁰ / cm ³ or less in a region where the depth is deeper than 30 nm. On the other hand, in the case of “Condition B”, the phosphorus concentration exceeds 1 × 10 ²⁰ / cm ³ in a region where the depth is shallower than 45 nm.

  In the present embodiment, “Condition A” where the acceleration voltage is 10 kV is adopted as the condition for doping phosphorus to form the high concentration impurity region 113b.

  Thereafter, the doped impurity element is activated by heat treatment or the like. Activation may be performed after forming an interlayer insulating film 120 having a single layer structure, which will be described later, or after forming a first layer or a second layer of the interlayer insulating film 120 having a laminated structure. As the activation method, laser light irradiation, RTA, heat treatment using a furnace at 550 ° C. or lower for 4 hours or shorter, and the like are used. This activation needs to be performed under the condition that the concentration distribution of phosphorus contained in the high concentration impurity region 113b in the depth direction is not uniform.

An interlayer insulating film 120 is formed to have a thickness of 600 nm or more so as to cover at least the high-concentration impurity regions 113b, which are part of the film 113 containing island-shaped silicon as a main component, and the electrode 116 (FIG. 3A). The interlayer insulating film 120 is formed using an organic material or an inorganic material. The interlayer insulating film 120 may have a single layer structure, or may have a two-layer or three-layer structure. In this embodiment mode, a three-layer structure in which a silicon nitride film is sandwiched between silicon oxide films containing nitrogen (SiO _x N _y ) (x>y> 0) is used for the interlayer insulating film 120.

  A contact hole 121 for exposing at least a part of the high concentration impurity region 113b is formed in the interlayer insulating film 120 by dry etching (FIG. 3B). Simultaneously with the formation of the contact hole 121, a contact hole (not shown) for exposing at least a part of the electrode 116 may be formed in the interlayer insulating film 120. However, attention must be paid to the depth of overetching on the electrode 116.

In this embodiment mode, dry etching for forming the contact hole 121 is performed through three steps. The gas used for dry etching in this embodiment is a mixed gas of helium (He) and CHF ₃ , but the mixing ratio (flow rate ratio) differs in each step. In the first step, the mixing ratio is CHF ₃ / He = 50 sccm / 100 sccm, and plasma is generated at a pressure of 5.5 Pa. In the second step, the mixing ratio is CHF ₃ /He=7.5 sccm / 142.5 sccm, and etching is performed at the same pressure as in the first step until the remaining film thickness of the interlayer insulating film 120 reaches about 200 nm. In the third step, a condition in which the etching selectivity between the interlayer insulating film 120 and the high-concentration impurity region 113b is high is adopted. Therefore, the mixing ratio is set to CHF ₃ / He = 48 sccm / 152 sccm, and the first step and the second step A contact hole 121 is finally formed under the same pressure.

In the present embodiment, the time required for the third step is set longer than the time required for the first step and the second step, and overetching is performed in the third step. Hereinafter, in the present specification, the above three steps are referred to as “condition C”. As the gas used in the “condition C”, another gas C _X F _Y (X and Y are positive integers) such as CF ₄ can be used instead of CHF ₃ , and another rare gas such as argon can be used instead of helium. (Ar) can be used.

  Next, a stacked structure including a conductive layer in the contact hole 121, a layer mainly containing titanium (Ti) in this embodiment, and a layer mainly containing aluminum (Al) is formed thereon by a sputtering method. Then, a wiring or an electrode 122 is formed through a photolithography process (FIG. 3C). In this way, a TFT is manufactured. Instead of titanium, a metal having a melting point higher than that of aluminum such as copper (Cu), molybdenum (Mo), tantalum (Ta), tungsten (W), or the like can be used. Further, the stacked structure may include a conductive metal nitride, and may be formed without using a layer containing aluminum as a main component. The wiring or electrode 122 is electrically connected to the high concentration impurity region 113b. The high concentration impurity region 113b includes a first region 113c and a second region 113d. The first region 113 c is a region immediately below a portion where the high concentration impurity region 113 b is in contact with the wiring or the electrode 122 (the bottom portion of the contact hole 121). The first region 113 c can also be expressed as a region deeper than a portion where the high-concentration impurity region 113 b is in contact with the wiring or the electrode 122 (the bottom portion of the contact hole 121). In the case where a contact hole (not shown) for exposing at least a part of the electrode 116 is formed, by simultaneously forming the conductive layer in the contact hole, a wiring electrically connected to the electrode 116 is formed. It is formed.

  In FIG. 4A, a high-concentration impurity region 113b formed by doping phosphorus into a film containing silicon as a main component under “Condition A” and a wiring or electrode 122 are connected to the interlayer insulating film 120 under “Condition C”. The cross section of the part connected through the contact hole 121 formed in the above is observed with an electron microscope, and a photograph taken is shown. The high-concentration impurity region 113b is over-etched when the contact hole 121 is formed. As a result, the thickness of the high-concentration impurity region 113b is about 40 nm in the first region 113c that is directly below the portion in contact with the wiring or electrode 122 (bottom portion of the contact hole 121). It has become. Since the thickness of the second region 113d excluding the first region 113c in the high concentration impurity region 113b is about 62 nm, the high concentration impurity region 113b is over-etched to a depth of about 22 nm. The depth of about 22 nm where the high concentration impurity region 113b is over-etched is 40% or less of the thickness of about 62 nm of the high concentration impurity region 113b. The sheet resistance of the high-concentration impurity region 113b is 320Ω / □ to 340Ω / □.

  The result of measuring the contact chain resistance of an element having a contact structure between a film mainly composed of silicon doped with phosphorus under “condition A” and a wiring or electrode having a laminated structure made of the same material as the wiring or electrode 122 Is shown in FIG. In this specification, the contact chain resistance is a resistance value of an element (contact chain) in which 1000 contact structures of a conductor and a semiconductor, between conductors, or between semiconductors are connected in series. Therefore, 1/1000 of the value of the contact chain resistance shown in FIG. 4B corresponds to one contact chain of a film mainly composed of silicon doped with phosphorus under “condition A” and a wiring or an electrode. The resistance is calculated to be 140Ω or more and 170Ω or less. This result shows that the resistance is low and the variation is small. In FIG. 4B, the horizontal axis represents different substrates on which contact chains are formed, and the vertical axis represents the result of measuring the contact chain resistance at a plurality of locations for the contact chains formed on the respective substrates.

The concentration distribution of phosphorus contained in the high concentration impurity region 113b shown in FIG. 4A is estimated as follows with reference to FIG. The phosphorus concentration in the region from the surface not over-etched to a depth of 22 nm (region shallower than the depth of 22 nm) was 4 × 10 ²⁰ / cm ³ or more and 1 × 10 ²¹ / cm ³ or less, and was over-etched. The phosphorus concentration on the surface (the portion in contact with the wiring or electrode 122) is about 4 × 10 ²⁰ / cm ³ , and the phosphorus concentration in a region deeper than 22 nm is lower than 4 × 10 ²⁰ / cm ³ .

Therefore, the high concentration impurity region 113b of the phosphorus concentration 4 × ¹⁰ 20 / cm ³ or more 1 × ¹⁰ 21 / cm ³ or less of the area is over-etched during the dry etching easily lost, but the phosphorus concentration of 4 × ^{10 20} / It is considered that the high-concentration impurity region 113b in a region lower than cm ³ , particularly in a region of 1 × 10 ²⁰ / cm ³ or less (with 0 / cm ³ as a lower limit) is not easily over-etched during dry etching.

  As described above, the depth of overetching can be controlled by controlling the depth direction distribution of the concentration of an impurity element such as phosphorus contained in the semiconductor film.

  The result of having confirmed by experiment that the etching rate of the semiconductor film by dry etching changes with the phosphorus density | concentration in the semiconductor film and the dose amount at the time of doping phosphorus into the semiconductor film is shown. A low etching rate means that etching is difficult.

Samples to be dry-etched are ones in which a film mainly composed of silicon doped with phosphorus is formed on the substrate, and ones in which a film mainly composed of silicon not doped is formed on the substrate. The sample doped with phosphorus is obtained by performing a heat treatment at 850 ° C. for 2 hours after doping in order to make the concentration distribution of phosphorus in the film containing silicon as a main component, particularly in the depth direction, uniform. Phosphorus doping is performed under three conditions that differ only in dose, and the dose is 7 × 10 ¹³ / cm ² , 7 × 10 ¹⁴ / cm ² , and 7 × 10 ¹⁵ / cm ² . The phosphorus concentration in the film containing silicon as a main component after the heat treatment was measured by SIMS (secondary ion mass spectrometry). As a result, the concentration of phosphorus is about 1 × 10 ¹⁹ / cm ³ in the sample doped with a dose amount of 7 × 10 ¹³ / cm ² and about 1 × in the sample doped with a dose amount of 7 × 10 ¹⁴ / cm ^2. In the sample doped with 10 ²⁰ / cm ³ and a dose of 7 × 10 ¹⁵ / cm ² , it was about 1 × 10 ²¹ / cm ³ .

The sample was subjected to dry etching using a mixed gas of helium and CHF ₃ for 2 minutes to form a contact hole. The depth of the formed contact hole is about 10 nm for the undoped sample, about 17.4 nm for the sample doped with phosphorus at a dose amount of 7 × 10 ¹³ / cm ² , and a dose amount of 7 × 10 ¹⁴ / cm ^2. In the sample doped with phosphorus at about 20.9 nm, the sample doped with phosphorus at a dose of 7 × 10 ¹⁵ / cm ² was about 25.5 nm. This result shows that the lower the phosphorus concentration in the film containing silicon as the main component, the lower the etching rate, and the undoped sample has the lowest etching rate.

As described above, although an example of manufacturing a TFT has been described in this embodiment, the invention disclosed in this specification can be applied to semiconductor elements other than the TFT. For example, a field effect transistor using a silicon substrate can be manufactured. In that case, the base insulating film 112 and the film 113 mainly containing island-shaped silicon are not provided. When a P-type silicon substrate is used as the substrate 111, the silicon substrate is doped with an impurity element imparting N-type to form a high concentration impurity region 113b (a source region and a drain region). Further, the low concentration impurity region 113a may be formed adjacent to the high concentration impurity region 113b. When the high-concentration impurity region 113b is formed, the concentration of the impurity element imparting N-type contained in a region deeper than a predetermined depth of the high-concentration impurity region 113b is set to 1 × 10 ²⁰ / cm ³ or less.

(Comparative example)
A case where phosphorus doping is performed under “condition B” in which the acceleration voltage described in the first embodiment is 20 kV is shown. In the photograph shown in FIG. 5A, a high-concentration impurity region 513b in which a film containing silicon as a main component is doped with phosphorus under “Condition B” and a wiring or an electrode 522 are formed in the interlayer insulating film 520. A cross section of a portion connected through a contact hole is observed with an electron microscope and photographed. This comparative example is different from the first embodiment only in that phosphorus doping is performed under “condition B” in place of “condition A” in which the acceleration voltage described in the first embodiment is 10 kV.

  As a result of excessive etching at the time of forming the contact hole, the high-concentration impurity region 513b is extremely thin in the first region immediately below the portion in contact with the wiring or the electrode 522, and is less than 50% of the film thickness before the contact hole is formed. It is thick. The thickness of the second region of the high concentration impurity region 513b excluding the first region is about 60 nm. The sheet resistance of the high concentration impurity region 513b is 190Ω / □ to 210Ω / □, which is lower than the sheet resistance of the high concentration impurity region 113b in the first embodiment. This result is due to the difference in the phosphorus concentration distribution.

  FIG. 5B shows the result of measuring the contact chain resistance of an element having a contact structure between a film mainly composed of silicon doped with phosphorus and wiring or an electrode 522 under “Condition B”. The contact chain resistance shown in FIG. 5B is much higher than the contact chain resistance shown in FIG. 4B, and the variation is large. This result means that even if the sheet resistance of the high concentration impurity region 513b is small as described above, it is not suitable for practical use. In FIG. 5B, the horizontal axis represents different substrates on which contact chains are formed, and the vertical axis represents the result of measuring the contact chain resistance at a plurality of locations with respect to the contact chains formed on the respective substrates.

The concentration distribution of phosphorus contained in the high concentration impurity region 513b shown in FIG. 5A is estimated as follows with reference to FIG. The phosphorus concentration in the region from the surface not over-etched to a depth of 45 nm (region shallower than the depth of 45 nm) exceeds 1 × 10 ²⁰ / cm ³ and is 1 × 10 ²¹ / cm ³ or less. The phosphorus concentration of (the portion in contact with the wiring or electrode 522) is 1 × 10 ²⁰ / cm ³ to 2 × 10 ²⁰ / cm ³ .

Therefore, the high concentration impurity region 513b in the region where the phosphorus concentration is higher than 1 × 10 ²⁰ / cm ³ and lower than or equal to 1 × 10 ²¹ / cm ³ is easily over-etched and lost during dry etching, but the phosphorus concentration is 1 × 10 6. ^It is considered that the high concentration impurity region 513b in the region of ²⁰ / cm ³ or less (with 0 / cm ³ being the lower limit) is hardly over-etched during dry etching.

  As a result of this comparative example, when the thickness of the film mainly composed of silicon doped with phosphorus under “Condition B” is 45 nm or less, the film is highly likely to disappear as a result of overetching. Is shown. When disappearing in this way, the contact chain resistance becomes larger than the value shown in FIG.

  The reason why the depth of overetching is different between the first embodiment and this comparative example will be considered. The only difference between the two processes is the difference in acceleration voltage when doping phosphorus. However, the phosphorus concentration distribution differs as shown in FIG.

In the case of the first embodiment, the high concentration impurity region 113b has a maximum phosphorus concentration in the vicinity of a depth of 10 nm. When it is deeper than 10 nm, the concentration of phosphorus decreases. At a depth of 20 nm, the concentration of phosphorus is about 5 × 10 ²⁰ / cm ³ , and when it is deeper than 30 nm, the concentration of phosphorus is 1 × 10 ²⁰ / cm ³ or less. In this case, the etching selectivity between the interlayer insulating film 120 and the high-concentration impurity region 113b becomes higher as the phosphorus concentration becomes deeper than 10 nm. That is, since the etching rate of the high concentration impurity region 113b is reduced, the etching is suppressed. Therefore, as shown in FIG. 4A, over-etching of the high concentration impurity region 113b is stopped at a depth of about 22 nm.

  On the other hand, in the case of this comparative example, the high concentration impurity region 513b has the maximum phosphorus concentration near the depth of 20 nm, and finally the phosphorus concentration starts to decrease in the region deeper than 20 nm. A much slower decline. Therefore, unlike the case of Embodiment 1, the etching selectivity between interlayer insulating film 520 and high concentration impurity region 513b is low, and the etching of high concentration impurity region 513b is not suppressed. Therefore, as shown in FIG. 5A, there is a problem that the high concentration impurity region 513b is over-etched to a depth much deeper than 22 nm.

(Embodiment 2)
This embodiment is an example in which a TFT is manufactured by a method different from that in Embodiment 1.

  Doping for forming a high concentration impurity region (source region and drain region) in the region of the semiconductor film opened by the contact hole is not performed before the contact hole is formed, but is performed after the contact hole is formed. If it does so, the etching selectivity of an interlayer insulation film and a semiconductor film is high, and it becomes easy to stop etching at those interfaces. That is, when the contact hole is formed, the interlayer insulating film can be completely removed without overetching the semiconductor film. A specific example will be described below.

  In accordance with Embodiment Mode 1, the process up to the step of exposing part of the film 113 mainly including island-shaped silicon (part of the low-concentration impurity region 113a) shown in FIG. A further part of the exposed part, that is, a region to be opened later by a contact hole is covered with a mask such as a resist mask. Then, phosphorus doping is performed on the film 113 containing island-like silicon as a main component under “Condition B” employed in the comparative example, whereby a high concentration impurity region 613b is formed (FIG. 6A). On the other hand, the high concentration impurity region 613b is not formed in a region covered with a mask such as a resist mask. The reason for doping phosphorus under “Condition B” is to reduce the sheet resistance of the high concentration impurity region 613b. Doping may be performed not on “Condition B” but on “Condition A” employed in the first embodiment. After that, the used resist mask or the like is removed, and the interlayer insulating film 120 described in Embodiment 1 is formed.

The interlayer insulating film 120 is dry-etched to form a contact hole 621 (FIG. 6B). At this time, the high concentration impurity region 613 b is not formed at the bottom of the contact hole 621. In this embodiment mode, a condition where the etching selectivity of the interlayer insulating film 120 and the film 113 (low-concentration impurity region 113a) mainly containing island-like silicon is high, for example, a mixed gas of helium (He) and CHF ₃ is used. The mixture ratio is CHF ₃ / He = 56 sccm / 144 sccm, and dry etching is performed at a pressure of 7.5 Pa. Dry etching is performed so that the time required for the third step of “Condition C” described in Embodiment 1 is shortened so that the island-shaped silicon-based film 113 (low-concentration impurity region 113a) is not over-etched. You may do. In the case where the contact hole 621 is formed to have a size that exposes all the regions where the high-concentration impurity regions 613b shown in FIG. 6C are exposed, it is covered with a mask such as a resist mask as described above and doped with phosphorus. There is no need for a process to perform the above.

  Further, in order to form a high-concentration impurity region 613b in the film 113 (low-concentration impurity region 113a) containing island-shaped silicon as a main component through this contact hole 621, phosphorus doping is performed under “condition B” (FIG. 6 (C)). Doping may be performed under “condition A” instead of “condition B”. Thereafter, the doped impurity element is activated.

  After that, a wiring or an electrode 122 is formed in the contact hole 621 as described in Embodiment Mode 1 (FIG. 6D).

  Although the process of this embodiment is more complicated than that of Embodiment 1, since phosphorus doping can be performed under “condition B”, the sheet resistance of the high-concentration impurity region 613b can be lowered and the high-concentration impurity region 613b can be reduced. It is characterized in that it is difficult or not overetched. However, also in this embodiment, the contact hole 621 may be formed so that the high-concentration impurity region 613b is over-etched as in the first embodiment.

  Examples of a liquid crystal display device and an electroluminescence display device are shown as display devices manufactured using the TFT according to the invention disclosed in this specification. Hereinafter, in this specification, the electroluminescence display device is referred to as an EL display device.

  FIG. 7 shows an example of a cross section of a liquid crystal display device. A liquid crystal layer 704 is provided between the first substrate 701 and the second substrate 702, and these substrates are bonded to each other with a sealant 700. At least a pixel portion 703 is formed on the first substrate 701, and at least a coloring layer 705 is formed on the second substrate 702 by a printing method or the like. The colored layer 705 is necessary when performing color display. In the case of the RGB method, a colored layer corresponding to each color of red, green, and blue is provided corresponding to each pixel. Polarizers 706 and 707 are provided outside the first substrate 701 and the second substrate 702, respectively. In addition, a protective film 716 is formed on the surface of the polarizing plate 707 to reduce external impact.

  A TFT which is a semiconductor element is formed in the pixel portion 703 corresponding to each pixel, and the TFT according to the invention disclosed in this specification can be applied. By doing so, since the TFT of each pixel operates normally without malfunction, defects in the display image such as point defects and line defects can be reduced.

  A wiring substrate 710 is connected to a connection terminal 708 provided on the first substrate 701 through an FPC 709. A driver circuit 711 (IC chip or the like) is provided in the FPC 709 or the connection wiring, and an external circuit 712 such as a control circuit or a power supply circuit is provided in the wiring substrate 710.

  The cold cathode tube 713, the reflection plate 714, and the optical film 715 are a backlight unit, and these serve as a light source. The first substrate 701, the second substrate 702, the light source, the wiring substrate 710, and the FPC 709 are held and protected by a bezel 717.

  8A, 8B, and 8C are schematic views of a display device such as a liquid crystal display device or an EL display device as viewed from above.

  In FIG. 8A, a pixel portion 801 in which a plurality of pixels 802 are arranged in a matrix, a scanning line side input terminal 803, and a signal line side input terminal 804 are formed over a substrate 800. The pixels 802 are arranged in a matrix form by intersecting a scanning line extending from the scanning line side input terminal 803 and a signal line extending from the signal line side input terminal 804. Each of the plurality of pixels 802 includes a TFT as a switching element and a pixel electrode. FIG. 8A illustrates an example in which signals input to the scan line and the signal line are controlled by a driver circuit connected to the outside of the substrate through the scan line side input terminal 803 and the signal line side input terminal 804. A COG method in which a driving circuit is formed on a substrate may be used.

  FIG. 8B illustrates an example in which the pixel portion 811 and the scan line driver circuit 812 are formed over the substrate 810. Reference numeral 814 denotes a signal line side input terminal similar to that shown in FIG. FIG. 8C illustrates an example in which the pixel portion 821, the scan line driver circuit 822, and the signal line driver circuit 824 are formed over the substrate 820.

  The scan line driver circuit 812 illustrated in FIG. 8B and the scan line driver circuit 822 and the signal line driver circuit 824 illustrated in FIG. 8C are formed of TFTs and may be formed at the same time as the TFTs provided in the pixel portion. it can. However, since the scanning line driver circuit and the signal line driver circuit are required to operate at high speed, a TFT using a crystalline semiconductor film as a channel formation region instead of an amorphous semiconductor film is used as a TFT used for these. Good.

  The TFT according to the invention disclosed in this specification includes a scan line driver circuit 812 illustrated in FIG. 8B as well as the pixel portion illustrated in FIG. 8A, FIG. 8B, and FIG. The yield can be improved by employing the scan line driver circuit 822 and the signal line driver circuit 824 shown in FIG.

  FIG. 9 shows an example of a cross section of an EL display device. This EL display device includes a terminal portion 900, a driver circuit portion 901, and a pixel portion 902. The driver circuit portion 901 includes a P-channel TFT 910 and an N-channel TFT 911. The pixel portion 902 includes a switching TFT 912 and a driving TFT. A TFT 913 is included. The driver circuit portion 901 and the pixel portion 902 are both formed over the same substrate.

  FIG. 9 shows a so-called multi-gate structure as the switching TFT 912 and the driving TFT 913, which is intended to reduce the off-current of the TFT. The switching TFT 912 can be an N-channel TFT, for example, and the driving TFT 913 can be a P-channel TFT, for example. The gate electrode of the switching TFT 912 is electrically connected to the scanning line, and the electrode or wiring connected to the source region or drain region of the switching TFT 912 through the contact hole is electrically connected to the signal line.

  The electrode or wiring connected to the source region or drain region of the driving TFT 913 through a contact hole provided in the interlayer insulating film is electrically connected to the light emitting element 914 in which the anode, the cathode, and the light emitting layer are stacked therebetween. Connected. FIG. 9 shows a configuration in which the electrode or wiring is provided on the interlayer insulating film, another interlayer insulating film is provided thereon, and the light-emitting element 914 is formed thereon. It is not limited. A transparent conductive film formed on one or both of the cathode and the anode of the light-emitting element 914 by a sputtering method or a printing method (a droplet discharge method such as an inkjet, a screen printing method, etc.) such as an ITO (Indium Tin Oxide) film. Can be used. The material constituting the transparent conductive film is not limited to the ITO, but may be another material having translucency and conductivity. By using a transparent conductive film for both the cathode and the anode, light from the light emitting layer can be emitted upward and downward, so that images can be viewed from both the front and back surfaces of the EL display device.

  The TFT according to the invention disclosed in this specification can be applied to the pixel portion 902. By doing so, display image defects such as point defects and line defects can be reduced as in the case of the liquid crystal display device. Further, by applying not only to the pixel portion 902 but also the driver circuit portion 901, the yield can be improved.

  The display device described in this embodiment is mounted on various electronic devices. Examples of such electronic devices include television receivers, cameras (video cameras, digital cameras, etc.), navigation systems, sound playback devices (car audio, audio components, etc.), personal computers, game devices, portable information terminals (mobile computers). A display device capable of playing back a recording medium such as a digital versatile disc (DVD) and displaying the image. And the like). The display device described in this embodiment is mounted on a display portion of these electronic devices.

  FIG. 10A illustrates an example of a television receiver, which includes a housing 1001, a display portion 1002, a speaker 1003, an operation portion 1004, a video input terminal 1005, and the like. A display device such as a liquid crystal display device or an EL display device manufactured using a TFT according to the invention disclosed in this specification is applied to the display portion 1002.

  10B and 10C illustrate an example of a digital camera. FIG. 10B is a front view of the digital camera. 1011 is a release button, 1012 is a main switch, 1013 is a finder window, 1014 is a strobe, 1015 is a lens, and 1016 is a housing. FIG. 10C is a view of the digital camera as viewed from the rear. Reference numeral 1017 denotes a viewfinder eyepiece window, 1018 denotes a display portion, and 1019 and 1020 denote operation buttons. A display device such as a liquid crystal display device or an EL display device manufactured using the TFT according to the invention disclosed in this specification is applied to the display portion 1018.

  FIG. 10D illustrates an example of a mobile phone. This cellular phone includes a main body (A) 1021 provided with operation switches 1024, a microphone 1025, and the like, and a main body (B) 1022 provided with a display panel (A) 1028, a display panel (B) 1029, a speaker 1026, and the like. The main body (A) 1021 and the main body (B) 1022 are connected to each other by a hinge 1030 so as to be opened and closed. The display panel (A) 1028 and the display panel (B) 1029 are housed in the housing 1023 of the main body (B) 1022 together with the circuit board 1027. The pixel portions of the display panel (A) 1028 and the display panel (B) 1029 are arranged so as to be seen from an opening window formed in the housing 1023. Display devices such as a liquid crystal display device and an EL display device manufactured using the TFT according to the invention disclosed in this specification are applied to the display panel (A) 1028 and the display panel (B) 1029.

  In the display panel (A) 1028 and the display panel (B) 1029, specifications such as the number of pixels can be set as appropriate in accordance with the function of the cellular phone. For example, the display panel (A) 1028 can be combined as a main screen and the display panel (B) 1029 can be combined as a sub-screen.

  By using such a display panel, the display panel (A) 1028 is a high-definition color display screen for displaying characters and images, and the display panel (B) 1029 is a single-color information display screen for displaying character information. be able to. In particular, by increasing the definition of the display panel (B) 1029 as an active matrix type, various character information can be displayed and the information display density per screen can be improved. For example, the display panel (A) 1028 is 2 to 2.5 inches with 64 gradations and 260,000 colors of QVGA (320 dots × 240 dots), and the display panel (B) 1029 is 2 to 8 gradations with a single color. Romaji, Hiragana, Katakana, numbers, kanji, etc. can be displayed as a high-definition panel of 180 to 220 ppi.

  The mobile phone according to the present embodiment can be transformed into various modes according to the function and application. For example, an imaging element may be incorporated in a part such as a hinge 1030 to form a mobile phone with a camera. Alternatively, the operation switches 1024, the display panel (A) 1028, and the display panel (B) 1029 may be housed in one housing.

  This embodiment can be implemented in combination with Embodiment Mode 1 and Embodiment Mode 2.

  The transistor according to the invention disclosed in this specification can be used for a semiconductor device such as an integrated circuit or a non-contact type integrated circuit device (also referred to as a wireless IC tag or an RFID (Radio Frequency Identification) tag). This non-contact type integrated circuit device (hereinafter referred to as a wireless IC tag in this specification) is affixed to various electronic devices as shown in the first embodiment, thereby clarifying the distribution route of the electronic device. Can be.

  FIG. 11A and FIG. 11B are block diagrams illustrating an example of a wireless IC tag. The wireless IC tag 1100 can exchange data without contact, and includes a power supply circuit 1101, a clock generation circuit 1102, a data demodulation / modulation circuit 1103, a control circuit 1104, an interface circuit 1105, a storage circuit 1106, a bus 1107, and An antenna 1108 is included. FIG. 11B illustrates a case where the CPU 1121 is further provided in FIG.

  The power supply circuit 1101 generates a power supply based on the AC signal input from the antenna 1108. The clock generation circuit 1102 generates a clock signal based on the signal input from the antenna 1108. The data demodulation / modulation circuit 1103 demodulates / modulates data communicated with the reader / writer 1109. The control circuit 1104 controls the memory circuit 1106. The antenna 1108 performs signal reception and data transmission.

  As a material constituting the antenna 1108, for example, gold, silver, copper, aluminum, ferrite, ceramics, or the like can be used. The shape of the antenna 1108 can be, for example, a dipole type, a ring-shaped loop type, a spiral spiral type, or a flat rectangular parallelepiped patch type.

  A circuit included in the wireless IC tag 1100 can be manufactured using a transistor according to the invention disclosed in this specification. The antenna 1108 is provided so as to be electrically connected to the transistor. The antenna 1108 can be manufactured together with a transistor over a substrate by a combination of a sputtering method, a CVD method, and a photolithography process, a screen printing method that does not require a photolithography process, a droplet discharge method, or the like. Further, an antenna 1108 can be electrically connected to the transistor by using an off-the-shelf component as the antenna 1108 and bonding the substrate to which the transistor is formed with a conductive paste or the like.

  As the memory circuit 1106, DRAM, SRAM, mask ROM, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), flash memory, organic memory, or the like can be used. An organic memory has a structure in which an organic compound layer is provided between a pair of electrodes, or a layer in which an organic compound and an inorganic compound are provided between a pair of electrodes. The organic memory is used for the memory circuit 1106 of the wireless IC tag. Therefore, it contributes to miniaturization, thinning, and weight reduction of the wireless IC tag.

  Since the manufacturing cost of a wireless IC tag is higher than that of a conventional barcode, it is necessary to reduce the cost. By manufacturing a wireless IC tag using the invention disclosed in this specification, a yield can be improved and supply can be performed at a low price, and variation in performance can be reduced with high quality.

  FIGS. 12A to 12E show usage examples of wireless IC tags. A wireless IC tag is attached to the recording medium 1201 itself on which information is recorded or a case in which the recording medium 1201 is stored, a book 1202, a product package 1203, clothing 1204, a glass or plastic bottle 1205, and the like. It can be used for sales, inventory, lending and return management, prevention of loss or theft, collection, and other purposes. In each of FIGS. 12A to 12E, an example of a wireless IC tag attachment position 1200 is shown.

  This embodiment can be implemented in combination with Embodiment Mode 1, Embodiment Mode 2, or Example 1.

Sectional drawing which shows the preparation process of TFT. The graph which shows concentration distribution in the depth direction of phosphorus. Sectional drawing which shows the preparation process of TFT. Sectional drawing of a contact part, and the graph which shows contact chain resistance. Sectional drawing of a contact part, and the graph which shows contact chain resistance. Sectional drawing which shows the preparation process of TFT. Sectional drawing which shows a liquid crystal display device. The schematic diagram which looked at the display from the upper surface. Sectional drawing which shows an electroluminescent display apparatus. FIG. 9 illustrates an electronic device. The block diagram which shows a radio | wireless IC tag. The figure which shows the usage example of a radio | wireless IC tag.

Explanation of symbols

111 Substrate 112 Underlying insulating film 113 Film 113a mainly composed of island-like silicon Low concentration impurity region 113b High concentration impurity region 113c First region 113d Second region 114 First insulating film 116 Electrode 116a Pattern 116b Pattern 117 Insulator 118 Insulating film 120 Interlayer insulating film 121 Contact hole 122 Wiring or electrode 513b High concentration impurity region 520 Interlayer insulating film 522 Wiring or electrode 613b High concentration impurity region 621 Contact hole 701 First substrate 702 Second substrate 703 Pixel portion 704 Liquid crystal layer 705 Colored layer 706 Polarizing plate 707 Polarizing plate 708 Connection terminal 709 FPC
710 Wiring board 711 Drive circuit 712 External circuit 713 Cold cathode tube 714 Reflector 715 Optical film 716 Protective film 717 Bezel 800 Substrate 801 Pixel portion 802 Pixel 803 Scan line side input terminal 804 Signal line side input terminal 810 Substrate 811 Pixel portion 812 Scan Line driver circuit 814 Signal line input terminal 820 Substrate 821 Pixel unit 822 Scan line driver circuit 824 Signal line driver circuit 900 Terminal unit 901 Driver circuit unit 902 Pixel unit 910 P-channel TFT
911 N-channel TFT
912 TFT for switching
913 Driving TFT
914 Light emitting element

Claims (12)

A semiconductor film containing an impurity element imparting P-type or N-type;
An insulating film formed on the semiconductor film;
Having at least an electrode or a wiring electrically connected to the semiconductor film through a contact hole formed in the insulating film;
In the semiconductor film, the concentration of the impurity element contained in a region deeper than a predetermined depth is in the first range, and the concentration of the impurity element contained in a region shallower than the predetermined depth is the first concentration. A second range higher than the range,
The transistor characterized in that the concentration of the impurity element is in the first range in a region deeper than a portion of the semiconductor film in contact with the electrode or the wiring. A source region and a drain region containing an impurity element imparting P-type or N-type;
An insulating film formed on the source region and the drain region;
An electrode or a wiring electrically connected to at least one of the source region and the drain region through a contact hole formed in the insulating film;
In the source region and the drain region, the concentration of the impurity element contained in a region deeper than a predetermined depth is a first range, and the concentration of the impurity element contained in a region shallower than the predetermined depth is A second range higher than the first range;
The transistor characterized in that the concentration of the impurity element is in the first range in a region deeper than a portion in contact with the electrode or the wiring in one of the source region and the drain region. A semiconductor film in which a source region and a drain region containing an impurity element imparting P-type or N-type are formed;
An insulating film formed on the semiconductor film;
An electrode or a wiring electrically connected to at least one of the source region and the drain region through a contact hole formed in the insulating film;
In the source region and the drain region, the concentration of the impurity element contained in a region deeper than a predetermined depth is a first range, and the concentration of the impurity element contained in a region shallower than the predetermined depth is A second range higher than the first range;
The concentration of the impurity element is the first range in the first region, which is directly below the portion in contact with the electrode or the wiring, in any one of the source region and the drain region,
The thickness of the first region is thinner than the thickness of the second region of either the source region or the drain region excluding the first region, and the lower limit is 50% of the thickness of the second region. A transistor characterized by comprising:   4. The transistor according to claim 1, wherein the impurity element is phosphorus, and the semiconductor film is a film containing silicon as a main component.   3. The transistor according to claim 2, wherein the impurity element is phosphorus, and the source region and the drain region are formed in a silicon substrate. 5. The first range is 1 × 10 ²⁰ / cm ³ or less, and the second range is more than 1 × 10 ²⁰ / cm ³ and 1 × 10 ²¹ / cm according to claim 1. A transistor having ³ or less.   The transistor according to any one of claims 1 to 4 and claim 6 is a thin film transistor, and a liquid crystal display device using the thin film transistor in at least a pixel.   The transistor according to any one of claims 1 to 4 and claim 6 is a thin film transistor, and an electroluminescence display device using the thin film transistor in at least a pixel.   The transistor according to any one of claims 1 to 4 and claim 6 is a thin film transistor, and an electronic device on which a liquid crystal display device using the thin film transistor for at least a pixel is mounted.   The transistor according to any one of claims 1 to 4 and claim 6 is a thin film transistor, and an electronic device on which an electroluminescence display device using the thin film transistor for at least a pixel is mounted.   A semiconductor device using the transistor according to claim 1.   A wireless IC tag using the transistor according to any one of claims 1 to 6.