JP4713200B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device including a circuit having a thin film transistor over a substrate having an insulating surface, and a manufacturing method thereof.

  A display device in which a pixel portion is formed by arranging active elements is called an active matrix display device, and a liquid crystal display device, an electroluminescence (hereinafter, also referred to as EL) display device, and the like have been developed. As the active element, an insulated gate transistor is used, and a thin film transistor (hereinafter also referred to as TFT) is preferably used. In a TFT, a semiconductor film is formed on a substrate such as glass by a vapor deposition method or the like, and a channel formation region, a source region, a drain region, or the like is formed using the semiconductor film. For the semiconductor film, a material mainly containing silicon such as silicon or silicon germanium is preferably used. Semiconductor films can be classified into amorphous semiconductor films and crystalline semiconductor films.

In a TFT in which an active layer is formed of an amorphous semiconductor film, it is almost impossible to obtain a field effect mobility of 10 cm ² / V · sec or more due to electronic physical factors due to the amorphous structure. Therefore, in an active matrix liquid crystal display device, a driving circuit for displaying an image can be formed even though it can be used as a switching element (hereinafter also referred to as a pixel TFT) for driving a liquid crystal in a pixel portion. It is impossible. Therefore, a technology for mounting a driver IC or the like using a TAB (Tape automated bonding) method or a COG (Chip on Glass) method is used for the drive circuit.

  On the other hand, in a TFT having a crystalline semiconductor film as an active layer, high field-effect mobility can be obtained, so that various functional circuits can be formed and driven, in addition to the pixel TFT on the same glass substrate. It is possible to realize a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and the like. The drive circuit is formed on the basis of a CMOS circuit composed of an n-channel TFT and a p-channel TFT. In order to promote weight reduction and thinning in liquid crystal display devices and EL display devices based on the mounting technology of such a drive circuit, a crystalline semiconductor film in which a drive circuit can be integrally formed on the same substrate in addition to a pixel portion It is considered that a TFT having an active layer is suitable.

  As described above, in order to simultaneously form the pixel portion and the driving circuit on the same substrate, it is necessary to form TFTs corresponding to the functions of various circuits. This is because the operating conditions are not necessarily the same between the pixel TFT and the TFT of the driving circuit, and the characteristics required for the TFT are also different. A pixel TFT composed of an n-channel TFT is driven by applying a voltage to a liquid crystal as a switching element. Since the liquid crystal is driven by alternating current, a method called frame inversion driving is often employed. The pixel TFT is required to have a sufficiently low off-current value in order to hold the charge accumulated in the liquid crystal layer during one frame period. On the other hand, since a high drive voltage is applied to the buffer circuit of the drive circuit and the like, it is necessary to increase the breakdown voltage so as not to break even when a high voltage is applied. Further, it is necessary to secure a sufficient on-current value in order to increase the on-current driving capability.

  As a structure of a TFT for reducing the off-current value, there is a structure in which a low concentration drain region (hereinafter also referred to as an LDD region) is provided. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source region and a drain region to which an impurity element is added at a high concentration. As a means for preventing the deterioration of the on-current value due to hot carriers, there is a so-called GOLD (Gate-drain Overlapped LDD) structure in which an LDD region is disposed so as to overlap with a gate electrode through a gate insulating film. With such a structure, a high electric field in the vicinity of the drain is relieved, and a decrease in on-current value due to hot carriers can be reduced. Note that a region where the LDD region is not disposed so as to overlap the gate electrode through the gate insulating film is also referred to as a Loff region, and a region where the LDD region is disposed is also referred to as a Lov region.

  Here, the Loff region has a high effect of suppressing the off-current value, but has a low effect of relaxing the electric field in the vicinity of the drain and preventing the decrease of the on-current value due to hot carriers. On the other hand, the Lov region relaxes the electric field in the vicinity of the drain and is effective in preventing a decrease in the on-current value, but has a low effect of suppressing the off-current value. Therefore, it is necessary to manufacture a TFT having a structure having the required TFT characteristics for each of various circuits.

  However, in order to manufacture TFTs corresponding to the functions of various circuits, there is a problem that the structure becomes complicated and the number of processes increases. An increase in the number of processes not only increases the manufacturing cost but also decreases the manufacturing yield.

  The present invention is a technique for solving such a problem. In a semiconductor device typified by an active matrix display device manufactured using TFTs, the structure of TFTs arranged in various circuits is changed. An object of the present invention is to improve the operating characteristics and reliability of the semiconductor device by making it appropriate according to the function, and to reduce the number of steps to reduce the manufacturing cost and the yield.

  In the present invention, a conductive film to be a gate electrode is provided on an island-shaped semiconductor layer through a gate insulating film, a tapered resist is formed on the conductive film, and the conductive film is etched together with the resist to taper. A gate electrode having a shape is formed. At this time, the resist is also reduced by etching. Then, a high concentration impurity is added using the tapered gate electrode as a mask to form a source region and a drain region. After that, the tapered gate electrode is etched in the vertical direction using a resist provided for forming the tapered gate electrode as a mask. Thus, the gate electrode from which the taper portion has been removed by etching is formed. Using this gate electrode as a mask, a low concentration impurity is added to the semiconductor layer to form an LDD region.

  In addition, multiple times of gate electrode dry etching, formation of a silicon oxide film or silicon nitride film for sidewalls, and sidewall formation by dry etching using an etch back method of a silicon oxide film or silicon nitride film, multiple times An LDD region is formed in the semiconductor layer by impurity implantation into the semiconductor layer, and a fine TFT having both a Lov region, a Loff region, and a Lov region and a Loff region can be formed.

The first configuration disclosed in the present invention is:
A first step of forming a gate insulating film so as to cover the island-shaped semiconductor layer;
A second step of forming a first conductive film to be a first gate electrode on the gate insulating film;
A third step of forming a second conductive film to be a second gate electrode on the first conductive film;
A fourth step of forming a tapered resist on the second conductive film;
Etching the resist and the second conductive film to form a second gate electrode having a tapered shape;
A sixth step of doping the semiconductor layer with an impurity element of one conductivity type after the fifth step;
A seventh step of vertically etching the second gate electrode using the resist as a mask;
An eighth step of doping the semiconductor layer with an impurity element of one conductivity type after the seventh step;
A ninth step of removing the resist;
A tenth step of forming a silicon compound so as to cover the second gate electrode;
An eleventh step of etching the silicon compound to form sidewalls at both ends of the second gate electrode;
Etching the first conductive film using the second gate electrode and the sidewall as a mask to form a first gate electrode,
The method for manufacturing a semiconductor device is characterized in that the concentration of the one conductivity type impurity element doped in the eighth step is lower than the concentration of the one conductivity type impurity element doped in the sixth step.

  When a semiconductor device is manufactured by the manufacturing method of this structure, a low-concentration impurity region (Lightly Doped Drain region: hereinafter also referred to as an LDD region) of a semiconductor layer is formed as a Loff region that does not overlap with a Lov region overlapping with a gate electrode of a thin film transistor. The region has a so-called GOLD (Gate Overlapped LDD) structure.

The second configuration disclosed in the present invention is:
A first step of forming a gate insulating film so as to cover the island-shaped semiconductor layer;
A second step of forming a first conductive film to be a first gate electrode on the gate insulating film;
A third step of forming a second conductive film to be a second gate electrode on the first conductive film;
A fourth step of forming a tapered resist on the second conductive film;
Etching the resist and the second conductive film to form a second gate electrode having a tapered shape;
A sixth step of doping the semiconductor layer with an impurity element of one conductivity type after the fifth step;
A seventh step of vertically etching the second gate electrode using the resist as a mask;
An eighth step of removing the resist;
A ninth step of doping the semiconductor layer with an impurity element of one conductivity type after the eighth step;
A tenth step of forming a silicon compound so as to cover the second gate electrode;
An eleventh step of etching the silicon compound to form sidewalls at both ends of the second gate electrode;
Etching the first conductive film using the second gate electrode and the sidewall as a mask to form a first gate electrode,
The method for manufacturing a semiconductor device is characterized in that the concentration of the one conductivity type impurity element doped in the ninth step is lower than the concentration of the one conductivity type impurity element doped in the sixth step.

  This configuration is different from the first configuration in the order of the etching removal process of the tapered resist, and similarly to the first configuration, there is a Loff region where the LDD of the semiconductor layer does not overlap with the Lov overlapping with the gate electrode of the thin film transistor. The Lov region has a GOLD structure.

The third configuration disclosed in the present invention is:
A first step of forming a gate insulating film so as to cover the island-shaped semiconductor layer;
A second step of forming a first conductive film to be a first gate electrode on the gate insulating film;
A third step of forming a second conductive film to be a second gate electrode on the first conductive film;
A fourth step of forming a tapered resist on the second conductive film;
Etching the resist, the first conductive film, and the second conductive film to form a first gate electrode and a second gate electrode having a tapered shape;
A sixth step of doping the semiconductor layer with an impurity element of one conductivity type after the fifth step;
A seventh step of vertically etching the second gate electrode using the resist as a mask;
An eighth step of doping the semiconductor layer with an impurity element of one conductivity type after the seventh step;
A ninth step of removing the resist;
A tenth step of forming a silicon compound so as to cover the second gate electrode;
An eleventh step of etching the silicon compound to form sidewalls at both ends of the second gate electrode;
And a twelfth step of etching the first gate electrode using the second gate electrode and the sidewall as a mask,
The method for manufacturing a semiconductor device is characterized in that the concentration of the one conductivity type impurity element doped in the eighth step is lower than the concentration of the one conductivity type impurity element doped in the sixth step.

  When a semiconductor device is manufactured by the manufacturing method of this configuration, Loff in which the LDD of the semiconductor layer does not overlap with Lov that overlaps with the gate electrode of the thin film transistor is formed, and Lov has a GOLD structure.

The fourth configuration disclosed in the present invention is:
A first step of forming a gate insulating film so as to cover the island-shaped semiconductor layer;
A second step of forming a first conductive film to be a first gate electrode on the gate insulating film;
A third step of forming a second conductive film to be a second gate electrode on the first conductive film;
A fourth step of forming a tapered resist on the second conductive film;
Etching the resist, the first conductive film, and the second conductive film to form a first gate electrode and a second gate electrode having a tapered shape;
A sixth step of doping the semiconductor layer with an impurity element of one conductivity type after the fifth step;
A seventh step of vertically etching the second gate electrode using the resist as a mask;
An eighth step of removing the resist;
A ninth step of doping the semiconductor layer with an impurity element of one conductivity type after the eighth step;
A tenth step of forming a silicon compound so as to cover the second gate electrode;
An eleventh step of etching the silicon compound to form sidewalls at both ends of the second gate electrode;
And a twelfth step of etching the first gate electrode using the second gate electrode and the sidewall as a mask,
The method for manufacturing a semiconductor device is characterized in that the concentration of the one conductivity type impurity element doped in the eighth step is lower than the concentration of the one conductivity type impurity element doped in the sixth step.

  This configuration is different from the third configuration in the order of the etching removal process of the tapered resist, and similarly to the configuration 1, a Loff in which the LDD of the semiconductor layer does not overlap with the Lov overlapping with the gate electrode of the thin film transistor is formed. Lov has a GOLD structure.

  In a fifth configuration disclosed in the present invention, the width in the channel length direction of the sidewall is shorter than the width in the channel length direction of the tapered portion of the second electrode etched vertically in the seventh step in the above configuration. This is a method for manufacturing a semiconductor device.

  A sixth structure disclosed in the present invention is a method for manufacturing a semiconductor device, characterized in that, in the above structure, any one of silicon oxide, silicon nitride, and silicon oxynitride is used as a silicon compound.

The seventh configuration disclosed in the present invention is:
A first step of forming a gate insulating film so as to cover the island-shaped semiconductor layer;
A second step of forming a first conductive film to be a first gate electrode on the gate insulating film;
A third step of forming a second conductive film to be a second gate electrode on the first conductive film;
A fourth step of forming a tapered resist on the second conductive film;
Etching the resist, the first conductive film, and the second conductive film to form a first gate electrode and a second gate electrode having a tapered shape;
A sixth step of doping the semiconductor layer with an impurity element of one conductivity type after the fifth step;
A seventh step of vertically etching the second gate electrode using the resist as a mask;
And an eighth step of doping the semiconductor layer with an impurity element of one conductivity type after the seventh step,
The method for manufacturing a semiconductor device is characterized in that the concentration of the one conductivity type impurity element doped in the eighth step is lower than the concentration of the one conductivity type impurity element doped in the sixth step.

  When a semiconductor device is manufactured by the manufacturing method of this structure, a Loff region where the LDD of the semiconductor layer does not overlap with the gate electrode of the thin film transistor is formed.

The eighth configuration disclosed in the present invention is:
A first step of forming a gate insulating film so as to cover the island-shaped semiconductor layer;
A second step of forming a first conductive film to be a first gate electrode on the gate insulating film;
A third step of forming a second conductive film to be a second gate electrode on the first conductive film;
A fourth step of forming a tapered resist on the second conductive film;
Etching the resist, the first conductive film, and the second conductive film to form a first gate electrode and a second gate electrode having a tapered shape;
A sixth step of doping the semiconductor layer with an impurity element of one conductivity type after the fifth step;
A seventh step of vertically etching the first gate electrode and the second gate electrode using the resist as a mask;
And an eighth step of doping the semiconductor layer with an impurity element of one conductivity type after the seventh step,
A method for manufacturing a semiconductor device, wherein the concentration of the one conductivity type impurity element doped in the eighth step is lower than the concentration of the one conductivity type impurity element doped in the sixth step.

  When a semiconductor device is manufactured by the manufacturing method of this structure, a Lov region where the LDD of the semiconductor layer overlaps with the gate electrode of the thin film transistor is formed, and the Lov region has a GOLD structure.

The configuration of the semiconductor device disclosed in the present invention is as follows.
A source region, a drain region, and a channel formation region are provided over a substrate having an insulating surface, and an impurity region having a lower concentration than that of the source and drain regions is provided between the source and drain regions and the channel formation region. Having an island-shaped semiconductor layer comprising
It has a gate insulating film so as to cover the island-shaped semiconductor layer,
A first gate electrode on the gate insulating film;
A second gate electrode having a length in the channel length direction shorter than the first gate electrode on the first gate electrode;
The second gate electrode has sidewalls made of a silicon compound at both ends in the channel length direction,
The first gate electrode overlaps with a part of the low concentration impurity region through the gate insulating film, and the length of the first gate electrode overlapping the low concentration impurity region and the length of the sidewall coincide with each other in the channel length direction. It is a semiconductor device characterized by the above.

  Note that the semiconductor device here includes a liquid crystal display device, a display device in which an electroluminescent light emitting element and a TFT are connected (hereinafter also referred to as an EL display device), and the like.

  By using the present invention, TFTs corresponding to the functions of various circuits can be manufactured in a semiconductor device in which a plurality of functional circuits are formed over the same substrate. Further, when a thin film transistor having a Lov region or a Loff region is manufactured, it is not necessary to newly provide a resist mask, so that the number of steps can be reduced, and the yield can be improved and the manufacturing process cost can be reduced.

  Further, in the present invention, etching is performed in the vertical direction by using the resist mask used when the tapered gate electrode is manufactured, and the LDD region is accurately formed in the semiconductor layer located under the tapered portion of the gate electrode removed by etching. be able to.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

(Embodiment 1)
Hereinafter, a method for manufacturing a semiconductor device according to Embodiment 1 will be described with reference to FIGS. 1A to 1D and FIGS. Note that the thin film transistor used for the semiconductor device manufactured in this embodiment includes a Lov region where the gate electrode overlaps with the LDD region of the semiconductor layer, and a Loff region which does not overlap.

  First, the base insulating film 102 is formed with a thickness of 100 to 300 nm on the substrate 101. As the substrate, a glass substrate, a quartz substrate, a plastic substrate, an insulating substrate such as a ceramic substrate, a metal substrate, a semiconductor substrate, or the like can be used.

The base insulating film can be formed by a CVD method or a sputtering method. For example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like formed by a CVD method using SiH ₄ , N ₂ O, and NH ₃ as raw materials can be applied. Moreover, you may use these lamination | stacking. Note that the base insulating film is provided in order to prevent impurities from diffusing from the substrate into the semiconductor layer. When a glass substrate or a quartz substrate is used as the substrate, the base insulating film is not necessarily formed.

  Subsequently, a semiconductor layer is formed to 10 to 100 nm. The material of the semiconductor layer can be selected according to the characteristics required for the TFT, and any of a silicon film, a germanium film, and a silicon germanium film may be used as the semiconductor layer, but an amorphous semiconductor formed by a CVD method or a sputtering method. It is preferable to use a material crystallized by thermal annealing using an electric heating furnace or laser annealing using an excimer laser. It is also possible to apply a rapid thermal annealing method (RTA method) using a halogen lamp. Alternatively, a so-called microcrystal semiconductor (μc-Si: H) that can be formed by a CVD method may be used. This semiconductor layer is patterned to form an island-shaped semiconductor layer 103.

  Here, if both the base insulating film 102 and the semiconductor layer 103 are formed by a plasma CVD method, the base insulating film and the semiconductor layer may be continuously formed in a vacuum. Since the surface of the base insulating film is not exposed to the air atmosphere after the formation of the base insulating film, contamination of the surface can be prevented, and variation in characteristics of the manufactured TFT can be reduced.

  Subsequently, a gate insulating film 104 is formed to have a thickness of 10 to 200 nm so as to cover the island-shaped semiconductor layer 103. As the gate insulating film 104, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like formed by a CVD method or a sputtering method can be used. A TFT capable of high-speed operation can be formed by forming a thin gate insulating film. However, if the gate insulating film is too thin, a leakage current increases, and TFT characteristics deteriorate. Therefore, the thickness of the gate insulating film is preferably 50 to 150 nm.

  Subsequently, a first conductive film 105 and a second conductive film 106 to be gate electrodes are formed over the gate insulating film 104. First, the first conductive film 105 is formed with a thickness of 5 to 50 nm. As the first conductive film 105, an aluminum (Al) film, a copper (Cu) film, a thin film mainly composed of aluminum or copper, a chromium (Cr) film, a tantalum (Ta) film, a tantalum nitride (TaN) film, A titanium (Ti) film, a tungsten (W) film, a molybdenum (Mo) film, or the like can be used. A second conductive film 106 is formed thereon with a thickness of 150 to 500 nm. The second conductive film 106 is preferably formed using a material that can be easily etched into a tapered shape in a later step. For example, a chromium (Cr) film, a tantalum (Ta) film, a titanium (Ti) film, a tungsten (W) film, an aluminum (Al) film, a thin film containing tantalum as a main component, or the like. However, the first conductive film 105 and the second conductive film 106 must be combined so that a selection ratio can be obtained in the mutual etching. As a combination of the first conductive film and the second conductive film that can be selected, for example, a combination of Al for the first conductive film, Ta for the second conductive film, Al for the first conductive film, and a second conductive film. A combination of Ti can be used for the film, a combination of TaN can be used for the first conductive film, and a combination of W can be used for the second conductive film. Further, in this embodiment, the gate electrode has a two-layer structure, and the impurity element is transmitted through the gate insulating film 104 and the first conductive film 105 in a later step, so that the impurity element can be easily transmitted. The first conductive film 105 is preferably formed thin.

  Subsequently, a photomask is used over the second conductive film, and a mask using a tapered resist 107 is formed using a photolithography technique (see FIG. 1A). A known method can be used for the tapered resist 107.

  Subsequently, first dry etching is performed (see FIG. 1B). In the first dry etching, the tapered resist 107 and the second conductive film 106 are etched with a low selection ratio, the tapered resist 107 and the second conductive film 106 are etched, and the second conductive film is etched. 106 is tapered to form a second gate electrode 108. At this time, the first conductive film 105 is preferably etched under etching conditions with a high selection ratio so as not to be etched. Note that the resist 107 is also etched to become the resist 109.

  The dry etching in this embodiment can be performed using an ICP (Inductively Coupled Plasma) etching method.

Subsequently, first doping is performed on the semiconductor layer under a condition that the impurity element transmits the first conductive film 105 and the gate insulating film 104, so that a source region and a drain region 110 are formed in the semiconductor layer 103 (FIG. 1 ( C)). As a doping method, an ion doping method or an ion implantation method can be used. For example, boron (B), gallium (Ga), or the like is used as an impurity element when a P-type semiconductor is manufactured, and phosphorus (P), arsenic (As), or the like is used when an N-type semiconductor is manufactured. . In the first doping, an impurity element is added to the semiconductor layer 103 at a concentration of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ .

Subsequently, second dry etching is performed. The second gate electrode 108 is vertically etched in accordance with the width of the resist 109 to form the second gate electrode 112 (see FIG. 1D). At this time, only the tapered portion 111 of the second gate electrode is etched under a condition having a high selection ratio with the first conductive film 105. As a result, the semiconductor layer having the taper width L <b> 1 covered by the tapered portion 111 of the second gate electrode is exposed through the gate insulating film 104. In other words, even if the first doping was not performed or the doping was performed, an extremely small amount of impurities (1 × 10 ¹⁶ atoms / cm ³ or less) that slightly passed through the tapered portion of the second gate electrode was added. The area is exposed. The term “exposed” is used in the sense that there is no mask portion when doping is performed, and does not necessarily mean that the semiconductor layer is exposed.

Subsequently, the resist 109 over the second gate electrode 112 is removed, and second doping is performed (see FIG. 2A). The second doping is performed under the condition that the semiconductor layer 103 can be doped through the gate insulating film 104 and the first conductive film 105 by using an impurity having the same conductivity type as the dopant of the first doping. By this second doping, a low concentration impurity region (Lightly Doped Drain region: hereinafter referred to as an LDD region) 201 is formed in a region where the first doping exposed by the second etching is not performed. At this time, the concentration of the impurity element in the LDD region 201 is set to 1 × 10 ¹⁶ to 1 × 10 ²⁰ atoms / cm ³ (preferably 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ ). Although the source region and the drain region are also doped by the second doping, the dose amount of the second doping is small compared to the dose amount of the first doping, so the influence is small. Note that the resist 109 may be removed after the second doping.

  Subsequently, a silicon compound such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed so as to cover the first conductive film 105 and the second gate electrode 112, and third dry etching is performed by an etch back method. (See FIG. 2B). Thus, sidewalls 202 made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film are formed at both ends of the second gate electrode 108. The width L2 of the sidewall 202 varies depending on the thickness of the silicon oxide film, the silicon nitride film, or the silicon oxynitride film.

  Subsequently, fourth dry etching is performed using the sidewall 202 and the second gate electrode 112 as a mask to etch the first conductive film 105, so that the first gate electrode 203 is formed (see FIG. 2C). . At this time, the first gate electrode 203 positioned outside the second gate electrode 112 and the LDD region 201 overlap, the Lov region 204 having the width L2, and the first gate electrode 203 and LDD do not overlap, and the width L3. A Loff region 205 is formed. Note that in the case where the sidewall 202 and the first conductive film 105 can be formed by the third dry etching, the fourth dry etching can be omitted.

  That is, Lov is determined by the width L1 in the channel length direction of the low-concentration impurity region determined by the first dry etching and the second dry etching, and the width L2 in the channel length direction of the sidewall formed by the third dry etching. The width L2 (Lov length) of the region 204 in the channel length direction and the width L3 (Loff length) of the Loff region 205 in the channel length direction are determined. In this process, it is necessary that L1> L2.

  By forming the Lov region 204 having a GOLD (Gate Overlapped LDD) structure, a highly reliable TFT can be provided. Further, by forming the Loff region 205, the off-state current can be reduced, and higher performance can be achieved.

  For example, when an LDD region is formed and a resist or a gate electrode serving as a doping mask is etched in the lateral direction, it is difficult to evaluate the lateral etching rate. Therefore, a stable process cannot be established. However, by tapering the gate electrode using a tapered resist as in the present embodiment, and further etching the tapered portion of the gate electrode vertically using this resist without using a new resist, The LDD region can be formed with good controllability, and a stable process can be established. In particular, it is suitable for manufacturing a semiconductor device having a fine TFT (a fine TFT formed using a stepper in a photolithography process).

  In this manner, a semiconductor device including a circuit including the thin film transistor of the present invention can be manufactured.

(Embodiment 2)
In this embodiment, a method for manufacturing a semiconductor device including a circuit including a thin film transistor in which an Lov region where an LDD region and a first gate electrode overlap with each other is formed will be described with reference to FIGS.

  A base insulating film 302, a semiconductor layer 303, a gate insulating film 304, a first conductive film, and a second conductive film are sequentially formed over the substrate 301 by a method similar to that in Embodiment 1, and then a tapered resist is formed. To do.

  Subsequently, first dry etching is performed. In Embodiment 2, when the second conductive film is etched into a tapered shape by the first dry etching to form the second gate electrode 306, the first conductive film is also etched at the same time, so that the first conductive film having the tapered shape is formed. A gate electrode 305 is also formed. The resist is also etched at the same time to become a resist 307.

  The dry etching in this embodiment can be performed using an ICP (Inductively Coupled Plasma) etching method.

Subsequently, first doping is performed, and an impurity is added to the semiconductor layer to form a source region and a drain region 308 (see FIG. 3B). At this time, the impurity element is added at a concentration of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . In the first embodiment, the first doping is performed through the first conductive film 105. However, in this embodiment, the doping can be performed without transmitting through the first gate electrode 305; When forming the drain region and the drain region, it becomes easy to dope a high concentration impurity.

  Subsequently, second dry etching is performed using the resist 307 as a mask. The second gate electrode 306 is etched by etching in the vertical direction, and the first gate electrode 305 is etched under an etching condition with a high selection ratio so as not to be etched. By this second etching, the tapered portion of the second gate electrode 306 is removed by etching (see FIG. 3C).

Subsequently, second doping is performed in the same manner as in Embodiment Mode 1 (see FIG. 3D). The LDD region 309 is formed in the semiconductor layer in a region overlapping with the first gate electrode by doping through the first gate electrode and the gate insulating film. The impurity element concentration of the LDD region 309 is 1 × 10 ¹⁶ to 1 × 10 ²⁰ atoms / cm ³ (preferably 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ ). Note that the LDD region 309 has a high concentration toward the source region and the drain region in the lower portion of the region having the tapered portion of the first gate electrode 305. Note that the resist 307 may be removed before the second doping or after the second doping.

  In this embodiment, a Lov region where the LDD region and the first gate electrode overlap is formed, and a GOLD structure is formed. A TFT having a GOLD structure has high reliability.

  For example, when an LDD region is formed and a resist or a gate electrode serving as a doping mask is etched in the lateral direction, it is difficult to evaluate the lateral etching rate. Therefore, a stable process cannot be established. However, by tapering the gate electrode using a tapered resist as in the present embodiment, and further etching the tapered portion of the gate electrode vertically using this resist without using a new resist, The LDD region can be formed with good controllability, and a stable process can be established. In particular, it is suitable for manufacturing a semiconductor device having a fine TFT (a fine TFT formed using a stepper in a photolithography process).

(Embodiment 3)
In this embodiment, a method for manufacturing a semiconductor device including a circuit including a thin film transistor in which a Lov region where an LDD region and a first gate electrode overlap with each other and a Loff region where the LDD region and the first gate electrode do not overlap with each other is formed. 3 (A) to (D) and FIG. In addition, a common code | symbol is used about a common part with FIG.

  The state shown in FIG. 3D is obtained by the same method as in the second embodiment. The steps up to here may be the same as those in Embodiment 1, but in this embodiment, a Loff region where the LDD region and the first gate electrode 305 do not overlap is formed.

  Subsequently, as described in Embodiment 1, a silicon compound such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed so as to cover the first gate electrode 305 and the second gate electrode 306. Third dry etching is performed by an etch back method (see FIG. 4A). Thus, sidewalls 401 made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film are formed at both ends of the second gate electrode 108. Here, the side wall 401 is formed so that the width L 4 in the channel length direction is narrower than the width of the LDD region 309.

  The dry etching in this embodiment can be performed using an ICP (Inductively Coupled Plasma) etching method.

  Subsequently, fourth dry etching is performed using the sidewall 401 and the second gate electrode 306 as a mask, so that the first gate electrode 305 is etched to form the first gate electrode 402 (see FIG. 4B). At this time, a Lov region 403 where the LDD region 309 overlaps with the first gate electrode 402 and a Loff region 404 where the LDD region 309 does not overlap with the first gate electrode 402 are formed. By forming the Lov region 403 having a GOLD (Gate Overlapped LDD) structure, a highly reliable TFT can be provided. Further, by forming the Loff region 404, the off-current can be reduced and the performance can be further improved. Note that in the case where the sidewall 401 can be formed and the first gate electrode 305 can be etched by the third dry etching, the fourth dry etching can be omitted.

  For example, when an LDD region is formed and a resist or a gate electrode serving as a doping mask is etched in the lateral direction, it is difficult to evaluate the lateral etching rate. Therefore, a stable process cannot be established. However, by tapering the gate electrode using a tapered resist as in the present embodiment, and further etching the tapered portion of the gate electrode vertically using this resist without using a new resist, The LDD region can be formed with good controllability, and a stable process can be established. In particular, it is suitable for manufacturing a semiconductor device having a fine TFT (a fine TFT formed using a stepper in a photolithography process).

(Embodiment 4)
In this embodiment, FIGS. 3A, 3B, and 5A illustrate a method for manufacturing a semiconductor device including a circuit including a thin film transistor in which an LDD region and a Loff region where the first gate electrode does not overlap with each other. , (B) will be described. In addition, a common code | symbol is used about a common part with FIG.

The state shown in FIG. 5A is obtained using the steps up to FIG. 3B described in Embodiment Mode 2.

  Subsequently, second dry etching is performed using the resist 307 as a mask (see FIG. 5B). The first gate electrode 305 and the second gate electrode 306 are etched by vertical etching. By this second etching, the tapered portions of the first gate electrode 305 and the second gate electrode 306 are removed by etching. Then, the first gate electrode 501 and the second gate electrode 502 from which the tapered portion is removed are obtained.

  The dry etching in this embodiment can be performed using an ICP (Inductively Coupled Plasma) etching method.

  Although the gate electrode has a two-layer structure in this embodiment mode, the gate electrode may be formed with a single gate electrode without using the two-layer structure.

Subsequently, second doping is performed in the same manner as in the first embodiment. The LDD region 503 is formed in the semiconductor layer 303 in a region that does not overlap with the first gate electrode 501 by doping through the gate insulating film 304. The impurity element concentration of the LDD region 503 is 1 × 10 ¹⁶ to 1 × 10 ²⁰ atoms / cm ³ (preferably 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ ).

  In this embodiment, a semiconductor device having a TFT characteristic in which an off-current is reduced by forming a Loff region where the LDD region and the first gate electrode do not overlap with each other can be provided.

  For example, when an LDD region is formed and a resist or a gate electrode serving as a doping mask is etched in the lateral direction, it is difficult to evaluate the lateral etching rate. Therefore, a stable process cannot be established. However, by tapering the gate electrode using a tapered resist as in the present embodiment, and further etching the tapered portion of the gate electrode vertically using this resist without using a new resist, The LDD region can be formed with good controllability, and a stable process can be established. In particular, it is suitable for manufacturing a semiconductor device having a fine TFT (a fine TFT formed using a stepper in a photolithography process).

(Embodiment 5)
In this embodiment mode, a method for manufacturing an ID chip including a TFT having a structure having a Lov region or a Loff region or a TFT having a structure having a Lov region and a Loff region will be described with reference to FIGS. Note that here, an ID chip refers to a semiconductor device that includes an antenna in addition to a semiconductor integrated circuit or a thin film integrated circuit and reads data wirelessly. The ID chip has a function as a so-called electronic tag having a function of storing and reading data.

First, the peeling layer 1302 is formed over the glass substrate 1301. As the separation layer, a layer containing silicon as a main component such as amorphous silicon or polycrystalline silicon can be used. Subsequently, a base film 1303 is formed. As the base film 1303, silicon oxide (SiO _x ), silicon nitride (SiN _x ), or silicon oxynitride (SiO _x N _y ) can be used. Island-shaped semiconductor layers 1304 a to 1304 c are formed over the base film 1303. The island-shaped semiconductor layers 1304a to 1304c are formed by forming a semiconductor layer by a CVD method or a sputtering method and then patterning the semiconductor layer. Thereafter, laser light is irradiated for crystallization. Subsequently, a gate insulating film 1305 is formed so as to cover the island-shaped semiconductor layers 1304a to 1304c. Subsequently, a first conductive film 1306 to be a first gate electrode and a second conductive film 1307 to be a second gate electrode are formed. The first conductive film and the second conductive film are combined in a selective ratio. As a combination of the first conductive film and the second conductive film, a combination of TaN is used for the first conductive film and W is used for the second conductive film. Then, tapered resists 1308a to 1308d are formed over the island-shaped semiconductor layers 1304a to 1304c and over the second conductive film 1307 (see FIG. 13A).

  Subsequently, first dry etching is performed (see FIG. 13B). In the first dry etching, etching with low selectivity is performed on the tapered resists 1308a to 1308d and the second conductive film 1307, and the tapered resists 1308a to 1308d, the second conductive film 1307, and the first conductive film 1307 are etched. The film 1306 is etched to form second gate electrodes 1310a to 1310d and first gate electrodes 1309a to 1309d. At this time, the resists 1308a to 1308d are also etched to become resists 1311a to 1311d.

  The dry etching in this embodiment can be performed using an ICP (Inductively Coupled Plasma) etching method.

Next, first doping is performed (see FIG. 13B). An n-type impurity element (phosphorus in this embodiment) is added to form impurity regions 1312a to 1312g containing phosphorus at a high concentration. The ion doping method using phosphine (PH ₃ ) is used, and the concentration of phosphorus in this region is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ (typically 2 × 10 ^{20 to} 5 × 10 ²⁰ atoms / cm 2). cm ³ ).

  Subsequently, second dry etching is performed. The second gate electrodes 1310a to 1310d are etched in the vertical direction using the resists 1311a to 1311d as a mask. Thus, second gate electrodes 1313a to 1313d are formed (see FIG. 13C).

Subsequently, second doping is performed on the island-shaped semiconductor layers 1304a to 1304c. The second doping is a semiconductor layer under the taper of the second gate electrodes 1310a to 1310d etched away by the second dry etching using the same conductivity type impurity as the dopant of the first doping, Second doping is performed on a region where the first doping is not performed (see FIG. 13C). That is, the semiconductor layer which is a region under the taper of the second gate electrodes 1310a to 1310d becomes the LDD regions 1314a to 1314d. At this time, the concentration of the impurity element in the LDD regions 1314a to 1314d is set to 1 × 10 ¹⁶ to 1 × 10 ²⁰ atoms / cm ³ (preferably 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ ). Although the source region and the drain region are also doped by the second doping, the dose amount of the second doping is small compared to the dose amount of the first doping, so the influence is small. Note that the resists 1311a to 1311d may be removed after the second doping. A region of the semiconductor layer where the first doping and the second doping are not performed, that is, a semiconductor layer located under the resists 1311a to 1311d formed by the first dry etching is a channel formation region.

Next, a resist 1401 is formed as shown in FIG. Then, third dry etching is performed on the first gate electrodes 1309a and 1309b using the second gate electrodes 1313a and 1313b and the resist 1401 as a mask. Then, the first gate electrode has a shape of 1402a and 1402b.

  Subsequently, the resist 1401 is removed, and a silicon oxide film is formed so as to cover the second gate electrodes 1313a to 1313d by a CVD method. Then, the silicon oxide film is etched back by the fourth dry etching to form sidewalls 1404a to 1404d on both sides of the second gate electrodes 1313a to 1313d. This sidewall is formed on top of the LDD regions 1314a to 1314d. The sidewalls 1404a and 1404b are on the LDD regions 1314a and 1314b through the gate insulating film 1305, and the sidewalls 1404c and 1404d are in the LDD regions 1314c and 1314d through the gate insulating film 1305 and the first gate electrodes 1309c and 1309d. Form on top.

  Then, a resist 1403 is formed, and fifth dry etching is performed using the resist 1403, the second gate electrode 1313d, and the sidewalls 1404d as masks. The first gate electrode 1309d is etched to form a first gate electrode 1405 (see FIG. 14B).

Subsequently, as shown in FIG. 14C, a passivation film 1406 is formed, and a first interlayer insulating film 1407 is further formed. As the passivation film 1406, a silicon nitride film, a silicon oxynitride film, or the like can be used. As the first interlayer insulating film 1407, an organic resin film, an inorganic insulating film, an insulating film made of a siloxane resin, or the like can be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

Subsequently, contact holes are formed in the first interlayer insulating film 1407, the passivation film 1406, and the gate insulating film 1305, and the source and drain electrodes 1408a to 1408f in contact with the impurity regions 1312a and 1312c to 1312g to be the source and drain regions. (See FIG. 14D).

Next, a second interlayer insulating film 1501 is formed over the first interlayer insulating film 1407 and the source and drain electrodes 1408a to 1408f. Then, an opening is formed in the second interlayer insulating film 1501 at a position where part of the source and drain electrodes is exposed. Then, antennas 1502a to 1502e are formed over the second interlayer insulating film. Part of the antenna 1502e is in contact with the source and drain electrodes at the opening. After that, a protective layer 1503 is formed over the antennas 1502a to 1502e and the second interlayer insulating film 1501 (see FIG. 15A).

Next, as shown in FIG. 15B, a groove 1504 is formed in order to separate the ID chips. The depth of the groove 1504 may be as long as the peeling layer 1302 is exposed. The groove 1504 can be formed by dicing, scribing, or the like. Note that the groove 1504 is not necessarily formed when the ID chip formed over the substrate 1301 does not need to be separated.

Next, as shown in FIG. 16A, the peeling layer 1302 is removed by etching. In this way, the substrate 1301 is peeled off. In this embodiment mode, a halogenated fluorine gas is used as an etching gas, and this gas is introduced from the groove 1504. In the present embodiment, for example, nitrogen mixed with ClF ₃ or ClF ₃ gas may be used.

Next, as illustrated in FIG. 16B, the peeled TFTs 1602 to 1604 and the antennas 1502 a to 1502 e are attached to a support 1606 using an adhesive 1605. As the adhesive 1605, a material capable of bonding the support 1606 and the base film 1303 is used. As the adhesive 1605, for example, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used. As the support 1606, an organic material such as flexible paper or plastic can be used.

16B, after the protective layer 1503 is removed, an adhesive 1607 is applied over the second interlayer insulating film 1501 so as to cover the antennas 1502a to 1502e, and a cover material 1608 is attached. The cover material 1608 can be formed using a flexible organic material such as paper or plastic, like the support 1606. For the adhesive 1607, a material capable of bonding the cover material 1608 and the second interlayer insulating film 1501 is used. As the adhesive 1607, for example, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used.

The ID chip is completed through the steps described above. Note that this embodiment mode is not limited to this manufacturing method. An ID chip having a TFT having a structure having only a Lov region or a Loff region may be used, or an ID chip having only a TFT having a structure having both a Lov region and a Loff region may be manufactured. These can be manufactured by combining Embodiments 1 to 4 as appropriate.

Since the TFT used for the ID chip is required to be finely processed, it is preferably manufactured by a photolithography process using a stepper. However, when a stepper is used, the LDD region is formed with a resist mask, and the number of masks in all processes increases. That leads to an increase in manufacturing costs. Further, when a fine pattern is used, a margin for the patterning is small. For example, when a 0.5 μm Lov region is formed on one side of a 2 μm gate electrode with a mask, an alignment accuracy of 0.1 μm or less is required. When the gate electrode is isotropically etched, it is difficult to optimize the etching time. Specifically, it cannot be inspected how much etching has been performed laterally from the edge of the mask. That is, the end point cannot be detected, and it is difficult to evaluate the etching rate in the horizontal direction. A stable process cannot be established unless the lateral etching rate is stable.

Therefore, the present invention is particularly suitable for manufacturing a semiconductor device having TFTs that require microfabrication, such as an ID chip, a CPU, a flash memory, and an audio signal processing circuit integrated display device. In manufacturing these semiconductor devices, it has a desired TFT structure, and it becomes possible to reduce the manufacturing cost and improve the yield.

(Embodiment 6)
In this embodiment, a method for manufacturing a display device will be described with reference to FIGS. A method for manufacturing a display device described in this embodiment is a method for manufacturing a pixel portion and a TFT of a driver circuit portion provided around the pixel portion at the same time. In order to simplify the description, a CMOS circuit which is a basic unit with respect to the drive circuit is illustrated.

  First, as shown in FIG. 7A, a substrate 701 provided with a base film 702 on the surface is prepared. As the substrate, the substrate described in Embodiment 1 can be used. In this embodiment, a silicon nitride oxide film with a thickness of 100 nm and a silicon oxide film with a thickness of 200 nm are stacked and used as a base film over a substrate made of glass. At this time, the nitrogen concentration in contact with the substrate is preferably set to 10 to 25 wt%. Of course, the element may be formed directly on the substrate without providing the base film.

  Next, an amorphous silicon film having a thickness of 45 nm is formed on the base film 702 by a known film formation method. Note that the semiconductor film is not limited to an amorphous silicon film, and any semiconductor film including an amorphous structure (including a microcrystalline semiconductor film) may be used. Further, a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film may be used.

  Next, the amorphous silicon film is crystallized by a laser crystallization method. Of course, not only laser crystallization but also thermal crystallization using an RTA or furnace annealing furnace, or thermal crystallization using a metal element that promotes crystallization may be used.

  By the laser crystallization described above, a partially crystallized region is formed in the amorphous semiconductor film.

  Next, the crystalline semiconductor film with partially improved crystallinity is patterned into a desired shape, so that island-shaped semiconductor films 703 to 706 are formed. Note that channel doping may be performed on the semiconductor films 703 to 706 if necessary to control the threshold voltage of the TFT.

  Next, a gate insulating film 707 is formed to cover the island-shaped semiconductor films 703 to 706. The gate insulating film 707 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by plasma CVD or sputtering. In this embodiment mode, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) is formed with a thickness of 110 nm by a plasma CVD method. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by a plasma CVD method to a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz) power density of 0. It can be formed by discharging at 5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter.

  Subsequently, a first conductive film 708 and a second conductive film 709 to be gate electrodes are formed over the gate insulating film 707. First, the first conductive film 708 is formed with a thickness of 5 to 50 nm, and the second conductive film is formed with a thickness of 150 nm to 500 nm. The materials described in Embodiment 1 can be used for the first conductive film 708 and the second conductive film 709. In this embodiment, a tantalum nitride film (TaN) and a second conductive film are used as the first conductive film. A combination of a tungsten film (W) is used for the conductive film.

  As shown in FIG. 7B, tapered resists 710a to 710e are formed. The tapered resists 710a to 710e can be manufactured using a known method.

  Subsequently, first dry etching is performed (see FIG. 7C). In the first dry etching, the tapered resists 710a to 710e, the first conductive film 708, and the second conductive film 709 are etched to form the tapered first gate electrodes 711a to 711e and the second gate. Electrodes 712a to 712e are formed. Note that the resists 710a to 710e are also etched to form resists 713a to 713e.

  The dry etching in this embodiment can be performed using an ICP (Inductively Coupled Plasma) etching method.

Next, first doping is performed as shown in FIG. An n-type impurity element (phosphorus in this embodiment) is added to form impurity regions 801a to 801i containing phosphorus at a high concentration. The ion doping method using phosphine (PH ₃ ) is used, and the concentration of phosphorus in this region is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ (typically 2 × 10 ^{20 to} 5 × 10 ²⁰ atoms / cm 2). cm ³ ).

  Subsequently, second dry etching is performed. Using the resists 713a to 713e as a mask, the second gate electrodes 712b to 712e are etched in the vertical direction. Thus, second gate electrodes 802a to 802e are formed (see FIG. 8B).

Next, second doping is performed (see FIG. 8B). The second doping is performed in a self-aligning manner using the resists 713a to 713e and the second gate electrodes 802b to 802e as masks, and an n-type impurity element (phosphorus in this embodiment) having a concentration lower than that of the first doping is used. Added. The impurity regions 803a to 803e thus formed are doped with phosphorus at a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ (typically 3 × 10 ^{17 to} 3 × 10 ¹⁸ atoms / cm ³ ). It is preferable to do so.

  Next, the resists 713a to 713e are removed, and a resist 804 is formed as shown in FIG. Then, third dry etching is performed. Then, as shown in FIG. 8C, part of the first gate electrodes 711a, 711c, and 711d is etched to obtain the first gate electrodes 805a, 805c, and 805d.

Note that in the case where the resist 804 is formed without removing the resists 713a to 713e and third dry etching is performed, an etching gas in which Cl ₂ and CF ₄ are mixed at a flow rate of 30/30 sccm is used as the etching gas. The pressure in the chamber is 1.5 Pa by the exhaust system, and 500 W of RF (13.56 MHz) power is applied to the coil type electrode of the ICP etching apparatus, and 20 W of RF (13.56 MHz) power is applied to the substrate side. You may go.

Subsequently, a resist 901 is formed and third doping is performed (see FIG. 9A).
In the third doping, 801a, 801b, and 803a, which are n-type impurity regions, are doped with a p-type impurity element (boron in this embodiment) by ion doping using diborane (B ₂ H ₆ ). Impurity regions 902 and 903 containing boron at a high concentration are formed by adding at a concentration of × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ (typically 5 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ ). To do. Thus, the impurity regions 902 and 903 function as a source region and a drain region of the p-channel TFT.

  Next, as shown in FIG. 9B, the resist 901 is removed. After that, sidewalls 904a to 904e are formed on both sides of the second gate electrodes 802a to 802e. The sidewalls 904a to 904e are formed by forming a silicon compound and performing fourth dry etching as described in the first embodiment.

  Next, a resist mask 905 is formed, and then a fifth dry etching is performed. Then, as illustrated in FIG. 9C, part of the first gate electrode 711e is etched to obtain the first gate electrode 906e.

  Thereafter, the n-type or p-type impurity element added at each concentration is activated. The activation process is performed by laser annealing. When using the laser annealing method, it is possible to use the laser used for crystallization.

  Next, a passivation film 1001 is formed with a thickness of 50 to 500 nm (typically 200 to 300 nm). This may be replaced by a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or a laminate thereof.

  Next, an organic resin film 1002 having a thickness of 1.6 μm is formed on the passivation film 1001. As the organic resin, polyimide, acrylic, BCB (benzocyclobutene), or the like can be used. Since it is necessary to flatten the step due to the TFT, it is preferable to use an acrylic film having excellent flatness. Thereafter, a passivation film may be further formed on the organic resin film.

  Next, as shown in FIG. 10B, contact holes are formed in the passivation film 1001 and the organic resin film 1002, and source and drain wirings 1003a to 1003g are formed. In this embodiment mode, this electrode is a laminated film having a three-layer structure in which a Ti film is 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film 150 nm is continuously formed by sputtering. Of course, other conductive films may be used.

  Subsequently, a pixel electrode 1004 is formed so as to be in contact with the drain wiring 1003f. The pixel electrode 1004 is formed by patterning a transparent conductive film. The pixel electrode 1004 functions as an anode of the light emitting element. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used.

  After the pixel electrode is formed, a bank 1005 made of a resin material is formed. The bank 1005 is formed by patterning an acrylic film or a polyimide film having a thickness of 1 to 2 μm so as to expose a part of the pixel electrode 1004. Note that a black film serving as a shielding film (not shown) may be appropriately formed below the bank 1005.

  Next, the EL layer 1006 and the cathode (MgAg electrode) 1007 are continuously formed using a vacuum deposition method without being released to the atmosphere. Note that the EL layer 1006 may have a thickness of 80 to 200 nm (typically 100 to 120 nm), and the cathode 1007 may have a thickness of 180 to 300 nm (typically 200 to 250 nm).

  In this step, an EL layer and a cathode are sequentially formed for a pixel corresponding to red, a pixel corresponding to green, and a pixel corresponding to blue. However, since the EL layer has poor resistance to the solution, it has to be formed individually for each color without using a photolithography technique. Therefore, it is preferable to hide other than the desired pixels using a metal mask, and selectively form the EL layer and the cathode only at necessary portions.

  That is, first, a mask that hides all pixels other than those corresponding to red is set, and an EL layer and a cathode emitting red light are selectively formed using the mask. Next, a mask for hiding all but the pixels corresponding to green is set, and the EL layer and the cathode emitting green light are selectively formed using the mask. Next, similarly, a mask for hiding all but the pixels corresponding to blue is set, and an EL layer and a cathode emitting blue light are selectively formed using the mask. Note that although all the different masks are described here, the same mask may be used. Further, it is preferable to perform processing without breaking the vacuum until the EL layer and the cathode are formed on all the pixels.

  Note that a known material can be used for the EL layer 1006. As the known material, it is preferable to use an organic material in consideration of the driving voltage. For example, a four-layer structure including a hole injection layer, a hole transport layer, a light emitting layer, and an electron injection layer may be used as the EL layer. In this embodiment, an example in which an MgAg electrode is used as a cathode of an EL element is shown, but other known materials may be used.

  When the cathode 1007 is formed, the light emitting element 1008 is completed. After that, a protective film 1009 is provided so as to completely cover the light emitting element 1008. As the protective film 1009, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film can be used, and these insulating films can be used as a single layer or a stacked layer.

  Further, a sealing material 1010 is provided so as to cover the protective film 1009, and a cover material 1011 is attached thereto. As the sealing material 1010, it is preferable to use an ultraviolet curable resin containing a substance having a hygroscopic effect or a substance having an antioxidant effect. In this embodiment, a glass substrate, a quartz substrate, or a plastic substrate can be used as the cover material 1011.

  Thus, an active matrix EL display device having a structure having a p-channel TFT 1012, an n-channel TFT 1013, a switching TFT 1014 and a current control TFT 1015 as shown in FIG. 10C is completed.

  FIG. 11 shows a schematic diagram of a display device. A gate signal line driver circuit 1101, a source signal line driver circuit 1102, and a pixel portion 1104 including a plurality of pixels 1103 are formed over a substrate 1100. The gate signal line driver circuit 1101 and the source signal line driver circuit 1102 are connected to an FPC (flexible printed circuit) 1105. The p-channel TFT 1012 and the n-channel TFT 1013 in FIG. 10C can be used for a source signal line driver circuit and a gate signal line driver circuit.

  The source signal line driver circuit 1102 includes a shift register circuit, a level shifter circuit, and a sampling circuit. A clock signal (CLK) and a start pulse signal (SP) are input to the shift register circuit, and a sampling signal for sampling the video signal is output from the shift register circuit. The sampling signal output from the shift register is input to the level shifter circuit to increase the amplitude of the signal. The amplified sampling signal is input to the sampling circuit. The sampling circuit samples a video signal input from the outside with a sampling signal and inputs it to the pixel portion.

  Since these drive circuits are required to operate at high speed, it is preferable to use TFTs having a GOLD structure. In addition, the Lov region has a function to alleviate a high electric field generated near the drain, can prevent deterioration due to hot carriers, and is used for an n-channel TFT such as a shift register circuit, a level shifter circuit, or a buffer circuit of a drive circuit. It is because it is suitable for. On the other hand, it is preferable to use a TFT having a structure having a Loff region that can reduce off-state current as the pixel switching TFT and the holding TFT that holds the gate voltage of the current control TFT. The sampling circuit preferably has a structure having Lov and Loff regions since measures against hot carriers and measures against low off-state current are required.

  Needless to say, the present invention is not limited to a display device having such a structure, but can be applied to the manufacture of various display devices.

(Embodiment 7)
There are various methods for manufacturing the semiconductor device described in any of Embodiments 1 to 4 and a method for manufacturing a display device described in Embodiment 6 (hereinafter referred to as a method for manufacturing the display device described in Embodiment 6). It can be used when manufacturing a display portion or the like of an electronic device. Examples of such electronic devices include television devices, video cameras, digital cameras, goggles-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, audio components, etc.), personal computers, game machines, mobile phones An information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), an image playback device (specifically, Digital Versatile Disc (DVD)) provided with a recording medium, and the image is displayed. And a device equipped with a display that can be used. Specific examples of these electronic devices are shown in FIGS.

  FIG. 12A illustrates a television device which includes a housing 13001, a support base 13002, a display portion 13003, speaker portions 13004, a video input terminal 13005, and the like. The manufacturing method and the like of the display device described in Embodiment 6 can be used for manufacturing the display portion 13003 and the like, so that a television device can be completed. As the display portion 13003, an EL display, a liquid crystal display, or the like can be used. Note that the television device includes all television devices for computers, for receiving television broadcasts, for displaying advertisements, and the like.

  FIG. 12B illustrates a digital camera, which includes a main body 13101, a display portion 13102, an image receiving portion 13103, operation keys 13104, an external connection port 13105, a shutter 13106, and the like. The manufacturing method and the like of the display device described in Embodiment 6 can be used for manufacturing the display portion 13102 and the like, and a digital camera can be completed.

  FIG. 12C illustrates a computer, which includes a main body 13201, a housing 13202, a display portion 13203, a keyboard 13204, an external connection port 13205, a pointing mouse 13206, and the like. The manufacturing method and the like of the display device described in Embodiment 6 can be used for manufacturing the display portion 13203 and the like, and the computer can be completed.

  FIG. 12D illustrates a mobile computer, which includes a main body 13301, a display portion 13302, a switch 13303, operation keys 13304, an infrared port 13305, and the like. The manufacturing method and the like of the display device described in Embodiment 6 can be used for manufacturing the display portion 13302 and the like, and the mobile computer can be completed.

  FIG. 12E shows an image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 13401, a housing 13402, a display portion A 13403, a display portion B 13404, and a recording medium (DVD etc.) reading portion 13405. Operation key 13406, speaker unit 13407, and the like. Although the display portion A 13403 mainly displays image information and the display portion B 13404 mainly displays character information, the method for manufacturing the display device described in Embodiment 6 is used for manufacturing the display portion A 13403, the display portion B 13404, and the like. And an image reproducing apparatus can be completed. Note that the image reproducing device provided with the recording medium includes a game machine and the like.

  FIG. 12F illustrates a goggle type display (head mounted display), which includes a main body 13501, a display portion 13502, and an arm portion 13503. The manufacturing method and the like of the display device described in Embodiment 6 can be used for manufacturing the display portion 13502 and the like, and a goggle type display can be completed.

  FIG. 12G illustrates a video camera, which includes a main body 13601, a display portion 13602, a housing 13603, an external connection port 13604, a remote control receiving portion 13605, an image receiving portion 13606, a battery 13607, an audio input portion 13608, operation keys 13609, an eyepiece Part 13610 and the like. The manufacturing method and the like of the display device described in Embodiment 6 can be used for manufacturing the display portion 13602 and the video camera can be completed.

  FIG. 12H illustrates a mobile phone, which includes a main body 13701, a housing 13702, a display portion 13703, an audio input portion 13704, an audio output portion 13705, operation keys 13706, an external connection port 13707, an antenna 13708, and the like. The manufacturing method and the like of the display device described in Embodiment 6 can be used for manufacturing the display portion 13703 and the like, so that a cellular phone can be completed. Note that the display portion 13703 can suppress current consumption of the mobile phone by displaying white characters on a black background.

  In particular, a display device used for a display portion of these electronic devices has a thin film transistor for driving a pixel, and a desired TFT structure differs depending on a function of a circuit used. By applying the present invention, a TFT having a structure suitable for various circuits can be manufactured with high accuracy, and high-quality electronic devices can be produced with high yield.

  As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields.

  A manufacturing process when using a tapered resist pattern having a line width of 2.2 μm in the process of Embodiment 1 will be described with reference to FIGS. 6, 1, and 2. Common portions use the same reference numerals.

  The state shown in FIG. 6A corresponding to FIG. 1A was obtained through the same steps as in Embodiment Mode 1. At this time, the line width of the resist 107 was 2.2 μm and had a tapered shape.

  Next, the second conductive film 106 is etched together with a tapered resist having a line width of 2.2 μm by first dry etching to form a second gate electrode 108 to have a tapered shape (see FIG. 6B). ). At this time, the resist 107 was also etched to become a resist 109. The line width of the resist 109 after etching was 0.7 to 1.0 μm, and the line width under the second gate electrode 108 was 2.0 μm. That is, the line width of the taper portion on one side was 0.5 μm.

The dry etching in this example was performed by an ICP (Inductively Coupled Plasma) etching method. As an etching gas for the first dry etching, an etching gas obtained by mixing Cl ₂ , CF _4, and O ₂ at a flow rate of 25/25/10 sccm was used, and the pressure in the chamber was set to 1.5 Pa by an exhaust system. Also, 500 W of RF (13.56 MHz) power was applied to the coil-type electrode of the ICP etching apparatus, and 50 W of RF (13.56 MHz) power was applied to the substrate side.

  Subsequently, first doping was performed by a method similar to that in Embodiment 1 to form a source region and a drain region (see FIG. 1C).

  Subsequently, second dry etching was performed. Etching was performed in the vertical direction using the resist 107 as a mask to remove the tapered portion of the second gate electrode, so that the semiconductor layer 103 was exposed (see FIG. 1D). This exposed region to which no impurity was added had the same line width as that of the tapered portion region, and thus was 0.5 μm on one side. Here, the exposure of the semiconductor layer means that a portion serving as a mask is removed in doping performed in a later step, and does not necessarily mean that the semiconductor layer 103 is exposed. Therefore, it goes without saying that the gate insulating film 104 and the first conductive film 105 which do not serve as a doping mask are not removed by etching.

As an etching gas for the second dry etching, an etching gas in which Cl ₂ , SF ₆ and O ₂ are mixed at a flow rate of 12/24/24 sccm is used, and the pressure in the chamber is set to 2.0 Pa by an exhaust system. Also, 700 W of RF (13.56 MHz) power was applied to the coil-type electrode of the ICP etching apparatus.

  Subsequently, second doping was performed on the semiconductor layer 103. The semiconductor layer under the taper of the second gate electrode 108 removed by etching by the second dry etching is performed in the region where the first doping is not performed (FIG. 2A). reference). That is, the line width of 0.5 μm of the semiconductor layer, which is the region under the taper of the second gate electrode, becomes the LDD region 201. Then, a region of the semiconductor layer where the first doping and the second doping are not performed, that is, a line width of 1.0 μm which is the line width of the resist 109 formed by the first etching is a channel formation region.

  Subsequently, the resist 109 was removed, and 0.5 μm of silicon oxide was formed so as to cover the second gate electrode by the CVD method. Then, the silicon oxide was etched back by third dry etching to form sidewalls 202 on both sides of the second gate electrode. The line width of the sidewall was 0.3 μm (see FIG. 6C).

As the etching gas for the third dry etching, an etching gas in which CHF ₃ and Ar are mixed at a flow rate of 25/250 sccm is used, and the pressure in the chamber is set to 8.0 Pa by the exhaust system. Also, 200 W RF (13.56 MHz) power was applied to the coil-type electrode of the ICP etching apparatus, and 350 W RF (13.56 MHz) power was applied to the substrate side.

  Subsequently, fourth dry etching was performed using the second gate electrode 112 and the sidewalls 202 as a mask (see FIG. 2C). By this etching, the first gate electrode was etched to form an LDD region that did not overlap the first gate. The LDD region that does not overlap with the gate electrode is called a Loff region, and the line width of this region is 0.2 μm. The Loff region is formed for the purpose of reducing off current. The region that overlaps the LDD region and the first gate electrode that remains without being etched with the side wall as a mask is called a Lov region, and this line width is approximately 0.3 μm because it substantially matches the line width of the side wall ( (See FIGS. 6C and 2C). This Lov region is formed in order to prevent hot carrier deterioration.

As an etching gas for the fourth dry etching, Cl ₂ was used at a flow rate of 60 sccm, and the pressure in the chamber was 1.0 Pa by the exhaust system. Further, 350 W of RF (13.56 MHz) power was applied to the coil-type electrode of the ICP etching apparatus, and 20 W of RF (13.56 MHz) power was applied to the substrate side.

  According to the method for manufacturing a semiconductor device of the present invention, since the Lov region and the Loff region are formed in a self-aligning manner by changing the shape of the gate electrode, the process is simpler than the step of forming the LDD region using a resist mask. Thus, a semiconductor device having excellent TFT characteristics can be manufactured.

  Further, for example, when an LDD region is formed and a resist or a gate electrode serving as a doping mask is etched in the lateral direction, it is difficult to evaluate the lateral etching rate. Therefore, a stable process cannot be established. However, as in this embodiment, a tapered resist is used to taper the gate electrode, and the taper portion of the gate electrode is further etched vertically using this resist without using a new resist. Can be formed with good controllability. In particular, it is suitable for manufacturing a semiconductor device having a fine TFT (a fine TFT formed using a stepper in a photolithography process).

8A and 8B illustrate a method for manufacturing the semiconductor device of Embodiment 1 and Example 1. FIGS. 8A and 8B illustrate a method for manufacturing the semiconductor device of Embodiment 1 and Example 1. FIGS. 10A to 10D illustrate a method for manufacturing the semiconductor device of Embodiment 2. FIGS. 8A to 8D illustrate a method for manufacturing the semiconductor device of Embodiment 3. 8A to 8D illustrate a method for manufacturing the semiconductor device of Embodiment 4. 8A and 8B illustrate a method for manufacturing the semiconductor device of Example 1. FIG. 8A and 8B illustrate a method for manufacturing a display device in Embodiment 6. 8A and 8B illustrate a method for manufacturing a display device in Embodiment 6. 8A and 8B illustrate a method for manufacturing a display device in Embodiment 6. 8A and 8B illustrate a method for manufacturing a display device in Embodiment 6. FIG. 7 is a schematic view of a display device that can be manufactured by the display device manufacturing method described in Embodiment 6. FIG. 9 illustrates an electronic device shown in Embodiment 7; 6A and 6B illustrate a method for manufacturing the ID chip shown in Embodiment Mode 5 6A and 6B illustrate a method for manufacturing the ID chip shown in Embodiment Mode 5 6A and 6B illustrate a method for manufacturing the ID chip shown in Embodiment Mode 5 6A and 6B illustrate a method for manufacturing the ID chip shown in Embodiment Mode 5

Claims (7)

A gate insulating film is formed so as to cover the island-shaped semiconductor layer,
The first conductive film is formed on the gate insulating film,
A second conductive film is formed on the first conductive film,
A resist is formed with a tape supermarkets shape on the second conductive film,
The resist and by etching the second conductive film, forming a second gate electrode that having a tapered shape consisting of the second conductive film,
Doping the semiconductor layer with an impurity element of one conductivity type at a first concentration using the second gate electrode having the tapered shape as a mask ;
Etching the second gate electrode vertically using the resist as a mask ,
Doping the semiconductor layer with a second concentration lower than the first concentration in the semiconductor layer using the vertically etched second gate electrode as a mask ;
Removing the resist;
Forming a silicon compound so as to cover the second gate electrode;
By etching the silicon compound, sidewalls are formed at both ends of the vertically etched second gate electrode,
By etching the first conductive layer using the vertical second gate electrode and the sidewall etched as a mask, and characterized by forming a first gate electrode made of the first conductive film A method for manufacturing a semiconductor device. A gate insulating film is formed so as to cover the island-shaped semiconductor layer,
The first conductive film is formed on the gate insulating film,
A second conductive film is formed on the first conductive film,
A resist is formed with a tape supermarkets shape on the second conductive film,
The resist and by etching the second conductive film, forming a second gate electrode that having a tapered shape consisting of the second conductive film,
Doping the semiconductor layer with an impurity element of one conductivity type at a first concentration using the second gate electrode having the tapered shape as a mask ;
Etching the second gate electrode vertically using the resist as a mask,
Removing the resist ;
Doping the semiconductor layer with a second concentration lower than the first concentration in the semiconductor layer using the vertically etched second gate electrode as a mask ;
Forming a silicon compound so as to cover the second gate electrode;
By etching the silicon compound, sidewalls are formed at both ends of the vertically etched second gate electrode,
By etching the first conductive layer using the vertical second gate electrode and the sidewall etched as a mask, and characterized by forming a first gate electrode made of the first conductive film A method for manufacturing a semiconductor device. A gate insulating film is formed so as to cover the island-shaped semiconductor layer,
The first conductive film is formed on the gate insulating film,
A second conductive film is formed on the first conductive film,
A resist is formed with a tape supermarkets shape on the second conductive film,
From the resist, the by the etching the first conductive film and the second conductive film, the first conductive first gate electrodes that have a tapered shape composed of film及beauty the second conductive film Forming a second gate electrode having a tapered shape ,
Using the first gate electrode having the tapered shape and the second gate electrode having the tapered shape as a mask , doping the semiconductor layer with an impurity element of one conductivity type at a first concentration ;
Etching the second gate electrode vertically using the resist as a mask ,
Wherein said semiconductor layer to said lower than the first concentration second concentration impurity element imparting one conductivity type to Doping the second gate electrode etched vertically as a mask,
Removing the resist;
Forming a silicon compound so as to cover the second gate electrode;
By etching the silicon compound, sidewalls are formed at both ends of the vertically etched second gate electrode,
The method for manufacturing a semiconductor device characterized by etching the first gate electrode having the tapered shape of the second gate electrode and the sidewall of the is vertically etched as a mask. A gate insulating film is formed so as to cover the island-shaped semiconductor layer,
The first conductive film is formed on the gate insulating film,
A second conductive film is formed on the first conductive film,
A resist is formed with a tape supermarkets shape on the second conductive film,
From the resist, the by the etching the first conductive film and the second conductive film, the first conductive first gate electrodes that have a tapered shape composed of film及beauty the second conductive film Forming a second gate electrode having a tapered shape ,
Using the first gate electrode having the tapered shape and the second gate electrode having the tapered shape as a mask , doping the semiconductor layer with an impurity element of one conductivity type at a first concentration ;
Etching the second gate electrode vertically using the resist as a mask,
Removing the resist ;
Doping the semiconductor layer with a second concentration lower than the first concentration in the semiconductor layer using the vertically etched second gate electrode as a mask;
Forming a silicon compound to cover the vertically etched second gate electrode;
By etching the silicon compound, sidewalls are formed at both ends of the vertically etched second gate electrode,
Etching the first gate electrode having the tapered shape using the vertically etched second gate electrode and the sidewall as a mask,
The method for manufacturing a semiconductor device, which comprises removing the resist. Any Oite to one of claims 1 to 4, that the width of the channel length direction of the side wall, shorter than the channel length direction of the width of the tapered portion of the second gate electrode etched vertically A method for manufacturing a semiconductor device. Any one to Oite of claims 1 to 5, silicon oxide as the silicon compound, a method for manufacturing a semiconductor device, which comprises using any one of a silicon silicon nitride or oxynitride. An island-shaped semiconductor having a source region, a drain region, a channel formation region, and low-concentration impurity regions provided between the source region and the channel formation region and between the drain region and the channel formation region, respectively Layers ,
A gate insulating film provided to cover the island-shaped semiconductor layer ;
A first gate electrode provided on the gate insulating film,
A second gate electrode provided on the first gate electrode and having a length in a channel length direction shorter than the first gate electrode ;
Sidewalls made of silicon compounds respectively provided at both ends in the channel length direction of the second gate electrode ,
The first gate electrode overlaps a portion of the low concentration impurity region through said gate insulating film,
In the channel length direction, the length of the first gate electrode overlapping the low concentration impurity region is equal to the length of the sidewall ,
The semiconductor device is characterized in that an end portion of the low-concentration impurity region and an end portion of the first gate electrode do not coincide with each other in the channel length direction .

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