JPH0653422A - Semiconductor integrated circuit device and fabrication thereof - Google Patents

Abstract

PURPOSE:To fabricate a semiconductor integrated circuit device having CMOS or BiCMOS structure with high integration. CONSTITUTION:In a semiconductor integrated circuit device having CMOS or BiCMOS structure, implantation of impurities for forming CMOS region, i.e., N-well and P-well, is performed through self-aligned manner for an isolation region, i.e., a field isolation film 23 and an isolation groove 24, after formation thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is a complementary MOSFET.
A semiconductor integrated circuit device having (hereinafter, referred to as CMOS), or a bipolar-CMOS in which a bipolar transistor and a CMOS are integrated on the same semiconductor substrate.
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having (hereinafter, referred to as Bi-CMOS).

[0002]

BACKGROUND OF THE INVENTION JP-A-2-184068, a silicon substrate provided on the insulating layer (S ilicon O n I nsulao
tor substrate: hereinafter referred to as an SOI substrate), an N-type well and a P-type well are formed, and then a groove for isolation is formed between the N-type well and the P-type well.
The N separated by the isolation groove.
P-channel MOSFET and N-channel MOSFE forming CMOS on the main surface of each of the P-type well and the P-type well
A process for forming T is disclosed.

Also, in 1989, published by Karwa Academic Publishing Co., edited by Antonio All Albert, "Bi-CMOS Technology and Applications," pages 100 to 10
Page 7 (1989, Kluwer Academic P
ublishers, edited by Anton
io R Alvarez, “Bi-CMOS Te
chnology and Application
s ", pp100-107), an N-type buried layer and a P-type buried layer are formed on the surface of the P-type silicon substrate, and an N-type epitaxial layer is further formed on the P-type silicon substrate. After that, a Bi-CMOS process is disclosed in which an N-type well and a P-type well are respectively formed in the N-type epitaxial layer located on the N-type buried layer and the P-type buried layer. Further, in the above document, a thick field oxide film is provided at the boundary between the N-type well and the P-type well, and the isolation
It is stated that it will be used as an application area.

[0004]

DISCLOSURE OF THE INVENTION The present inventor has found that CMOS
Further, as a result of examining further high integration and high reliability of the semiconductor integrated circuit device having Bi-CMOS, the following problems were clarified.

All of the above-described conventional manufacturing processes are N-channel MOSFET and P-channel MOSFET.
After forming the P-type and N-type wells as the T formation region, a field oxide film or an isolation groove as an isolation region is formed at the boundary between the P-type and N-type wells. Therefore, when forming the field oxide film or the isolation trench, the isolation mask including the field oxide film or the isolation trench is taken into consideration in consideration of the mask alignment margin with the P-type well and the N-type well. It is necessary to widen the application area. Furthermore, since the P-type and N-type impurities for forming the P-type and N-type wells are mutually diffused by heat treatment during the formation of the P-type and N-type wells,
Since an ambiguous region of unknown conductivity type (a region where the impurity profile is unclear) is formed at the boundary between the p-type well and the p-type well, an isolation region including the field oxide film or the isolation trench is further formed. It needs to be formed widely.
Therefore, it is difficult to effectively reduce the element isolation width between the active region of the N-channel MOSFET and the active region of the P-channel MOSFET in the CMOS section.

In the field of Bi-CMOS, in particular, C
From the viewpoint of improving the reliability of the MOS, as a measure against latch-up, in order to reduce the well parasitic resistance, a P-type buried layer and an N-type buried layer having a high impurity concentration are formed below the P-type well and the N-type well, respectively. It is formed prior to the formation of the epitaxial layer and the P-type and N-type wells. Therefore, when forming the P-type and N-type wells, it is necessary to consider the mask alignment margin with each of the P-type and N-type buried layers, and as in the case of forming the wells described above. In addition, since an ambiguous region of unknown conductivity type (region in which the impurity profile is unclear) is formed at the boundary between the P-type and N-type buried layers, the element isolation region becomes wider and high integration is hindered. The problem arises.

Further, as described in the above-mentioned prior art documents, in the formation of wells or buried layers having different conductivity types, the following self-alignment technique is used for the purpose of high integration. It was First, a nitride (SiN) film is selectively formed on the surface of the silicon substrate, and N-type impurities are introduced into the main surface of the silicon substrate using this as a mask for introducing impurities. Thereafter, the fact that the oxidation rate of the region in which the N-type impurity is introduced is faster than that in the region in which the nitride (SiN) film is formed is utilized, and thick silicon is formed only on the region in which the N-type impurity is introduced. The oxide film is formed by the thermal oxidation method. After this, the nitride (Si
When the N) film is removed, a thick silicon oxide film is formed only on the region into which the N-type impurity is introduced. Therefore, using this as an impurity introduction mask, the P-type impurity is selectively applied to the main surface of the silicon substrate. Can be introduced to. After that, the thick silicon oxide film used as the mask is
For example, it is removed with a hydrofluoric acid-based etching solution. In this way, the P-type impurity is introduced in a self-aligned manner with respect to the region in which the N-type impurity is introduced. Impurities can be selectively introduced, and high integration is possible.

However, since the silicon oxide film is thickly formed only on the N-type layer in this series of processes, the silicon oxide film is formed on the silicon substrate (or the epitaxial layer) at the boundary between the N-type layer and the P-type layer. A step is produced in proportion to the thickness of the silicon oxide film. Since this step is formed in the isolation region or the active region in the vicinity thereof, for example, in the process of forming a groove for isolation,
This may affect the processing of the groove and cause problems such as defective shapes. Further, even at the time of exposure for forming a photoresist pattern for processing the gate electrode of the CMOS, it is possible to accurately process a fine pattern due to the difference in photoresist film thickness caused by the step. In addition, there is a problem that the electrical reliability of the semiconductor integrated circuit device is lowered.

The present invention has been made to solve the above-mentioned problems, and one object of the present invention is to provide a CMO.
It is an object of the present invention to provide a technique capable of achieving high integration and high reliability of a semiconductor integrated circuit device having an S or Bi-CMOS structure.

[0010]

The outline of a typical one of the present invention will be briefly described as follows.

That is, in a method of manufacturing a semiconductor integrated circuit device having a CMOS, before introducing an impurity for forming each of an N-type well and a P-type well into a semiconductor substrate, first, an isolation trench and an element isolation region are formed. A field insulating film is formed. After that, N constituting the CMOS is
P-type and N-type impurities for forming P-type and N-type wells, which are regions for forming channel MOSFETs and P-channel MOSFETs, are selectively introduced into the main surface of the semiconductor substrate defined by the isolation trenches. To do. here,
The P-type and N-type impurities for forming each well are
It is selectively introduced by using a resist mask formed by a normal photolithography technique. However, by keeping the alignment margin of the resist mask within the width of the groove, it is self-aligned with the element isolation region. Introduce.

Further, in the method of manufacturing a semiconductor integrated circuit device having Bi-CMOS, impurities for selectively forming an N-type buried layer are introduced into only a bipolar transistor forming region of a semiconductor substrate to form a CMOS. N in the area
No impurities are introduced to form the P-type and P-type buried layers. Alternatively, an N-type impurity for forming the N-type buried layer is introduced into the entire surface of the semiconductor substrate in the bipolar transistor forming region and the CMOS forming region. Then, an epitaxial layer is formed on the main surface of the semiconductor substrate, and then an N-channel MOSFET and a P-channel MOSF forming a bipolar transistor and a CMOS.
The epitaxial layer in each ET forming region is partitioned by a groove.

[0013]

According to the above-mentioned means, the N-channel MOSFET and the P-channel MOSFE forming the CMOS are formed after forming the isolation trench and the field insulating film to be the element isolation region.
Since P-type and N-type impurities for forming P-type and N-type wells for forming T are introduced in self-alignment with the element isolation region, the alignment margin between the element isolation region and each well region is increased. It is not necessary to take into account the above, and the P-type and N-type impurities in each well are mutually diffused by the heat treatment for forming the well due to the preceding formation of the isolation trench, thereby forming an ambiguous region of unknown conductivity type. It will not be done.
Therefore, high integration of a semiconductor integrated circuit device having CMOS becomes possible.

Further, since the problem of latch-up due to the element isolation by the groove is almost solved, a buried layer having a high impurity concentration different in conductivity type from the conventional one is formed in the CMOS portion in terms of element characteristics. Since it is not necessary, it is not necessary to introduce the selective impurities by the conventional nitride film. Therefore, the N-channel MOSFET and the P-channel MOSFE forming the CMOS are
Since there is no step at the boundary of the T formation region, Bi-C
It is possible to improve the electrical reliability of the semiconductor integrated circuit device having the MOS.

[0015]

Embodiments of the present invention will be specifically described below with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted. FIG. 1 shows a chip layout of a semiconductor integrated circuit device having a Bi-CMOS structure of the present invention. The semiconductor integrated circuit device having the Bi-CMOS structure of the present invention is provided on the main surface of an SOI substrate 8 in which two single crystal silicon substrates are bonded together via an insulating layer. In the figure, an NPN bipolar transistor, an N channel MOSFET and a P channel MOSFE on the SOI substrate 8 are shown.
A specific arrangement example of T is shown. NPN Bypo
Transistor forming regions 2 and 3 and N-channel MOSF
The ET forming regions 4, 5 and 6 are surrounded by the groove pattern 1. P-channel MOSFET formation region 7
Is outside the groove pattern 1, and the NPN bipolar
Transistor forming regions 2 and 3 and N-channel MOSF
It extends between the ET forming regions 4, 5, 6.

Next, a specific device structure of the semiconductor integrated circuit device having the Bi-CMOS structure of the present invention will be described with reference to FIG.
3 and FIG. Figure 2 shows the NPN bipolar.
Transistor Q1, P-channel MOSFET MP1,
Specific device plane layouts for MP2 and N-channel MOSFETs MN1, MN2 respectively are shown.
Further, FIG. 3 shows a device cross-sectional view taken along one-dot chain line A1-A2 in FIG.

As shown in FIGS. 2 and 3, the Bi of the present invention is
-The semiconductor integrated circuit device 100 of the CMOS configuration is SOI
It is provided on the substrate 8. This SOI substrate comprises a P-type single crystal silicon support substrate 8A, a silicon oxide film 8B, and an N-type single crystal silicon film 8C. As shown in the figure,
In the region NPN, the NPN bipolar transistor Q1,
P-channel MOSFETs MP1 and MP are provided in the region PMOS.
2. N-channel MOSFET MN1, for region NMOS
Each MN2 is configured. The bipolar transistor Q1 mainly includes an emitter region 9 made of an N + type semiconductor region and an intrinsic base region 10 made of a P type semiconductor region.
And a vertical NPN bipolar transistor composed of the N-type single crystal epitaxial layer 11. Further, the bipolar transistor Q1 has the intrinsic base region 10
An external base region 12 formed of a P + type semiconductor region electrically connected to the external base region 12, and the external base region 12 has a P
A base extraction layer 13 made of a + type polycrystalline silicon layer is connected. The base extraction layer 13 is provided so as to surround the emitter region 9, and is made of an n + type polycrystalline silicon layer through an opening defined by a sidewall spacer 14 made of an insulating film provided on the side portion thereof. The emitter extraction layer 15 is connected to the emitter region 9. As described above, the bipolar transistor Q1 has a double polysilicon self-aligned transistor structure and is excellent in high speed operation. The bipolar transistor Q1 includes an n + type buried layer 16 formed of an n + type semiconductor region for reducing collector series resistance,
Collector extraction region 17 formed of an n + type semiconductor region for extracting a collector potential from the surface. A collector electrode 22 is connected to the collector extraction region 17 via a connection hole CONT3. A base electrode 20 is connected to the base extraction layer 13 via a connection hole CONT1 formed in the interlayer insulating films 18 and 19. An emitter electrode 21 is connected to the emitter extraction layer 15 via a connection hole CONT2 provided in the interlayer insulating film 19. The emitter electrode 2
1, the base electrode 20, and the collector electrode 22 are provided in the first-layer wiring forming process, and are formed of, for example, a tungsten (W) layer. Incidentally, each semiconductor region (impurity-doped layer) forming the bipolar transistor Q1
Is formed by selectively introducing n-type and p-type impurities into the n-type single crystal silicon epitaxial layer Epi grown on the main surface of the SOI substrate 8.

Further, the bipolar transistor Q1 is surrounded by an isolation region formed by the field insulating film 23 and the isolation trench 24, and is electrically isolated from other active elements (eg MOSFET MP1, MN1). Has been done. The separation groove 24 is
The field insulating film 23, the epitaxial layer Epi, and the n-type single-crystal silicon film 8A are extended to reach the insulating film 8B of the SOI substrate. An insulating material such as a silicon oxide film is embedded in the isolation trench 24 to form a dielectric isolation structure. The field insulating film 23 in the region NPN
The plane pattern of NPN-LOCOS in FIG.
Indicated by.

P-channel MOSFETs MP1 and MP2
Are provided on the main surface portions of the n-type semiconductor regions (n-type wells) 25A and 25B formed in the n − -type epitaxial layer Epi. P-channel MOSFET MP1, MP2
Of the high-concentration source / drain regions 27A, 27B, and 2 composed of p + type semiconductor regions and gate electrodes 26A and 26B mainly composed of polycrystalline silicon layers containing n-type impurities.
8A and 28B and gate insulating films 29A and 29B. P-channel MOSFET MP1, MP2
Each further lower impurity concentration than the high concentration source and drain regions, lightly doped source and drain regions 30A comprising a p- type semiconductor region includes a 30B, so-called LDD (L ightly- D oped- D rain ) It has a structure.
Further, in order to reduce the resistance value of the n-type semiconductor regions 25A and 25B, an n + -type semiconductor region having a higher impurity concentration than the n-type semiconductor regions 25A and 25B is provided below the n-type semiconductor regions 25A and 25B. 31A and 31B are provided. The n + type semiconductor regions 31A and 31B
Each of is formed by high-energy ion implantation,
An n-type well is formed integrally with the n-type semiconductor regions 25A and 25B. Also, the n + type semiconductor regions 31A, 3
Since 1B is formed by high-energy ion implantation, the n + type semiconductor region 3 is formed under the field insulating film 23 at the same time.
7 is formed. P-channel MOSFET MP1, M
The surface regions of the respective P2s are surrounded by the field insulating film 23 and are separated from each other. Area PM
The plane pattern of the field insulating film 23 of the OS is shown by PMOS-LOCOS in FIG. An insulating film 32 is coated on the upper portions of the gate electrodes 26A and 26B, and side portions of the gate electrodes 26A and 26B are
Sidewall spacers 33 made of an insulating film are provided. The sidewall spacers 33 are provided to secure the distance between the sidewalls of the gate electrode and the high concentration source / drain regions. Further, the insulating film 3 is formed on the source / drain regions 27A and 28A.
Connection holes CONT4, CON provided in 4, 18, 19
Source / drain electrodes 35A and 36A are connected via T5, and similarly, the source / drain regions 27B and
Source / drain electrodes 35B and 36B are connected to 28B through connection holes CONT6 and CONT7 provided in the insulating films 34, 18, and 19. These source / drain electrodes 35A, 35B, 36A and 36B are formed in the same step as the emitter, base and collector electrodes of the bipolar transistor Q1. In addition, the P
Gate electrodes 26 of the channel MOSFETs MP1 and MP2
Each of A and 26B has a gate wiring (not shown)
It is connected via NT12 and CONT13. The gate wiring is also formed in the same process as the source / drain electrodes. Also, the P channel MOSF
A power supply potential (for example, 0 V) on the high level side of the circuit is supplied to the n-type semiconductor regions 25A and 25B of ETMP1 and MP2 and the n + -type semiconductor regions 31A and 31B. The power supply potential on the high level side is supplied through the CONT 16 by a power supply wiring (not shown). The power supply wiring is also formed in the same process as the source / drain electrodes. In addition, the region PMOS has a field insulating film 23, similar to the NPN bipolar transistor.
An isolation region composed of the isolation trench 24 in which a silicon oxide film is buried is electrically isolated from other active elements (for example, MOSFET MN1 and NPN bipolar transistor Q1).

N-channel MOSFETs MN1 and MN2
Are provided on the main surface portions of the p-type semiconductor regions (p-type wells) 39A and 39B formed in the n-type epitaxial layer Epi. N-channel MOSFETs MN1 and MN2
The gate electrodes 26C and 26D are mainly composed of a polycrystalline silicon layer containing n-type impurities, and the high-concentration source / drain regions 40A, 40B and 41 are composed of n + -type semiconductor regions.
A, 41B and gate insulating films 29C, 29D. Each of the N-channel MOSFETs MN1 and MN2 further includes low-concentration source / drain regions 42A and 42B made of an n-type semiconductor region having an impurity concentration lower than that of the high-concentration source / drain regions. It has a structure. Further, under the p-type semiconductor regions 39A and 39B,
In order to reduce the resistance value of the p-type semiconductor regions 39A and 39B, p + -type semiconductor regions 43A and 43B having an impurity concentration higher than that of the p-type semiconductor regions 39A and 39B are provided. Each of the p + type semiconductor regions 43A and 43B is formed by high-energy ion implantation, and forms a p type well together with the p type semiconductor regions 39A and 39B. In addition, p-type semiconductor regions 43A and 43B
Is formed by high-energy ion implantation,
A p + type semiconductor region 44 is simultaneously formed under the field insulating film 23. N-channel MOSFETs MN1 and MN2
Are surrounded by the field insulating film 23 and are separated from each other. The plane pattern of the field insulating film 23 in the region NMOS is NM in FIG.
It is indicated by OS-LOCOS. The gate electrode 26
The upper surfaces of C and 26D are covered with the insulating film 32, and the side walls of the gate electrodes 26C and 26D are provided with sidewall spacers 46 made of an insulating film. The sidewall spacers 46 are provided to secure the distance between the sidewalls of the gate electrode and the high concentration source / drain regions. Further, source / drain electrodes 47A, 48A are connected to the source / drain regions 40A, 41A via connection holes CONT8, CONT9 provided in the insulating films 34, 18, 19 and similarly, In the source / drain regions 40B and 41B, the connection hole CONT1 provided in the insulating films 34, 18, and 19 is formed.
0, CONT11, source / drain electrode 47
B and 48B are connected. These source / drain electrodes are the emitter of the bipolar transistor Q1,
It is formed in the same process as the base and collector electrodes. In addition, the gate electrodes 26C and 26D of the N-channel MOSFETs MN1 and MN2 have gate wirings (not shown),
They are connected via CONT 14 and CONT 15, respectively. The gate wiring is also formed in the same process as the source / drain electrodes. The p-type semiconductor regions 39A and 39B, which are the formation regions of the N-channel MOSFETs MN1 and MN2, and the p + -type semiconductor region 43.
A and 43B are supplied with a power supply potential on the low level side of the circuit (for example, minus 3 V). The power supply potential on the low level side is CONT by a power supply wiring not shown.
It is supplied via 17. The power supply wiring is also formed in the same process as the source / drain electrodes. Further, the region NMOS has an isolation region composed of the field insulating film 23 and the isolation trench 24 in which the silicon oxide film is buried, as in the NPN bipolar transistor, and is used as another active element (for example, MOSFETMP1,
It is electrically separated from the NPN bipolar transistor Q1 and the like).

Next, the Bi-CMO shown in FIGS.
A specific method of manufacturing the semiconductor integrated circuit device having the S configuration will be described with reference to FIGS.

First, as shown in FIG. 4, an SOI substrate 8 is prepared. The SOI substrate 8 includes a P-type single crystal silicon support substrate 8A, a silicon oxide film 8B, and an N-type single crystal silicon layer 8C. The P-type semiconductor support substrate 8A is, for example, 8
It has a resistance value of about 12 [Ωcm] and its film thickness is about 550 μm, for example. The film thickness of the silicon oxide film 8B is, for example, about 500 nm. The N-type single crystal silicon film 8C has a resistance value of, for example, about 8 to 12 [Ωcm], and its film thickness is, for example, about 1.5 μm. The SOI substrate 8 can be formed by bonding two silicon wafers through the silicon oxide film 8B by heat treatment and then polishing one side of the silicon wafers to a predetermined thickness.

Next, as shown in FIG. 5, silicon nitride (Si
N) An oxidation resistant mask 50 such as a film is selectively formed on the SOI substrate 8 in a region other than the bipolar transistor Q1. Pattern of oxidation resistant mask 50 - the training, photolithography - using an etching mask (photoresist) NBL formed by techniques, a thin silicon oxide film 49 etched stopper - as film, RIE (R eactive I on
E tching) is carried out by anisotropic etching such as. Here, the film thickness of the silicon oxide film 49 is, for example, 20 nm, oxidation resistance mask 50, CVD silicon nitride film (C hemical V a
deposited at por D eposition) method, a film thickness of about 50 [nm], the film thickness of the photoresist mask NBL 1.0
It is about μm. The plane pattern of the oxidation resistant mask is shown by NBL in FIG. Next, the n-type impurity 51
Are selectively introduced into the main surface portion of the N-type single crystal silicon film 8C in the bipolar transistor Q1 region. The n-type impurity 5
1 uses, for example, antimony (Sb) with an impurity concentration of about 10 ¹⁵ [atoms / cm ² ]. Then, the photoresist NBL is removed. Next, the n-type impurity 5
1 is subjected to a thermal diffusion treatment at about 1200 ° C. and stretched and diffused in the N-type single crystal silicon film 8C,
As shown in FIG. 6, an n + type buried layer 16 made of an n + type semiconductor region is formed.

Subsequently, as shown in FIG. 6, the silicon oxide film 52 is selectively formed by thermally oxidizing the main surface of the N-type single crystal silicon film 8C exposed from the oxidation resistant mask. The oxide film 52 is formed by a steam oxidation method at a high temperature of about 1000 ° C., and has a thickness of 150 nm.
It is formed with a film thickness of about. The oxide film 52 is formed for the purpose of forming a step used for alignment positioning in a later photography technique. After that, the oxidation resistant mask 50 and the oxide films 49 and 52 are removed.

Next, as shown in FIG. 7, an n--type epitaxial layer Epi is grown on the main surface of the SOI substrate 8.
The n− type epitaxial layer Epi is formed of single crystal silicon, has a resistance value of, for example, about 3 [Ωcm], and is formed to have a film thickness of, for example, about 0.7 μm. This n
By the growth of the − type epitaxial layer Epi, the n type impurities forming the n + type buried layer 16 are diffused up to the lower part of the n − type epitaxial layer Epi. Next, the oxidation-resistant mask 53 such as a silicon nitride film (SiN) is used for the bipolar transistor Q1 and the P-channel MOSFET region PMOS.
And on the n-type epitaxial layer Epi of the N-channel MOSFET region NMOS. For the patterning of the oxidation resistant mask 53, an etching mask 54 formed by a photolithography technique is used, and anisotropic etching such as RIE is performed using the silicon oxide film 55 as an etching stopper film. Here, the thickness of the oxide film 55 is, for example, 10 to 20 nm, and the oxidation resistant mask 53
Is a silicon nitride film having a film thickness of about 100 to 200 [nm] deposited by the CVD method, and is a photoresist mask 54.
Has a film thickness of about 1.0 μm. The planar pattern of the oxidation-resistant mask 53 is the same as NPN-LOCOS, P shown in FIG.
The patterns are the same as those of MOS-LOCOS and NMOS-LOCOS, respectively. After patterning the oxidation resistant mask 53, the photoresist 54 is removed.

Thereafter, as shown in FIG. 8, the field insulating film 23 made of a silicon oxide film is selectively formed by thermally oxidizing the main surface of the n--type epitaxial layer Epi exposed from the oxidation resistant mask. To do. The field insulating film is formed by a steam oxidation method at a high temperature of about 1000 ° C. and has a film thickness of about 400 nm.

Next, as shown in FIG. 9, a multi-layered structure mask for forming the separation groove is formed. In this multilayer structure mask, a polycrystalline silicon film 56 and a silicon oxide film 57 are sequentially formed on the SOI substrate 8, and then a photoresist mask 58 is used to perform anisotropic etching such as RIE to form the silicon oxide film 57. And the polycrystalline silicon film 56 may be sequentially etched. Here, the polycrystalline silicon film 56 and the silicon oxide film 57 are
It is deposited by using the CVD method, and the film thickness is 200, for example.
[Nm] and about 300 [nm]. The film thickness of the photoresist mask 57 is about 1.0 [μm]. The planar opening pattern of the multilayer structure mask is
This is indicated by the diagonal lines TR1 and TR2 in FIG. The opening width of the mask for forming the separation groove is, for example, 0.4 [μ
m]. After that, the resist mask 58 is removed.

Next, as shown in FIG. 10, using the silicon oxide film 57 as an etching mask, the epitaxial layer Epi, the n + buried layer 16 and the N-type single crystal silicon film 8C are sequentially etched by anisotropic etching such as RIE. Etching
An isolation trench 24 reaching the silicon oxide film 8B is formed.
Here, the silicon oxide film 56 also functions as a protective film for the element region. The plane layout of the isolation trench 24 is as shown in FIG.
Only the formation region of the channel MOSFET is surrounded. The reason is that if the entire element region is separated by a groove, a region where the potential is not fixed, which is surrounded by the groove, may be formed depending on the layout of each element, which may lead to increase in noise and parasitic capacitance. is there.
Also, it is difficult to route the power supply wiring for well power supply. In this embodiment, the region surrounded by the groove is a bipolar transistor and an N-channel MOSF.
Limited to ET only, the remaining area is P-channel MOSFE
Since the region where T is formed is used, a region surrounded by the groove and having a non-fixed potential is not formed.
It is possible to solve the problems of parasitic capacitance and routing of power supply wiring.

Next, as shown in FIG. 11, an insulator 58 is embedded in the separation groove 24. This insulator 58 is CVD
A silicon oxide film having a film thickness of about 500 nm is deposited on the entire surface of the SOI substrate 8 including the separation groove 24 by using a technique, and then the separation groove 24 is formed by the entire surface etch back by anisotropic etching such as RIE. It can be embedded inside. Further, since it is difficult to flatten the surface by performing the entire surface etch-back once, the insulating material is deposited again in the same manner at about 500 nm, and then the second etching-back is performed to perform the insulating material 5 again.
9 is embedded in the surface of the separation groove 24. Here, the polycrystalline silicon film 56 functions as a stopper film for two full-scale etchbacks. Further, the silicon oxide film 57 is over-etched and removed during the first overall etching. In this way, by embedding the insulating material in the isolation trench 24, the dielectric isolation structure is completed. As an alternative to the embedded insulator, polycrystalline silicon may be embedded. In this case, it is necessary to selectively oxidize the inner surface of the isolation trench 24 to form a silicon oxide film before burying the polycrystalline silicon.

After that, the polycrystalline silicon film 56 and the silicon nitride film 53 are removed. Next, a high-concentration n-type impurity is selectively introduced into the formation region of the bipolar transistor Q1, and as shown in FIG. 12, the collector extraction region 17 of the bipolar transistor Q1 formed of the n + type semiconductor region is formed.
To form. The collector extraction region 17 is provided so that its bottom surface contacts the n + type buried layer 16.
The collector series resistance is reduced together with the n + type buried layer 16. Thus, the substrate (including the SOI substrate 8 and the n-type epitaxial layer Epi) as the base of the semiconductor integrated circuit device having the Bi-CMOS structure is completed.

Next, as shown in FIG. 12, a p-type impurity 6 is added to the main surface of the n-type epitaxial layer Epi of the region NMOS.
Ion implantation is performed on each of 1, 62 and 63. The p
The type impurities 61, 62 and 63 are used as the photoresist mask 6
0 is used as a mask for introducing impurities. The plane layout pattern of the resist mask 60 is IM in FIG.
The opening is shown by and the alignment positioning is performed by the separation groove 24. In this embodiment, N-channel MOSF
The formation of the p-type well, which is the formation region of ETMN1 and MN2, is performed in two ion implantation steps. That is,
P-type impurities 61 for forming shallow p-type wells 39A and 39B
Ion implantation step and deep p-type wells 43A, 43
There is a step of ion-implanting the p-type impurity 62 for forming B. Further, the p-type impurities 62 for forming the deep p-type wells 43A and 43B are simultaneously introduced also under the field oxide film 23 which is an isolation region, and the p-type semiconductor region 44 which functions as a channel stopper. To form. The introduction conditions of the p-type impurities 61 and 62 are optimized in consideration of the subsequent heat treatment depending on the device characteristics and the element isolation characteristics. As an example thereof, the p-type impurity 61 is, for example, 10 ¹² [atoms / cm ^2] of about impurity concentration of boron fluoride (BF ₂₎ using a 60 [KeV]
It is introduced by an ion implantation method with a certain level of energy. Further, the p-type impurity 62 for forming the deep p-type wells 43A and 43B and the p-type semiconductor region 44 is, for example, 5 × 10 ¹² [atoms /
cm ² ], an impurity concentration of boron (B) is used, and 1
It is introduced by a high energy ion implantation method of about 50 [KeV]. Further, the same photoresist mask 60 is used to introduce the p-type impurity 63 for adjusting the threshold voltage of the N-channel MOSFET. The p-type impurity 63 is introduced by using, for example, boron fluoride (BF ₂ ) having an impurity concentration of about 5 × 10 ¹² [atoms / cm ² ] and 80 [KeV].
The ion implantation method with a certain level of energy is used. Also, the p
The mold well may be formed by one ion implantation step, or may be formed by three or more ion implantation steps. As described above, in the present invention, the impurities for forming the well are introduced after the field oxide film and the isolation trench, which are the element isolation regions, are formed. It is possible to suppress the diffusion in the direction by the separation groove. Furthermore, since the well can be formed in self-alignment with the field oxide film and the isolation trench, high integration can be achieved. Further, since the impurities for forming the well are introduced by high-energy ion implantation through the field oxide film, it is possible to simultaneously form the channel stopper region under the field oxide film.
Therefore, there is an advantage that the manufacturing process can be simplified. Also,
Since the channel stopper region is formed by high-energy ion implantation of p-type impurities through the field oxide film after the field oxide film is formed, a high temperature and a long time heat are applied when the field oxide film is formed. Never receive history.
Therefore, the impurities in the channel stopper region are
Since it can be prevented from leaking out in the channel direction of ET, the controllability of the threshold voltage of the MOSFET can be improved and the electrical reliability can be improved.

Next, as shown in FIG.
N-type impurities 65 and 66 are ion-implanted into the main surface of the n-type epitaxial layer Epi. For the n-type impurities 65 and 66, the photoresist mask 64 is used as a mask for introducing impurities. This resist mask 6
Reference numeral 4 is provided so as to selectively cover the regions NPN and NMOS, and the alignment positioning is performed by the separation groove 24.
In this embodiment, P-channel MOSFETs MP1, M
The formation of the n-type well, which is the P2 formation region, is performed in two ion implantation steps. That is, there are an ion implantation step of the n-type impurity 65 for forming the shallow n-type wells 25A and 25B and an ion implantation step of the n-type impurity 66 for forming the deep n-type wells 31A and 31B. Also, the n-type impurity 6 for forming the deep n-type wells 31A and 31B is formed.
6 is a field oxide film 2 which is an isolation region.
An n-type semiconductor region 44 which is also introduced into the lower part of 3 and functions as a channel stopper is formed. This n
The conditions for introducing the type impurities are optimized in consideration of the subsequent heat treatment depending on the device characteristics and element isolation characteristics. The n-type impurity 65 is, for example, phosphorus (P) having an impurity concentration of about 10 ¹² [atoms / cm ² ] and 120 [KeV].
It is introduced by an ion implantation method with a certain level of energy. As the n-type impurity 66, for example, divalent phosphorus (P) ions having an impurity concentration of about 5 × 10 ¹² [atoms / cm ² ] are used, and ions having an energy of about 300 [KeV] in terms of monovalent phosphorus ions. Introduce by the driving method. Further, the same photoresist mask 64 is used to introduce a p-type impurity 67 for adjusting the threshold voltage of the P-channel MOSFET. This p
The introduction of the type impurities 67 is, for example, 5 × 10 ¹² [atoms / c
m ² ], and boron fluoride (BF ₂ ) having an impurity concentration of about 30 [KeV] is used for the ion implantation method. The introduction of the p-type impurity 67 is performed by the N channel M
It can be shared with the p-type impurity 63 for adjusting the threshold voltage of the OSFET. In that case, after forming an isolation region, a photoresist mask that selectively covers only the region NPN is used. Region NMOS collectively,
A p-type impurity having a predetermined impurity concentration may be ion-implanted into the PMOS. Also, in general, arsenic, antimony,
The mass of n-type impurities such as phosphorus is larger than that of p-type impurities such as boron. Therefore, it is difficult to form a high-concentration buried layer by high-energy ion implantation of n-type impurities. However, in this embodiment, by setting the conductivity type of the epitaxial layer Epi and the upper substrate (n-type silicon layer 8C) as the base of well formation to n-type, the n-type for forming the deep n-type wells 31A and 31B is set. The impurity concentration of the impurities 66 is reduced to such an extent that high-energy ion implantation is possible. That is, when high-energy ion implantation is used, the substrate as a base is preliminarily n
It is important to type.

After the field oxide film which is the element isolation region and the isolation trench are thus formed, the P channel MOSF is formed.
Since the impurities for forming the n-type well, which is the formation region of ET, are introduced, the same effect as when forming the p-type well can be obtained. Further, since the formation regions of the n-type well and the p-type well are separated from each other in advance by the isolation trench which is an isolation region, the impurities of the n-type well and the p-type well do not mutually diffuse. Therefore, it is possible to prevent the formation of an ambiguous region whose conductivity type is unknown (a region where the impurity profile is unclear) at the boundary between the n-type well and the p-type well. It is possible to improve the target reliability and achieve high integration.

Next, as shown in FIG. 14, the n-type well 2
Gate insulating films 29A to 29D are formed on the main surfaces of 5A, 25B and p-type wells 39A, 39B, respectively. The gate insulating films 29A to 29D are formed by a steam oxidation method at a high temperature of about 800 to 900 ° C.
The film thickness is about m]. Next, the gate insulating film 29
A polycrystalline silicon film is formed on the entire surface of the SOI substrate including A to D. The polycrystalline silicon film is deposited by the CVD method to have a film thickness of about 200 to 300 [nm]. An n-type impurity (for example, phosphorus (P)) that reduces the resistance value is introduced into the polycrystalline silicon film by a thermal diffusion method or an ion implantation method. Next, an insulating film 32 is formed on the entire surface of the polycrystalline silicon film. The insulating film 32 is formed of a silicon oxide film of about 100 to 200 [nm] deposited by the CVD method. Next, the insulating film 3
2 and the polycrystalline silicon film are sequentially etched into a predetermined shape to form N-channel MOSFETs MN1 and MN2.
And gate electrodes 26A to 26D of the P-channel MOSFETs MP1 and MP2 are formed, respectively. The etching is performed by anisotropic etching such as RIE using an etching mask formed by a photolithography technique. The plane pattern of each gate electrode is GATE1 to GATE1 in FIG.
4 is shown. Next, the gate electrodes 26C and 2
The p-type wells 39A and 39B exposed from 6D, respectively
N-type impurities are selectively introduced into the respective main surface portions. As the n-type impurity, for example, phosphorus (P) having an impurity concentration of about 1 × 10 ¹³ [atoms / cm ² ] is used, and 50 [KeV] is used.
It is introduced by an ion implantation method with a certain level of energy. The n-type impurities are introduced in a self-aligned manner with respect to each of the gate electrodes 26C and 26D. Since this n-type impurity is introduced at a relatively low concentration, the N-channel MOSFET MN1,
Each of MN2 can be formed with an LDD structure. By introducing this n-type impurity, low-concentration source / drain regions 42A and 42B made of an n-type semiconductor region are formed, respectively. Next, the low concentration source / drain regions 42 are formed.
Similar to the formation of A and 42B, the gate electrodes 26A and 2B
P-type impurities are selectively introduced into the main surface portions of the n-type wells 25A and 25B exposed from 6B to form the low-concentration source / drain regions 30A and 30B of the P-channel MOSFETs MP1 and MP2. As the P-type impurity, boron fluoride (BF ₂ ) having an impurity concentration of about 1 × 10 ¹³ [atoms / cm ² ] is used, and 40 [Ke
V] is introduced by the ion implantation method.
This p-type impurity is introduced in self alignment with the gate electrodes 26A and 26B.

Next, as shown in FIG. 15, sidewall spacers 33 and 46 are formed on the respective side portions of the gate electrodes 26A, 26B, 26C and 26D. The sidewall spacers 33 and 46 are formed by depositing a silicon oxide film on the entire surface of the substrate, and etching back by anisotropic etching such as RIE by an amount corresponding to the thickness of the deposited silicon oxide film. can do. The silicon oxide films of the sidewall spacers 33 and 46 are formed by the CVD method using the inorganic silane gas and the nitric oxide gas as the source gas. This silicon oxide film has, for example, 200 [nm]
It is formed with a film thickness of about. This sidewall spacer 3
The length of 3, 46 in the gate length direction (channel length direction) is about 150 nm. Further, the anisotropic etching causes the gate electrodes 26A, 26B, 2
Gate insulating film 29A exposed from each of 6C and 26D
A part of D and the gate insulating film in the formation region of the bipolar transistor Q1 are over-etched and removed.
At this time, the n-type wells 25A and 25B and the p-type well 39A, which are the base of the removed gate insulating film,
The silicon layer on the main surface of 39B is also overetched by a small amount. After forming the sidewall spacers 33 and 46, heat treatment is performed at about 800 ° C. in an inert gas (for example, argon gas) atmosphere. By the heat treatment, the silicon oxide film forming the sidewall spacers 33 and 46 is densified, and the low-concentration source / drain regions 42A, 42B, 30A,
30B is activated to recover the damage to the silicon layer due to the overetching. Next, the bipolar transistor Q1 and the P-channel MOSFET MP1,
The MP2 formation region is covered with a mask made of a photoresist film using a photolithography technique. Next, using the mask as a mask for introducing impurities, n-type impurities are introduced into the main surface portions of the p-type wells 39A and 39B. This n-type impurity is mainly introduced in self alignment with the gate electrodes 26C and 26D and the sidewall spacers 46.
The n-type impurities are, for example, 10 ¹⁵ to 10 ¹⁶ [atoms / c
m ² ], and arsenic (As) with an impurity concentration of about 70
It is introduced by an ion implantation method with an energy of about 90 [KeV]. By introducing the n-type impurity, the p-type well 39
N-channel MOSFET MN1, on the main surface of A, 39B
High-concentration source / drain regions 40A, 41A and 40B, 41B of MN2 are formed. After that, the photoresist mask is removed.

Next, P-channel MOSFETs MP1 and M
A mask having an opening in the P2 formation region is formed. Although not shown, the mask is made of a photoresist film formed by a photography technique. Then, using the photoresist mask as a mask for introducing impurities, p-type impurities are introduced into the main surfaces of the n-type wells 25A and 25B. The p-type impurities are, for example, 10 ¹⁵ to 10
Boron fluoride (BF ₂ ) having an impurity concentration of about ¹⁶ [atoms / cm ² ] is used, and ion implantation is performed with an energy of about 70 to 90 [KeV]. By introducing this P-type impurity, the high-concentration source / drain regions 27A, 28A and 27B, 2 of the P-channel MOSFETs MP1, MP2 are introduced.
8B are formed respectively. After that, the photoresist mask mask is removed.

Next, heat treatment is applied to each of the introduced n-type impurities and p-type impurities to recover the damage due to ion implantation and activate the impurities. The heat treatment is performed at a high temperature of about 850 ° C. for about 10 minutes. By the process of forming the high concentration source / drain regions, the N channel MOSFETs MN1 and MN2 and the P channel MOSF shown in FIG. 2 are formed.
Each of ETMP1 and MP2 is substantially completed. The gate electrode material of the MOSFET is n + in this embodiment.
Although the type polycrystalline silicon is used, a gate electrode having a polycide structure in which a refractory metal layer such as tungsten (W) or molybdenum (MO) is stacked on the polycrystalline silicon and silicidized may be used.

Next, as shown in FIG. 16, for example, CV
A silicon oxide film 34 having a film thickness of about 100 nm is formed on the entire surface of the substrate by the D method. Next, a photoresist mask BP having an opening in the base forming region of the bipolar transistor is formed, and using this as an etching mask, the silicon oxide film 34 and a predetermined portion of the gate insulating film are selectively etched. By removing n
An opening DT is formed on the mold collector region 11.

Next, as shown in FIG. 17, the opening D
The polycrystalline silicon layer 13 is deposited on the entire surface of the substrate including on the T by, for example, the CVD method. The polycrystalline silicon layer 1
The film thickness of 3 is, for example, about 200 [nm]. The polycrystalline silicon layer 13 may be either an intrinsic state in which impurities are not introduced or a silicon layer in which n-type or p-type impurities are lightly doped. Next, the polycrystalline silicon layer 13
A p-type impurity is introduced therein. The p-type impurity is, for example, boron (B) having an impurity concentration of about 10 ¹⁵ to 10 ¹⁶ [atoms / cm ² ] and is introduced by an ion implantation method with energy of about 10 to 15 [keV]. Next, a photoresist mask EB1 for structuring the base extraction layer of the bipolar transistor is formed. By using the mask EB1 as an etching mask to pattern the polycrystalline silicon layer 13 by anisotropic etching such as RIE, for example, as shown in FIG. 18, a p + -type polycrystalline silicon layer 13C serving as a base extraction layer is formed. To form. Incidentally, in this state, p serving as the base extraction layer is formed.
The planar shape of the + type polycrystalline silicon layer 13C is simply a rectangle, and is not a ring shape which is the final shape.
Then, the mask EB1 is removed.

Next, as shown in FIG. 18, an interlayer insulating film 18 is formed on the entire surface of the substrate including the polycrystalline silicon layer 13C.
To form. The interlayer insulating film 18 is formed of a silicon oxide film deposited by a CVD method. Then, a photoresist mask EB2 for patterning the base extraction layer 13C of the bipolar transistor Q1 into a final shape.
To form. The mask EB2 is a mask pattern in which the regions where the intrinsic base and emitter of the bipolar transistor Q1 are to be formed are opened. Then, with the mask EB2 as an etching mask, the interlayer insulating film 18 and the base lead layer 13C are sequentially and selectively etched. For the etching, anisotropic etching such as RIE is used. By this etching, as shown in FIG. 19, base extraction layer 13C is patterned so as to surround the emitter region of bipolar transistor Q1. Then, the mask EB2 is removed. Next, a p-type impurity for forming the intrinsic base region 10 is introduced into the main surface portion of the collector region 11. The p-type impurities are, for example, 10 ¹³ to 10 ¹⁴ [atoms / c
Boron (B) having an impurity concentration of about m ² ] is used and is introduced by an ion implantation method with relatively low energy.

Next, as shown in FIG. 19, an insulating film (Si is formed on the side portion of the patterned base extraction layer 13C).
A sidewall spacer 14 made of O ₂ ) is formed. The spacer 14 is made of the LDD structure MOSFE.
Side wall spacers 33 and 46 such as TMN1 and M1
Similar to the above, it can be formed by etching back the insulating layer. The side wall spacer 14 defines the emitter formation region in a self-aligned manner.

Next, as shown in FIG. 20, a polycrystalline silicon layer 15 is formed on the entire surface of the substrate including the opening defined by the sidewall spacers 14. The polycrystalline silicon layer 15 is formed by, for example, a CVD method and has a film thickness of about 150 [nm]. next,
An n-type impurity is introduced into the polycrystalline silicon layer 15. The n-type impurity is, for example, 10 ¹⁶ [atoms / cm ² ].
Arsenic (As) with a high impurity concentration is used and is introduced by the ion implantation method. By introducing this n-type impurity, the polycrystalline silicon layer 15 becomes n + type and becomes a conductor.

Next, as shown in FIG. 20, a photoresist mask EB3 is selectively formed on the polycrystalline silicon layer 15 in the region NPN. The pattern of the mask EB3 is a formation pattern of the emitter extraction layer of the bipolar transistor Q1. Next, the polycrystalline silicon layer 15 is selectively removed by etching using the mask 15 as an etching mask. For the etching, anisotropic etching such as RIE is used. By the etching, the emitter extraction layer 15 of the bipolar transistor Q1 is formed as shown in FIG. afterwards,
By subjecting the substrate to heat treatment, each of the n-type impurities introduced into the n + -type polycrystalline silicon layer 15 and the p-type impurities introduced into the p + -type polycrystalline silicon layer 13C is removed from the main surface portion of the collector region 11. Drive in to spread. By this drive-in diffusion, the emitter region 9 of the bipolar transistor Q1 made of the n + type semiconductor region and the external base region 12 made of the p + type semiconductor region.
Are formed respectively. Further, the p-type impurities introduced in advance in the main surface portion of the collector region 11 are also activated by the heat treatment, and the intrinsic base region 10 made of the p-type semiconductor region is formed. The external base region 12 and the intrinsic base region 10 are electrically connected under the sidewall spacer 14 and are integrally formed. The heat treatment process substantially completes the bipolar transistor Q1.

Next, an interlayer insulating film 19 is formed on the entire surface of the substrate including the elements of the bipolar transistor Q1 and the MOSFETs MN1, MN2, MP1 and MP2. The interlayer insulating film 19 is, for example, a silicon oxide film, BPSG (B oro
is composed of n- P hosphorus- S ilicate G lass) film two-layer structure obtained by sequentially stacking the respective. The lower silicon oxide film is deposited by the CVD method using silane gas and nitric oxide gas as source gases. The lower silicon oxide film is formed to have a film thickness of, for example, about 100 [nm] to prevent impurities (each of P and B) from leaking from the upper BPSG film. The upper BPSG film is deposited by, for example, the CVD method.
The upper BPSG film is, for example, 300 to 500 [n
The film thickness is about m]. The BPSG film is subjected to a densification process and a reflow process in a nitrogen gas atmosphere at a temperature of about 900 to 1000 [° C.].
By this reflow, the surface of the upper BPSG film forming the interlayer insulating film 19 is flattened.

Next, the interlayer insulating films 19 and 18 and the insulating film 34 are sequentially and selectively etched by using ordinary photolithography and etching techniques to reach the collector extraction region 17 of the bipolar transistor. Connection hole CONT3, connection holes CONT2, CONT1, and P channel MOS reaching the emitter extraction layer 15 and the base extraction layer 13 of the bipolar transistor
Source / drain regions 27A of the FETs MP1 and MP2,
Connection holes CONT4 to 28A, 27B and 28B
7. Sources of N-channel MOSFETs MN1 and MN2
Connection holes CONT8 to 11 reaching the drain regions 40A, 41A and 40B, 41B are formed, respectively. After forming the connection holes, the base extraction layer 13C, the emitter extraction layer 15, the collector extraction region 17, and the source / drain regions 27A, 28A, 27 are formed through the connection holes.
B, 28B, 40A, 41A, 40B, 41B wiring layers (electrodes) 20, 21, 22, 35A, 3 respectively connected
6A, 35B, 36B, 47A, 48A, 47B, 48
Form B. The wiring layers 20, 21, 22, 35
A, 36A, 35B, 36B, 47A, 48A, 47
Each of B and 48B is formed by patterning a tungsten layer deposited by, for example, a CVD method by a normal photolithography and etching technique. Although not shown in FIG. 3, a power supply wiring formed in the same step as the wiring layer passes through the connection holes CONT16 and 17 shown in FIG. N channel MOSFE
Connected to the T well region. Although not shown in FIG. 3, the wiring layer also passes through the connection holes CONT 12 to 15 shown in FIG. 2 provided in the interlayer insulating film 19 to the gate electrodes 26A to D of the P channel MOSFET and the N channel MOSFET. Connected. Then, although not shown, the wiring layers 20, 21, 22, 35A, 36A, 3
An insulating film such as a silicon oxide film is formed on the entire surface of the substrate including 5B, 36B, 47A, 48A, 47B, and 48B, and further, the second layer wiring (for example, by a photolithography and etching technique) (for example, , Aluminum alloy wiring) are formed to electrically connect the respective semiconductor elements. By performing the above steps, Bi of the present invention can be obtained.
-A semiconductor device having a CMOS structure is almost completed.

Although the present invention has been specifically described based on the embodiments, it is not limited thereto. For example, as shown in FIG. 21, the n + type buried layer 16 for reducing the collector series resistance of the bipolar transistor Q1 is:
It may be formed on the entire surface of the n-type silicon layer 8C of the SOI substrate. By forming the n + type buried layer 16 on the entire surface of the n type silicon layer 8C, the bipolar transistor Q is formed.
Since it is possible to eliminate the step in the isolation region at the boundary between the formation region of No. 1 and the formation regions of the N-channel MOSFET and the P-channel MOSFET, not only the gate wiring but also the disconnection between the elements is a problem. Can be resolved, B
The electrical reliability of the semiconductor integrated circuit device having the i-CMOS structure can be further improved. Further, particularly when a semiconductor memory device is configured, the Bi-CMO of this embodiment is used.
S is advantageous for high integration and high speed. For example, the N-channel MO of the present embodiment is applied to the memory cell of the semiconductor memory device.
SFETMN1,2 and P-channel MOSFETMP
By applying Nos. 1 and 2, a full CMOS type memory cell composed of two CMOS inverter circuits in which each input and output are cross-coupled can be formed in a small area. Further, by applying the bipolar transistor Q1 having the double polysilicon structure of this embodiment to the peripheral circuits such as the address buffer circuit, the decoder circuit, the word driver circuit, the sense amplifier circuit, etc., the high speed operation is excellent. A semiconductor memory device can be configured.
Although the specific circuit configuration of the semiconductor memory device is not known, for example, Japanese Patent Application No. 3-53344 (filing date: February 25, 1991, assignee: Hitachi, Ltd.)
It is described in.

[0047]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in a semiconductor integrated circuit device having a CMOS, introduction of impurities for forming an N-type well and a P-type well, which are CMOS forming regions, is performed by using a field insulating film and an isolation groove, which are isolation regions. Since the isolation region is self-aligned after being formed, the semiconductor integrated circuit device having CMOS can be highly integrated.

[Brief description of drawings]

FIG. 1 shows an example of a chip layout of a semiconductor integrated circuit device having a Bi-CMOS structure of the present invention.

FIG. 2 shows a device plane layout of a semiconductor integrated circuit device having a Bi-CMOS structure of the present invention.

3 is a cross-sectional view corresponding to line A1-A2 shown in FIG.

FIG. 4 is a sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS configuration shown in FIGS. 2 and 3 in the order of manufacturing steps.

5 is a sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS structure shown in FIGS. 2 and 3 in the order of manufacturing steps.

FIG. 6 is a sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS structure shown in FIGS. 2 and 3 in the order of manufacturing steps.

FIG. 7 is a sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS structure shown in FIGS. 2 and 3 in the order of manufacturing steps.

FIG. 8 is a sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS structure shown in FIGS. 2 and 3 in the order of manufacturing steps.

FIG. 9 is a sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS structure shown in FIGS. 2 and 3 in the order of manufacturing steps.

FIG. 10 is a sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS structure shown in FIGS. 2 and 3 in the order of manufacturing steps.

FIG. 11 is a sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS structure shown in FIGS. 2 and 3 in the order of manufacturing steps.

12 is a sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS structure shown in FIGS. 2 and 3 in the order of manufacturing steps.

13 is a cross-sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS structure shown in FIGS. 2 and 3 in the order of manufacturing steps.

FIG. 14 is a sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS configuration shown in FIGS. 2 and 3 in the order of manufacturing steps.

FIG. 15 is a sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS structure shown in FIGS. 2 and 3 in the order of manufacturing steps.

16 is a sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS structure shown in FIGS. 2 and 3 in the order of manufacturing steps.

FIG. 17 is a cross-sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS structure shown in FIGS. 2 and 3 in the order of manufacturing steps.

FIG. 18 is a sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS structure shown in FIGS. 2 and 3 in the order of manufacturing steps.

FIG. 19 is a sectional view showing a method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS structure shown in FIGS. 2 and 3 in the order of manufacturing steps.

20 is a sectional view showing the method of manufacturing the semiconductor integrated circuit device having the Bi-CMOS structure shown in FIGS. 2 and 3 in the order of manufacturing steps.

FIG. 21 is a cross-sectional view of an essential part of a semiconductor integrated circuit device having a Bi-CMOS configuration which is a modification of the present invention.

[Explanation of symbols]

8 ... SOI substrate, NPN ... Bipolar transistor formation region, PMOS ... P-channel MOSFET formation region, N
MOS ... n channel MOSFET formation region, TR1, T
R2 ... Separation groove pattern, NPN-LOCOS, PMOS
LOCOS, NMOS LOCOS ... Field oxide film opening pattern, GATE ... Gate electrode pattern, CONT
... Connection hole, EB, BP ... Resist pattern, Q1 ... NP
N bipolar transistor, MP1MP2 ... p-channel MOSFET, MN1MN2 ... n-channel MOSFET
Is.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiro Hiramoto 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Nobuo Tanba 2326 Imai, Ome City, Tokyo Hitachi Device Co., Ltd. In the development center

Claims (16)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device having complementary MOSFETs, wherein an isolation groove for partitioning a first region and a second region of the main surface of the semiconductor substrate is provided on the main surface of the semiconductor substrate. And a step of forming the groove, after introducing a first impurity of the first conductivity type into the first region, by introducing a second impurity of the second conductivity type into the second region Forming a first conductivity type first well in the first region and a second conductivity type second well in the second region, and forming the complementary MOSFET on the main surface of the first well. Forming an N-channel MOSFET constituting the complementary well and forming a P-channel MOSFET constituting the complementary MOSFET on the main surface of the second well. 2. The first impurity and the second impurity are introduced by an ion implantation method and are self-aligned with respect to the isolation groove.
A method for manufacturing the semiconductor integrated circuit device described. 3. The method according to claim 2, further comprising the step of forming a field oxide film at a boundary between the first region and the second region before forming the isolation groove.
A method for manufacturing the semiconductor integrated circuit device described. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the isolation trench extends into the semiconductor substrate through the field oxide film. 5. The manufacturing of a semiconductor integrated circuit device according to claim 3, wherein the first impurity and the second impurity are introduced by high-energy ion implantation to pass through the field oxide film. Method. 6. The first impurity is introduced into the lower portion of the field oxide film to form a first channel stopper at the same time as the first well, and the second impurity is the field impurity.
4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the second channel stopper is formed below the cathode oxide film and is formed simultaneously with the second well. 7. A bipolar transistor and a complementary MOSF.
In a semiconductor integrated circuit device in which ET is integrated on the same semiconductor substrate, the bipolar transistor and the complementary MOSFET are provided in a single crystal silicon epitaxial layer provided on the semiconductor substrate, A high-concentration buried layer is provided on the junction surface between the single crystal silicon epitaxial layer in the region where the transistor is provided and the semiconductor substrate, and the single crystal silicon epitaxial layer in the region where the complementary MOSFET is provided; 4. The semiconductor integrated circuit device according to claim 3, wherein the high-concentration buried layer is not formed on the bonding surface of the semiconductor substrate. 8. A method for manufacturing a semiconductor integrated circuit device having a complementary MOSFET, comprising an SOI (Silicon O 2) having a single crystal silicon layer on an insulating layer.
n Insulator) substrate preparation step, partitioning a first region and a second region of the main surface of the single crystal silicon layer on the main surface of the single crystal silicon layer of the SOI substrate,
And, after the step of forming a groove for isolation reaching the insulating layer of the SOI substrate and the step of forming the groove, a first impurity of a first conductivity type is introduced into the first region, By introducing a second impurity of the second conductivity type into the two regions, a first well of the first conductivity type is formed in the first region, and a second well of the second conductivity type is formed in the second region. And a step of forming an N-channel MOSFET forming the complementary MOSFET on the main surface of the first well and forming a P-channel MOSFET forming the complementary MOSFET on the main surface of the second well. A method of manufacturing a semiconductor integrated circuit device, comprising: 9. The first impurity and the second impurity are introduced by an ion implantation method and are introduced in a self-aligned manner with respect to the isolation groove.
A method for manufacturing the semiconductor integrated circuit device described. 10. The method according to claim 9, further comprising the step of forming a field oxide film at a boundary between the first region and the second region before forming the isolation trench. A method for manufacturing the semiconductor integrated circuit device described. 11. A method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein said isolation trench extends to said single crystal silicon layer through said field oxide film. 12. The manufacturing method of a semiconductor integrated circuit device according to claim 10, wherein the first impurity and the second impurity are introduced by high-energy ion implantation to pass through the field oxide film. Method. 13. The first impurity is introduced below the field oxide film to form a first channel stopper at the same time as the first well, and the second impurity is formed in the field oxide film. 11. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the second channel stopper is formed in the lower portion and is formed at the same time as the second well. 14. The semiconductor integrated circuit device is a semiconductor memory device, and the complementary MOSFET constitutes a memory cell of the semiconductor memory device.
4. The method for manufacturing a semiconductor integrated circuit device according to 3. 15. A method of manufacturing the semiconductor integrated circuit device,
15. The method according to claim 14, further comprising the step of forming a bipolar transistor in a third region of the single crystal silicon layer of the SOI substrate, the bipolar transistor forming a peripheral circuit of the semiconductor memory device. A method for manufacturing the semiconductor integrated circuit device described. 16. The method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the memory cell is a full CMOS type cell.