JPS62179160A - Manufacture of mis-type semiconductor device - Google Patents

Abstract

PURPOSE:To form the device so that the ends of a source-drain diffused layer are positioned at the ends of upper and lower gate electrodes in the same way, by employing two exposure processes wherein a first gate electrode in used as a mask. CONSTITUTION:A pattern of a positive-type resist film 5 being identical with the one of a molybdenum gate electrode 2 in the lower layer is formed by executing exposure and development from the back of a substrate 1. With the film 5 used as a mask, subsequently, phosphorus is introduced in a polysilicon film 4 to form an N-type source-drain diffused layer 6. On the occasion, the exposure is so made that no light goes through the molybdenum gate electrode 2. After the pattern of the positive-type resist film 5 is exfoliated, an SiO2 film 7 is formed, and subsequently a negative-type resist film 8 is formed by coating. By executing exposure and development from the back of the substrate 1, a pattern of the negative-type resist 8 inverted to the one of the molybdenum gate electrode 2 in the lower layer is formed, and then, with said pattern used as a mask, the SiO2 film 7 in the lower layer is etched until the polysilicon film 4 in the layer located under the film 7 is disclosed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing an MIS type semiconductor device, and particularly to a method for manufacturing an MIS type semiconductor device having gate electrodes at the upper and lower portions of a channel portion.

[Conventional technology]

MTS type semiconductor device formed on a semiconductor film provided on an insulating film, so-called 50cm (Semiconductor
MIs-type semiconductor devices with onInsulator structure have smaller junction capacitance and wiring capacitance than conventional MrS-type semiconductor devices, and element isolation is complete and simple, making them suitable for high-speed large-scale integrated circuits (LSIs). It is said to be a device. Furthermore, according to this structure, a multilayered MIS type semiconductor device in which the MIS type semiconductor devices described above are stacked can be formed, and therefore it is expected to be applied to high-density LSI. However, in the case of a MIS type semiconductor device having an SOI structure, since electrodes cannot be connected to the substrate, a so-called substrate floating effect adversely affects the electrical characteristics of the MIS type semiconductor device.

In addition, particularly in the case of a MIS type semiconductor device having a multilayer SOI structure, malfunction may occur due to electrical interference from upper and lower active layers of the same type. As a structure that solved these problems, for example, Minoru Tsurushima reported the following structure in the proceedings of the 4th New Functional Device Technology Symposium, 1985, pages 156 to 160. As shown in FIG. 2, this is a MIS type semiconductor device having gate electrodes at the upper and lower portions of the channel portion. In the figure, 6 is a source/drain diffusion layer, 11 is a substrate, 12 is a first gate electrode, 13
14 is a first gate insulating film, 14 is an interlayer insulating film, 15 is a semiconductor film, 16 is a second gate insulating film, 17 is a second gate electrode, and 18 is an insulating film. In a MIS type semiconductor device having such a structure, the channel region is shielded by the upper and lower gate electrodes, and electrical interference from other active layers can be prevented, and the substrate floating effect can be controlled by the lower gate electrode. It is also possible. Furthermore, it is effective in suppressing short channel effects and improving subthreshold characteristics, which are problems when miniaturizing MIS type semiconductor devices. Furthermore, with such a structure, it is possible to form a channel region in the same way for either the upper or lower gate electrode, and various applications are expected in the future.

Incidentally, in order to manufacture such a MIS type semiconductor device having gate electrodes at the upper and lower portions of the channel portion, the following method is used, for example, according to Japanese Patent Laid-Open No. 56-88354. Taking FIG. 2 as an example, this method involves forming a first gate electrode 12, a first gate insulating film 13, and an interlayer insulating film 14 on a substrate 11, depositing a semiconductor film 15, and then The MIS type semiconductor device having the second gate electrode 17 is manufactured using exactly the same manufacturing method as a normal one-layer MIS type semiconductor device.

[Problem that the invention seeks to solve]

However, if such a method is used, it is possible to set the end of the source/drain diffusion layer 6 under the end of the gate electrode 17 using a self-line in the gate length direction in the figure; First gate electrode 12
As described above, the position of the end of the source/drain diffusion layer 6 cannot be set using the self-alignment line. Therefore, in order to set the position of the end of the source/drain diffusion layer 6 with respect to the first gate electrode 12 as described above using this method, it is necessary to take into account the alignment of the exposure and development steps. However, in general, the accuracy of alignment in the exposure and development steps depends on the mechanical accuracy of the exposure device, and it is inevitable that some misalignment will occur. As described above, according to the conventional manufacturing method, MIS having gate electrodes at the upper and lower parts of the channel part
It is impossible to manufacture a type semiconductor device such that the source/drain diffusion layers are in the same position with respect to the upper and lower gate electrodes.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing an MIS type semiconductor device having gate electrodes above and below a channel portion, which solves this problem.

[Means for solving problems]

The gist of the present invention is to provide a method for manufacturing an MIS type semiconductor device having gate electrodes at the upper and lower portions of a channel region, in which a first gate electrode pattern is formed on a substrate, and then a first insulating film and a first insulating film are formed. After sequentially forming a semiconductor film, a pattern corresponding to an element region is formed in the semiconductor film, and then a positive resist is applied to at least the substrate, the first insulating film, and the semiconductor film from the back side of the substrate. A pattern is formed in the positive resist by exposing and developing light with a wavelength that transmits and does not transmit the first gate electrode, and then, using the pattern of the positive resist as a mask, impurities of a conductive type are added to the semiconductor film. A source/drain diffusion layer is formed by ion implantation into the substrate, and then an insulating film is formed after peeling off the positive resist, and then a negative resist is applied to at least the substrate and the substrate from the back side of the substrate. forming a pattern on the negative resist by exposing and developing light with a wavelength that passes through the first insulating film, the semiconductor film, and the insulating film but does not pass through the first gate electrode; Using the pattern as a mask, the insulating film is etched until the semiconductor film is exposed, and then, after peeling off the negative resist, a second gate insulating film is formed on the semiconductor film, and then the second gate insulating film is etched. This is a method of manufacturing an MIS type semiconductor device characterized by forming a pattern of a second gate electrode that covers at least a gate insulating film.

[Principle/effect]

A feature of the present invention is that a MIS type semiconductor device having gate electrodes at the upper and lower portions of the channel portion can be manufactured such that the ends of the source/drain diffusion layers are located at the same position with respect to the upper and lower gate electrodes. In order to do this, it is necessary to pass through the substrate, the first gate insulating film, the semiconductor film, the insulating film on the semiconductor film, and the second gate insulating film that transmits the light of the wavelength of the light source used in the two exposure and development steps mentioned above. It is important to select a first gate electrode that does not

In the present invention, the light source for exposing the positive resist and the light source for exposing the negative resist may have the same wavelength or different wavelengths as long as the above conditions are satisfied. Further, the substrate used in the present invention may be either a semiconductor substrate or an insulating substrate as long as it satisfies the above conditions.

Further, the first gate electrode may be formed of a semiconductor film formed by a CVD method or a vapor deposition method, or a high melting point metal, as long as the above conditions are satisfied. Further, the first and second gate insulating films may be either an SiO□ film formed by a CVD method or a thermal oxide film, as long as the above conditions are satisfied. The semiconductor film may be a polysilicon film formed by a CVO method, a silicon film obtained by monocrystalizing the polysilicon film described above by laser annealing, or a compound semiconductor film such as GaAs, as long as the semiconductor film satisfies the above conditions. In addition, if the insulating film on the semiconductor film satisfies the above conditions, it can be a SiOg film or an S
Any i3N4 film may be used.

There are two important steps in the manufacturing method of the present invention. One method is to first form a first gate electrode, a first gate insulating film, and a semiconductor film on a substrate, then apply a positive resist thereon and expose it from the back side of the substrate to form a first gate electrode and a semiconductor film. This is a step of forming source/drain diffusion layers by forming the same resist pattern, and then using this resist pattern as a mask to inject conductive type impurities into the semiconductor film. The other method is to form an insulating film on the substrate from which the positive resist has been peeled off, and then apply a negative resist on top of it and expose it from the back of the substrate to reverse the pattern of the first gate electrode. Next, using this resist pattern as a mask, only the underlying insulating film corresponding to the first gate electrode pattern is removed by etching, and then the negative resist is peeled off and the second gate insulating film and the second gate insulating film are removed. This is a step of forming a second gate electrode pattern. These two processes are basically the same in that they use an exposure process using the first gate electrode as a mask. Therefore, by doing this, the source/drain diffusion layer can be formed so that the end of the source/drain diffusion layer is located at the end of the already formed first gate electrode in the gate length direction, and the source/drain diffusion layer can be formed in the same manner for the second gate electrode. It can be formed so that the end of the drain diffusion layer is located at the end of the second gate electrode.

Here, the transmittance of the light of the wavelength of the light source used in the two-time exposure process of the first gate electrode should be small enough to pattern the positive resist and negative resist on the substrate surface, as described above. In addition, as mentioned above, the transmittance of the substrate, the first gate insulating film, the semiconductor film, the insulating film on the semiconductor film, and the second gate insulating film to light of the wavelength of the light source used in the two exposures depends on the substrate surface. It only needs to be large enough to pattern positive and negative resists. These transmittances are determined not only by the material and thickness of each material but also by the wavelength of the exposure light source and the sensitivity of the positive resist and negative resist to that wavelength.

〔Example〕

Below, Figure 1 (at, (bl, (c), (d),
The present invention will be explained in detail with reference to the schematic cross-sectional view in (e).

In the figure, 1 is a quartz substrate, 2 is a molybdenum gate electrode, 3 is a first gate SiO□ film, 4 is a polysilicon film, 5 is a positive resist film, 6 is a source/drain diffusion layer, and 7 is S
in, film, 8 is a negative resist film, 9 is the second gate S
30g film, 10 is a phosphorus-doped polysilicon gate electrode.

First of all, as shown in FIG.
A Si0g film and a polysilicon film 4 corresponding to the active layer are sequentially deposited, and then a pattern corresponding to the element region of the polysilicon film 4 is formed, and then a positive resist film 5 is applied. Here the molybdenum gate electrode 2, the first gate) 5
The thickness of the iOz film 3 and the polysilicon film 4 is 400 mm each.
0 people, 400 people.

It has a capacity of 40,000 people and is formed using the CVD method. Further, the positive resist is spin-coated using MP-1400-27 to a thickness of 1.0 μm.

Next, as shown in FIG. 1 (bl), by exposing and developing the substrate 1 from the back side, a pattern of the positive resist film 5 identical to that of the molybdenum gate electrode 2 in the lower layer is formed, and then using this as a mask, a pattern of the positive resist film 5 is formed. 5X10 at 60 keV
By implanting "elm-" into the polysilicon film 4,
A type source/drain diffusion layer 6 is formed. At this time, the phosphorus needs to reach the bottom of the polysilicon film 4.

The light source used for exposure here was a 350W high-pressure mercury lamp with a wavelength of 4360 nm. Therefore, at this wavelength, enough light to form the pattern of the positive resist film 5 applied to the surface of the substrate passes through the quartz substrate 1, the first gate S30g film 3, and the polysilicon film 4 from the back side. However, the molybdenum gate electrode 2 is not transparent. Next, Figure 1 (C)
As shown in , after the pattern of the positive resist film 5 is peeled off, a SiO□ film 7 is formed, and then a negative resist lI! Apply 8. Here, the thickness of 5iOJi7 is 5
Formed by CVD method by 000 people. Further, the negative resist film 8 is spin-coated using OMR-85 to a thickness of 1.0 μm.

Next, as shown in FIG. 1 (dl), by exposing and developing the substrate 1 from the back side, a pattern of a negative resist film 8 inverted with respect to the molybdenum gate electrode 2 in the lower layer is formed, and this is then used as a mask. The underlying SiO□ film 7 is etched until the underlying polysilicon film 4 is exposed.The etching here uses reactive ion etching using a mixed gas of CP and H2.The conditions are CF,
and 11. The flow rates are 11005CC and 20SCC respectively.
The gas pressure is 80 mTorr, the high frequency power is 200 mTorr, and the target is polypropylene. The light source used for exposure was a high-pressure mercury lamp with a wavelength of 350 nm and a wavelength of 4,360 nm. Therefore, at this wavelength, sufficient light is emitted from the back surface of the quartz substrate 1 and the first gate to form a pattern of the negative resist film 8 applied to the surface of the substrate in the same manner as described above.
It passes through the SiQ□ film 3, polysilicon film 4, 5i02 film 7, but does not pass through the molybdenum gate electrode 2.

Finally, as shown in FIG. 1(e), after peeling off the pattern of the negative resist film 8, the exposed polysilicon film 4 is thermally oxidized to form a second SiO2 film 9. Then, the exposed second silicone) SiOz film 9
Form a pattern of the second phosphorus-doped polysilicon gate electrode 10 that is covered with a small amount of phosphorus. After forming 4,000 phosphorus-doped polysilicon films by the CVD method, a positive resist pattern was formed by a normal exposure and development process from the substrate surface using the positive resist and the light source, and then this was used as a mask. The underlying phosphorus-doped polysilicon film is etched to form a pattern for the phosphorus-doped polysilicon gate electrode 10. At this time, a mask for the exposure process is used to prevent misalignment in the exposure process in the gate length direction and for patterns to be formed during etching. In consideration of thinning, etc., a pattern corresponding to the phosphorus-doped polysilicon gate electrode 10 is mounted such that the exposed second gate SiO□ film is sufficiently covered with the phosphorus-doped polysilicon gate electrode 10. Use a mask.

As described above, according to the embodiment of the present invention, an n-channel MOS having gate electrodes at the upper and lower parts of the channel part
type semiconductor devices can be manufactured such that the ends of the source/drain diffusion layers are at the same position with respect to the upper and lower gate electrodes. Further, according to this embodiment, by changing the impurity to be implanted into the source/drain diffusion layer to a P type impurity, P
A channel MOS type semiconductor device can also be manufactured in the same manner.

Further, according to the present invention, a structure in which the source/drain diffusion layers are completely flat as shown in FIG. 2 can be manufactured by adding one step to the above embodiment. In other words, Figure 1 (
After forming a pattern of a molybdenum gate electrode 2 on a quartz substrate 1 in Al, a SiO□ film with a thickness of 6000 nm was formed by CV
The film is deposited by the D method, planarized by coating it with a resist, and then etched under conditions where the etching rate of the resist and the 5in2 film are the same until the molybdenum gate electrode is exposed. Next, Fig. 1 (a), (b
l, (C1, (dl,) By performing the same steps as (e), the structure shown in FIG. 2 can be manufactured.

In this example, a quartz substrate was used as the substrate, but other materials may not be used.
Either a substrate or a semiconductor substrate may be used. Further, although a molybdenum gate electrode is used as the first gate electrode, any other high melting point material or semiconductor material formed by CVD or vapor deposition may be used. Furthermore, although a 5iOz film formed by the CVD method was used as the first gate insulating film, it may be a 5iJ- film formed by the CVD method or any other insulating film. In addition, although a polysilicon film formed by the CVD method is used as the semiconductor thin film, it may be a silicon film made by monocrystalizing the polysilicon film described on the left by laser annealing or the like, or a compound semiconductor film such as GaAs, or an insulating film on the polysilicon film. to CV
Although the SiO2 film formed by the D method is used, a 5iJa film formed by the CVD method or any other insulating film may be used. Although the second gate insulating film is a SiO□ film obtained by thermally oxidizing the lower polysilicon film, it may be an SiO□ film formed by a CVD method, a 5iJ4 film, or any other insulating film. Further, although a phosphorus-doped polysilicon gate electrode is used as the second gate electrode, it may be made of a metal such as aluminum formed by CVD or vapor deposition, a high melting point metal such as molybdenum, or any other semiconductor material. Furthermore, the positive resist and the negative resist and the light source used to expose them may be other positive resists and negative resists, or a light source with a different wavelength may be used.

[Effects of the Invention] As described above, according to the manufacturing method of the present invention, a MIS type semiconductor device having gate electrodes at the upper and lower portions of the channel portion is formed by forming source/drain diffusion layers for the upper and lower gate electrodes in the same manner. This has the effect that the ends can be formed so as to be located at the ends of the upper and lower gate electrodes.

[Brief explanation of drawings]

Figure 1 (a), (b), (C1, (d), (e)
2 is a schematic cross-sectional view showing the main steps of an embodiment of the manufacturing method of the present invention in order of process, and FIG. 2 is a schematic cross-sectional view of a Mis-type semiconductor device obtained by the manufacturing method of the present invention. 1... Quartz substrate, 2... Molybdenum gate electrode, 3
...First gate SiO□ film, 4...Polysilicon film, 5...Positive resist film, 6...Source/drain diffusion layer, 7...SiO2 film, 8...Negative shaped resist film, 9... second gate SiO□ film, 10...
phosphorus-doped polysilicon gate electrode, 11...substrate,
12... First gate electrode, 13... First gate insulating film, 14... Interlayer insulating film, 15... Semiconductor film,
16... Second gate insulating film, 17... Second gate electrode, 18... Insulating film.

Claims (1)

[Claims] (1) M with gate electrodes at the top and bottom of the channel part
In a method for manufacturing an IS type semiconductor device, a first gate electrode pattern is formed on a substrate, a first insulating film and a semiconductor film are sequentially formed, and then a pattern corresponding to an element region is formed in the semiconductor film. is formed, and then a positive resist is applied, and exposed and developed from the back side of the substrate with light having a wavelength that passes through at least the substrate, the first insulating film, and the semiconductor film, but does not pass through the first gate electrode. A pattern is formed in the positive resist by forming a pattern, and then a source/drain diffusion layer is formed by ion-implanting a conductivity type impurity into the semiconductor film using the pattern of the positive resist as a mask. After peeling off the resist, an insulating film is formed, and then a negative resist is applied, which passes through at least the substrate, the first insulating film, the semiconductor film, and the insulating film from the back side of the substrate to form the first gate electrode. A pattern is formed on the negative resist by exposing it to light of a wavelength that does not transmit it and developing it. Then, using the pattern of the negative resist as a mask, the insulating film is etched until the semiconductor film is exposed. After peeling off the negative resist, a second gate insulating film is formed on the semiconductor film, and then the second gate insulating film is formed on the semiconductor film.
1. A method of manufacturing an MIS type semiconductor device, comprising forming a pattern of a second gate electrode covering at least a gate insulating film.