JPH065757B2 - Semiconductor device manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a MISFET manufacturing method.

[Prior Art] In recent years, a laminated device using an SOI substrate has been actively developed. As an example, a stacked CMOS S by AHShah etc.
RAM (1984. Symposium on VLSI Technology Digest of 1984, Symposium on VLSI Technology Digest of
Technical papers). Its structure is shown in FIG.
In the figure, 3 is a gate electrode, 4 is a gate insulating film, 21 is an n ⁺⁺ diffusion layer, 22 is a p ⁺ diffusion layer, 23 is an n ⁺ layer, and 24 is an Al electrode. From the figure, it can be seen that the gate electrode 3 is commonly used by the nMOSFET and the pMOSFET.

[Problems to be solved by the invention]

At this time, since the surface of the semiconductor film for the pMOSFET located in the upper layer is not flattened, the exposure accuracy of the photoresist used as the ion implantation mask does not increase when the source / drain regions are formed, which results in miniaturization of the device. Has become a drawback for. In order to miniaturize the device, it is necessary to form the source / drain regions by the self-alignment method.

The object of the present invention is to eliminate the above-mentioned conventional defects.
It is to provide a manufacturing method. In addition, since the semiconductor film that will be the channel region is flattened, the fabricated MISFET
In the drain current-gate voltage characteristic of, the slope of the subthreshold current can be made steeper.

[Means for solving problems]

The present invention is a MISFET manufacturing method using an SOI substrate, after forming an insulating film on a semiconductor substrate, the step of forming a gate electrode, the step of growing a gate insulating film on the surface of the gate electrode, the gate electrode film Forming a semiconductor film thicker than the total thickness of the gate insulating film and the gate insulating film, and then forming an impurity layer on the surface of the semiconductor film by an ion implantation method; A method of manufacturing a semiconductor device, comprising a step of polishing and planarizing the surface of the semiconductor film to the extent that an impurity layer other than the above is not removed.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Here, an nMOSFET using silicon as the MISFET can be taken as an example, but silicon can be used in other semiconductor films as well as in nM
Other than OSFET, pMOSFET is also possible.

In FIG. 1 (a), 1 μm SiO ₂ 2 is first formed on the Si substrate 1 by a thermal oxidation method. Next, n ⁺ poly-Si is LPCVD
After growing 0.5 μm by the method, the gate electrode 3 is formed by a resist process and an etching process. Next, an oxide film as a gate insulating film 4 is grown on the surface of the gate electrode 3 by 400 Å using a thermal oxidation method. Thereafter, as shown in FIG. 1 (b), a Si thin film 5 having a film thickness of 0.7 μm is deposited on the surface by the LPCVD method, and As is introduced into the Si thin film 5 by the ion implantation method. The injection condition at this time is that the acceleration voltage is 180 Ke.
V, the dose amount is 5 × 10 ¹⁵ cm ^-2 . Since the surface of this Si thin film 5 has irregularities corresponding to the shape of the gate electrode 3, the surface is polished by a mechanical chemical polishing method to flatten it, and the surface as shown in FIG. 1 (c) is obtained. A Si thin film 7 having a flat surface is obtained. At this time, the polishing does not expose the gate insulating film 4, and the source region 8 and the drain region 9 are not exposed.
The process is completed when the ion implantation layer that becomes Next, SiO ₂ 10 serving as a surface protection film is grown to a thickness of 0.5 μm by the LPCVD method, and then contact holes are formed in the source region 8 and the drain region 9 to form a source electrode 11 and a drain electrode 12 of Al. , MISFET is completed.

In this embodiment, As is used as the ion-implanted impurities and Si oxide film is used as the gate insulating film, but it is obvious that other materials may be used.

〔The invention's effect〕

The present invention, when manufacturing a MISFET having a gate electrode on the back surface of the SOI thin film, by flattening the SOI thin film surface using a treatment such as polishing, the source and drain regions can be formed in a self-aligned manner, and therefore, Since the element can be easily miniaturized and the channel region can be made thinner, the characteristics of the element can be improved.

[Brief description of drawings]

1 (a) to 1 (d) are sectional views showing an embodiment of the present invention in the order of steps, and FIG. 2 is a sectional view showing a conventional example. 1 ... Si substrate 2,10 ... SiO ₂ 3 ... Gate electrode 4 ... Gate insulating film 5,7 ... Si thin film 6 ... Ion implantation layer 8 ... Source region 9 ... Drain region 11 ... Source electrode 12 ... Drain electrode

Claims (1)

[Claims] 1. A method of manufacturing a MISFET using an SOI substrate, the method comprising: forming an insulating film on a semiconductor substrate; then forming a gate electrode; growing a gate insulating film on the surface of the gate electrode; Forming a semiconductor film thicker than the total film thickness of the gate electrode film and the gate insulating film, and then forming an impurity layer on the surface of the semiconductor film by an ion implantation method; and removing the impurity layer on the gate electrode, and A method of manufacturing a semiconductor device, comprising a step of polishing and planarizing the surface of the semiconductor film to such an extent that an impurity layer other than on the gate electrode is not removed.