JPH061837B2 - MIS type semiconductor device manufacturing method - Google Patents
MIS type semiconductor device manufacturing methodInfo
- Publication number
- JPH061837B2 JPH061837B2 JP7324887A JP7324887A JPH061837B2 JP H061837 B2 JPH061837 B2 JP H061837B2 JP 7324887 A JP7324887 A JP 7324887A JP 7324887 A JP7324887 A JP 7324887A JP H061837 B2 JPH061837 B2 JP H061837B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- type semiconductor
- resist
- mosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010408 film Substances 0.000 claims description 101
- 238000000034 method Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 19
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910008065 Si-SiO Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910006405 Si—SiO Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はMIS型半導体装置の製造方法に関する。The present invention relates to a method for manufacturing an MIS type semiconductor device.
絶縁膜上の半導体膜に形成したMIS型半導体装置、いわ
ゆるSOI(Semiconductor on Insulator)構造のMIS型半導
体装置は、従来のMIS型半導体装置に比較して接合容量
が小さく、素子分離が完全かつ簡便であることから高速
の大規模集積回路(LSI)に適した半導体装置であるとい
われる。The MIS type semiconductor device formed in the semiconductor film on the insulating film, that is, the MIS type semiconductor device having a so-called SOI (Semiconductor on Insulator) structure has a smaller junction capacitance than the conventional MIS type semiconductor device, and element isolation is complete and simple. Therefore, it is said to be a semiconductor device suitable for a high-speed large-scale integrated circuit (LSI).
従来、SOI構造のMIS型半導体装置の製造方法において、
その素子分離法の一つに絶縁体上の半導体膜のうち不要
な部分をすべて除去し、半導体膜をアイランド状に形成
する方法がある。例えばエス・デー・エス マルヒ(S.
D.S.Malhi)らは１９８２インタナショナルエレクトロン
デバイスミーティングテクニカルダイジェスト，(1982I
nternational Electron Devices Meeting Technical Di
gest)、107ページにこの方法を報告している。第２図は
このアイランド法で素子分離を行ったSOI型のMIS型半導
体装置の模式的断面図である。ここで第２図(a)のB-B面
の断面が第２図(b)である。図中、１はSi基板、２はSIO
2膜、３はSi膜中のソース・ドレイン拡散層、４はゲー
トSiO2膜、５はゲート電極、６は第１のチャネル領域、
７は第２チャネル領域である。Conventionally, in the manufacturing method of MIS type semiconductor device of SOI structure,
One of the element isolation methods is a method of removing an unnecessary portion of the semiconductor film on the insulator and forming the semiconductor film in an island shape. For example, S.D.M.March (S.
DS Malhi et al., 1982 International Electron Device Meeting Technical Digest, (1982I
nternational Electron Devices Meeting Technical Di
gest), page 107, and report this method. FIG. 2 is a schematic cross-sectional view of an SOI type MIS type semiconductor device in which elements are separated by this island method. Here, the cross section of the plane BB in FIG. 2 (a) is shown in FIG. 2 (b). In the figure, 1 is a Si substrate, 2 is SIO
2 films, 3 source / drain diffusion layers in Si film, 4 gate SiO 2 film, 5 gate electrode, 6 first channel region,
Reference numeral 7 is a second channel region.
しかしアイランド法で素子分離を行ったSOI構造のMIS型
半導体装置（MIS型半導体装置／SOI）の場合、第２図
(b)に示すようにSi膜上の通常の第１のチャネル領域６
の他にSi膜の側壁に第２のチャネル領域７が形成され
る。これら第１および第２のチャネル領域6,7は、それ
ぞれ第１のMIS型半導体装置と第２の半導体装置を形成
し、これら第１および第２のMIS型半導体装置は並列に
結合したことを等価である。この場合、第１のチャネル
領域と同様に第２のチャネル領域７においてもソースと
ドレイン間に電流が流れはじめるゲート電極５への印加
電圧（閾値電圧、Vt）が存在する。このため、第１のMI
S型半導体装置６の|Vt1|と第２のMIS型半導体装置７の|
Vt2|との関係が|Vt2|＜|Vt1|となった場合、MIS型半導
体装置/SOIのVtは第２のMIS型半導体装置のVT2に等しく
なる。しかしながら、一般にVtはゲート膜厚、チャネル
領域の不純物濃度や結晶性に依存し、これらの制御が難
しい第２のMIS型半導体装置７においてはVt2を制御する
ことは非常に難しい。それゆえ|Vt2|＜|Vt1|の場合、MI
S型半導体装置/SOIのVtは、作製目的である第１のMIS型
半導体装置６のVt1より低下し、またばらつきも増大す
る。However, in the case of a MIS type semiconductor device (MIS type semiconductor device / SOI) having an SOI structure in which elements are isolated by the island method, FIG.
As shown in (b), the normal first channel region 6 on the Si film
Besides, a second channel region 7 is formed on the side wall of the Si film. These first and second channel regions 6 and 7 respectively form a first MIS type semiconductor device and a second semiconductor device, and these first and second MIS type semiconductor devices are connected in parallel. Are equivalent. In this case, there is an applied voltage (threshold voltage, Vt) to the gate electrode 5 where a current starts to flow between the source and the drain in the second channel region 7 as in the first channel region. Therefore, the first MI
| Vt 1 | of the S-type semiconductor device 6 and | of the second MIS-type semiconductor device 7.
Vt 2 | relationship with the | Vt 2 | <| Vt 1 | when a, vt of the MIS type semiconductor device / SOI is equal to VT 2 of the second MIS type semiconductor device. However, in general, Vt depends on the gate film thickness, the impurity concentration and crystallinity of the channel region, and it is very difficult to control Vt 2 in the second MIS type semiconductor device 7 where these are difficult to control. Therefore, if | Vt 2 | <| Vt 1 |
The Vt of the S-type semiconductor device / SOI is lower than the Vt 1 of the first MIS-type semiconductor device 6 which is the manufacturing purpose, and the variation is increased.
本発明の目的は、上述した従来の問題点を解決したSOI
構造のMIS型半導体装置の製造方法を提供することにあ
る。The object of the present invention is to solve the above-mentioned conventional problems of SOI.
It is to provide a method of manufacturing a MIS type semiconductor device having a structure.
本発明は絶縁膜上に形成された半導体薄膜にMIS型半導
体装置を形成する方法において、前記半導体薄膜上に第
１の酸化膜、窒化膜を形成し、その表面にレジストを塗
布し、前記レジストがMIS型トランジスタを作製する素
子領域上に残るようにパターンニングした後、エッチン
グにより前記レジストをマスクにして前記窒化膜と第１
の酸化膜とをパターンニングした後、前記レジスト、窒
化膜、第１の酸化膜をマスクにして前記半導体膜をその
膜厚が半分以下になるまでエッチングにより除去して、
前記半導体膜中に不純物をイオン注入し、その後、前記
レジストを除去し、酸化処理を施して素子領域以外の前
記半導体膜を第２の酸化膜にした後、前記窒化膜と第１
の酸化膜を除去し、その後、前記半導体膜の研磨により
基板表面を平坦化して素子分離を行うことを特徴とする
MIS型半導体装置製造方法である。The present invention relates to a method of forming a MIS type semiconductor device on a semiconductor thin film formed on an insulating film, comprising forming a first oxide film and a nitride film on the semiconductor thin film, applying a resist on the surface thereof, Patterning is performed so as to remain on the element region where the MIS type transistor is manufactured, and then the nitride film and the first film are formed by etching using the resist as a mask.
After patterning the oxide film of, the resist film, the nitride film, and the first oxide film are used as a mask to remove the semiconductor film by etching until the film thickness becomes half or less,
Impurities are ion-implanted into the semiconductor film, the resist is removed, and an oxidation treatment is performed to form the semiconductor film other than the element region into a second oxide film, and then the nitride film and the first film are formed.
The oxide film is removed, and then the substrate surface is flattened by polishing the semiconductor film to perform element isolation.
It is a method for manufacturing an MIS type semiconductor device.
以下、本発明について実施例を用いて説明する。本実施
例においては、半導体膜としてSi膜，絶縁膜としてSiO2
膜，MIS型半導体装置としてnチャネルMOSFETを用いてい
る。Hereinafter, the present invention will be described using examples. In this embodiment, a Si film is used as the semiconductor film and SiO 2 is used as the insulating film.
An n-channel MOSFET is used as the film and MIS type semiconductor device.
第１図はSOI構造のnチャネルMOSFETの製造工程を示す模
式的断面図である。SOI構造の基板は第１図(a)に示すよ
うにSi基板上に膜厚１μｍのSiO2膜２，膜厚０．５μｍ
のSi膜８が順次形成されたものを用いる。このSi膜８上
に第１図(b)に示すように膜厚０．０４μｍのSiO2膜11
と膜厚0.12μｍのSi3N4膜12とを順次形成する。次にSi3
N4膜12上に第１図(c)に示すようにレジスト９を塗布
し、MOSFETの素子領域上にレジスト９が残るようにパタ
ーンニングする。その後、レジスト９をマスクにしてSi
3N4膜12とSiO2膜11をドライエッチングし、さらにSi膜
８を膜厚0.3μｍだけドライエッチングで除去する。そ
の後、第１図(d)に示すように、レジスト９をマスクに
してSi膜８のうちの領域13にボロンをイオン注入する。
注入条件は加速電圧150KeV、ドーズ量５×１０１３cm-2
である。その後、領域13のSi膜８をすべての酸化に必要
な条件で酸化を行い、SiO2膜10を得る。この時、ボロン
をイオン注入したSi膜は、イオン注入しなかったSi膜に
比べて酸化速度が約３倍速い。このため領域13のSi膜８
（膜厚0.2μｍ）が酸化されたときには、領域13以外のS
i膜８の側面は表面から0.07μｍだけ酸化され、試料断
面は第１図(e)に示すようになる。次にSi3N4膜12を除去
した後、SiO2膜が0.07μｍだけ除去するのに必要な時間
だけSiO2膜のウェットエッチングを行う。その結果、第
１図(f)に示すように、Si膜８がSiO2膜10の表面から約
0.13μｍ飛び出した基板が得られる。その後、ポリシン
グによりSi膜８を薄膜化する。薄間化が進み、Si膜８と
SiO2膜10の厚さが同じになると、SiO2のポリシング進行
速度はSiのそれに比べて非常に遅いのでSiO2膜10の領域
はポリシングのストツパーとなり、それ以上ポリシング
は進まなくなる。この結果、第１図(g)に示すような基
板表面が平坦であり、かつSi膜８が素子分離されたSOI
構造の基板が得られる。FIG. 1 is a schematic sectional view showing a manufacturing process of an n-channel MOSFET having an SOI structure. As shown in Fig. 1 (a), the SOI structure substrate has a SiO 2 film with a film thickness of 1 μm and a film thickness of 0.5 μm on the Si substrate.
The Si film 8 is sequentially used. On this Si film 8, as shown in FIG. 1 (b), a SiO 2 film 11 with a thickness of 0.04 μm is formed.
And a Si 3 N 4 film 12 having a film thickness of 0.12 μm are sequentially formed. Then Si 3
A resist 9 is applied on the N 4 film 12 as shown in FIG. 1 (c), and patterned so that the resist 9 remains on the element region of the MOSFET. Then, using the resist 9 as a mask, Si
The 3 N 4 film 12 and the SiO 2 film 11 are dry-etched, and the Si film 8 is removed by a dry-etching process to a thickness of 0.3 μm. Then, as shown in FIG. 1D, boron is ion-implanted into the region 13 of the Si film 8 using the resist 9 as a mask.
The implantation conditions are an acceleration voltage of 150 KeV and a dose of 5 × 10 13 cm -2.
Is. After that, the Si film 8 in the region 13 is oxidized under the conditions necessary for all oxidation to obtain the SiO 2 film 10. At this time, the Si film in which boron is ion-implanted has an oxidation rate about 3 times faster than the Si film in which ion is not ion-implanted. Therefore, the Si film 8 in the region 13
When (thickness 0.2 μm) is oxidized, S except for region 13
The side surface of the i film 8 is oxidized by 0.07 μm from the surface, and the sample cross section becomes as shown in FIG. 1 (e). Next, after removing the Si 3 N 4 film 12, wet etching of the SiO 2 film is performed for a time required to remove the SiO 2 film by 0.07 μm. As a result, as shown in FIG. 1 (f), the Si film 8 is removed from the surface of the SiO 2 film 10.
A substrate protruding by 0.13 μm can be obtained. Then, the Si film 8 is thinned by polishing. As thinning progresses, Si film 8
When the thickness of the SiO 2 film 10 is the same, the polishing progress speed of SiO 2 is much slower than that of Si, so that the region of the SiO 2 film 10 becomes a stopper for polishing, and the polishing cannot proceed further. As a result, as shown in FIG. 1 (g), the surface of the substrate is flat, and the Si film 8 is an element-isolated SOI.
A substrate of structure is obtained.
この基板を用い作製したときのSOI構造のMOSFETの模式
的断面図を第１図(h),(I)に示す。ここで第１図(h)のＩ
−Ｉ面の断面図が第１図(i)である。図中、３はMOSFET
のソース・ドレイン拡散層、４はゲートSiO2膜、５はゲ
ート電極、６は第１のチャネル領域、７は第２のチャネ
ル領域である。Schematic cross-sectional views of a MOSFET having an SOI structure manufactured using this substrate are shown in FIGS. 1 (h) and 1 (I). Here, I in FIG. 1 (h)
A cross-sectional view of the −I plane is shown in FIG. 1 (i). In the figure, 3 is a MOSFET
Is a source / drain diffusion layer, 4 is a gate SiO 2 film, 5 is a gate electrode, 6 is a first channel region, and 7 is a second channel region.
本発明のSOI型MOSFETも従来法と同様に、Si膜８の上面
の第１のチャネル領域に形成される第１のMOSFETとSi膜
８の側壁の第２のチャネル領域に形成される第２のMOSF
ETが並列に結合して構成されている。ただし、本発明の
場合にはSiO2膜10が存在しているために第２のMOSFETの
ゲートSiO2膜は第１のMOSFETのゲートSiO2膜よりも厚
い。Similarly to the conventional method, the SOI type MOSFET of the present invention also includes a first MOSFET formed in the first channel region on the upper surface of the Si film 8 and a second MOSFET formed in the second channel region on the sidewall of the Si film 8. MOSF
It is composed of ETs connected in parallel. However, in the case of the present invention it is thicker than the second is the MOSFET gate SiO 2 film gate SiO 2 film of the first MOSFET to the SiO 2 film 10 is present.
ここでnチャネルMOSFETのVtはSi−SiO2界面の界面準位
が小さいとすると、 また ここでＶFBはフラットバンド電圧、ΨBはSiのフェルミ
準位、ks,kiはそれぞれシリコン、シリコン酸化膜の比
誘電率，ε0は誘電率、qは電子の電荷量、Naは単位体積
あたりのアクセプタ不純物の密度、Ciはゲート酸化膜の
単位面積あたりのキャパシタンス、ｄはゲート酸化膜厚
である。Now Vt of n-channel MOSFET is a small interface state of Si-SiO 2 interface, Also Here, V FB is the flat band voltage, Ψ B is the Fermi level of Si, ks and ki are the relative permittivities of silicon and silicon oxide films, ε 0 is the permittivity, q is the charge of electrons, and Na is the unit volume. Is the density of acceptor impurities per unit area, Ci is the capacitance per unit area of the gate oxide film, and d is the gate oxide film thickness.
ゲート酸化膜が厚くなると前述の式よりVtは高くなる。
本発明の場合、第２のMOSFETのゲート酸化膜は第１のMO
SFETのゲート酸化膜より厚くなるので、第１，第２のMO
SFET閾値電圧Vt1,Vt2の関係はVt1<Vt2となる。また、一
般に第１のMOSFETのチャネル幅は第２のMOSFETのそれよ
り大きい。それゆえ第１，第２のMOSFETのソース・ドレ
イン間電流ID1,ID2の関係は常にID1>ID2となり、SOI構
造のMOSFETのソース・ドレイン間電流は第１のMOSFETの
ソース・ドレイン間電流で近似できる。すなわち、SOI
構造のMOSFETの静特性は第１のMOSFETの静特性にほとん
ど等しくなる。それゆえ、従来法で問題となった第２の
MOSFETによるSOI構造のMOSFETのVtの低下やばらつきは
生じない。As the gate oxide film becomes thicker, Vt becomes higher than the above equation.
In the case of the present invention, the gate oxide film of the second MOSFET is the first MO
Since it is thicker than the gate oxide film of SFET, the first and second MO
The relationship between the SFET threshold voltages Vt 1 and Vt 2 is Vt 1 <Vt 2 . In addition, the channel width of the first MOSFET is generally larger than that of the second MOSFET. Therefore, the relation between the source-drain currents I D1 and I D2 of the first and second MOSFETs is always I D1 > I D2 , and the source-drain current of the SOI structure MOSFET is the source-drain of the first MOSFET. Can be approximated by the inter-current. That is, SOI
The static characteristics of the structured MOSFET are almost equal to the static characteristics of the first MOSFET. Therefore, the second problem
There is no decrease or variation in Vt of the SOI structure MOSFET due to the MOSFET.
以上実施例においては、半導体膜としてSi膜、絶縁膜と
してSiO2膜、MIS型半導体装置としてMOSFETを用いた
が、他の半導体膜、絶縁膜、チャネルタイプのMIS型半
導体装置を用いても問題はない。In the above examples, the Si film is used as the semiconductor film, the SiO 2 film is used as the insulating film, and the MOSFET is used as the MIS type semiconductor device. However, the use of another semiconductor film, an insulating film, or a channel type MIS type semiconductor device causes a problem. There is no.
以上のように、本発明によればSOI型MOSFETにおけるVt
の低下やばらつきの増大、またリーク電流の増大等を抑
制することができる。As described above, according to the present invention, Vt in the SOI type MOSFET is
It is possible to suppress a decrease in voltage, increase in variation, increase in leak current, and the like.
また、ポリシングにより薄膜のSOI型MOSFETを作製する
ことができる効果を有する。Further, there is an effect that a thin film SOI type MOSFET can be manufactured by polishing.
第１図(a)〜(h)は本発明によるSOI型MOSFETの製造工程
の実施例を工程順に示す模式的断面図、(i)は(h)のＩ−
Ｉ線断面図、第２図(a)は従来法で素子分離を行ったSOI
型MOSFETの模式的断面図、(b)は(a)のＢ−Ｂ線断面図で
ある。 1…Si基板、 2，10，11…SiO2膜 3…MOSFETのソース・ドレイン拡散層 4…ゲートSiO2膜5…ゲート電極 6…第１のチャネル領域 7…第２のチャネル領域 8…Si膜 9……レジスト 12…Si3N4膜 13…Si膜８のうちボロンをイオン注入する領域1 (a) to 1 (h) are schematic cross-sectional views showing an embodiment of a process for manufacturing an SOI type MOSFET according to the present invention in the order of steps, and (i) is an I- line in (h).
A cross-sectional view taken along line I, Figure 2 (a) shows SOI with element isolation by the conventional method.
3B is a schematic cross-sectional view of the type MOSFET, and FIG. 3B is a cross-sectional view taken along line BB of FIG. 1 ... Si substrate, 2, 10, 11 ... SiO 2 film 3 ... MOSFET source / drain diffusion layer 4 ... Gate SiO 2 film 5 ... Gate electrode 6 ... First channel region 7 ... Second channel region 8 ... Si Film 9 ... Resist 12 ... Si 3 N 4 film 13 ... Region of Si film 8 where boron is ion-implanted
Claims (1)
半導体装置を形成する方法において、前記半導体薄膜上
に第１の酸化膜、窒化膜を形成し、その表面にレジスト
を塗布し、前記レジストがMIS型トランジスタを作製す
る素子領域上に残るようにパターンニングした後、エッ
チングにより前記レジストをマスクにして前記窒化膜と
第１の酸化膜とをパターンニングした後、前記レジス
ト、窒化膜、第１の酸化膜をマスクにして前記半導体膜
をその膜厚が半分以下になるまでエッチングにより除去
して、前記半導体膜中に不純物をイオン注入し、その
後、前記レジストを除去し、酸化処理を施して素子領域
以外の前記半導体膜を第２の酸化膜にした後、前記窒化
膜と第１の酸化膜を除去し、その後、前記半導体膜の研
磨により基板表面を平坦化して素子分離を行うことを特
徴とするMIS型半導体装置製造方法。1. A method of forming a MIS type semiconductor device on a semiconductor thin film formed on an insulating film, wherein a first oxide film and a nitride film are formed on the semiconductor thin film, and a resist is applied to the surface of the first oxide film and the nitride film. After patterning the resist so that it remains on the element region where the MIS transistor is formed, the resist and the nitride film are patterned by etching using the resist as a mask to form the nitride film and the first oxide film. The semiconductor film is removed by etching using the first oxide film as a mask until the film thickness becomes half or less, impurities are ion-implanted into the semiconductor film, and then the resist is removed and an oxidation treatment is performed. Is applied to make the semiconductor film other than the element region a second oxide film, the nitride film and the first oxide film are removed, and then the substrate surface is planarized by polishing the semiconductor film. MIS semiconductor device manufacturing method characterized by performing the isolation Te.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7324887A JPH061837B2 (en) | 1987-03-26 | 1987-03-26 | MIS type semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7324887A JPH061837B2 (en) | 1987-03-26 | 1987-03-26 | MIS type semiconductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63237573A JPS63237573A (en) | 1988-10-04 |
| JPH061837B2 true JPH061837B2 (en) | 1994-01-05 |
Family
ID=13512686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7324887A Expired - Lifetime JPH061837B2 (en) | 1987-03-26 | 1987-03-26 | MIS type semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH061837B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5225356A (en) * | 1991-01-14 | 1993-07-06 | Nippon Telegraph & Telephone Corporation | Method of making field-effect semiconductor device on sot |
| JP3078720B2 (en) * | 1994-11-02 | 2000-08-21 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP3249892B2 (en) * | 1994-11-28 | 2002-01-21 | 三菱電機株式会社 | Method for manufacturing semiconductor device having SOI structure |
-
1987
- 1987-03-26 JP JP7324887A patent/JPH061837B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63237573A (en) | 1988-10-04 |
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