JPH0569313B2 - - Google Patents
Info
- Publication number
- JPH0569313B2 JPH0569313B2 JP7324787A JP7324787A JPH0569313B2 JP H0569313 B2 JPH0569313 B2 JP H0569313B2 JP 7324787 A JP7324787 A JP 7324787A JP 7324787 A JP7324787 A JP 7324787A JP H0569313 B2 JPH0569313 B2 JP H0569313B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- mosfet
- resist
- semiconductor device
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 52
- 239000004065 semiconductor Substances 0.000 claims description 41
- 239000010409 thin film Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 4
- 239000011261 inert gas Substances 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- -1 oxygen ions Chemical class 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 16
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はMIS型半導体装置の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing an MIS type semiconductor device.
絶縁膜上の半導体膜に形成したMIS型半導体装
置、いわゆるSOI（Semiconductor on
Insulator）構造のMIS型半導体装置は、従来の
MIS型半導体装置に比較して接合容量が小さく、
素子分離が完全かつ簡便であることから高速の大
規模集積回路（LSI）に適した半導体装置である
といわれる。
MIS type semiconductor device formed on a semiconductor film on an insulating film, so-called SOI (Semiconductor on
MIS type semiconductor devices with an insulator structure are
Junction capacitance is smaller compared to MIS type semiconductor devices,
Because element isolation is complete and simple, it is said to be a semiconductor device suitable for high-speed large-scale integrated circuits (LSI).
従来、SOI構造のMIS型半導体装置の製造方法
において、その素子分離法の一つに絶縁体上の半
導体膜のうち不要な部分をすべて除去し半導体膜
をアイランド状に形成する方法がある。例えばエ
ス・デー・エス マルヒ（S.D.S.Malhi）らは
1982インタナシヨナルエレクトロンデバイスミー
テイングテクニカルダイジエスト，
（1982International Electron Devices Meeting
Technical Digest）、107ページにこの方法を報
告している。第２図はこのアイランド法で素子分
離を行つたSOI型のMIS型半導体装置の模式的断
面図である。ここで第２図ａのＢ−Ｂ面の断面が
第２図ｂの断面図である。図中、１はSi基板、２
はSiO2膜、３はSi膜中のソース・ドレイン拡散
層、４はゲートSiO2膜、５はゲート電極、６は
第１のチヤネル領域、７は第２のチヤネル領域で
ある。 Conventionally, in a method of manufacturing a MIS type semiconductor device having an SOI structure, one of the element isolation methods is a method of removing all unnecessary portions of a semiconductor film on an insulator and forming the semiconductor film in an island shape. For example, SDSMalhi et al.
1982 International Electron Device Meeting Technical Digest,
(1982International Electron Devices Meeting
Technical Digest), page 107, reports on this method. FIG. 2 is a schematic cross-sectional view of an SOI-type MIS-type semiconductor device in which element isolation is performed using this island method. Here, the cross section taken along line B-B in FIG. 2a is the cross-sectional view in FIG. 2b. In the figure, 1 is a Si substrate, 2
3 is a SiO 2 film, 3 is a source/drain diffusion layer in the Si film, 4 is a gate SiO 2 film, 5 is a gate electrode, 6 is a first channel region, and 7 is a second channel region.
しかしアイランド法で素子分離を行つたSOI構
造のMIS型半導体装置（MIS型半導体装置／
SOI）の場合、第２図ｂに示すようにSi膜上の通
常の第１のチヤネル領域６の他にSi膜の側壁に第
２のチヤネル領域７が形成され、これら第１およ
び第２のチヤネル領域６，７は、それぞれ第１お
よび第２のMIS型半導体装置を形成し、これらの
第１，第２のMIS型半導体装置は並列に結合した
ことと等価である。この場合、第１のチヤネル領
域６と同様に第２のチヤネル領域７においてもソ
ースとドレイン間に電流が流れはじめるゲート電
極５への印加電圧（閾値電圧、Vt）が存在する。
このため、第１のMIS型半導体装置の｜Vt1｜と
第２のMIS型半導体装置の｜Vt2｜との関係が｜
Vt2｜＜｜Vt1｜となつた場合、MIS型半導体装
置／SOIのVtは第２のMIS型半導体装置のVt2に
等しくなる。しかしながら、一般にVtはゲート
膜厚、チヤネル領域の不純物濃度や結晶性に依存
し、これらの制御が難しい第２のMIS型半導体装
置においてはVt2を制御することは非常に難し
い。それゆえ｜Vt2｜＜｜Vt1｜の場合、MIS型
半導体装置／SOIのVtは、作製目的である第１の
MIS型半導体装置６のVt1より低下し、またばら
つきも増大する。
However, an MIS type semiconductor device with an SOI structure (MIS type semiconductor device/
In the case of SOI), in addition to the usual first channel region 6 on the Si film, a second channel region 7 is formed on the side wall of the Si film, as shown in FIG. Channel regions 6 and 7 form first and second MIS type semiconductor devices, respectively, and these first and second MIS type semiconductor devices are equivalent to being coupled in parallel. In this case, in the second channel region 7 as well as in the first channel region 6, there is a voltage (threshold voltage, Vt) applied to the gate electrode 5 at which a current begins to flow between the source and drain.
Therefore, the relationship between |Vt 1 | of the first MIS type semiconductor device and |Vt 2 | of the second MIS type semiconductor device is |
When Vt 2 |<|Vt 1 |, the Vt of the MIS semiconductor device/SOI becomes equal to the Vt 2 of the second MIS semiconductor device. However, in general, Vt depends on the gate film thickness, the impurity concentration and crystallinity of the channel region, and it is very difficult to control Vt 2 in the second MIS type semiconductor device where these are difficult to control. Therefore, in the case of |Vt 2 |<|Vt 1 |, the Vt of the MIS type semiconductor device/SOI is
It is lower than Vt 1 of the MIS type semiconductor device 6, and the variation also increases.
本発明の目的は、上述した従来の問題点を解決
したSOI構造のMIS型半導体装置の製造方法を提
供することにある。 An object of the present invention is to provide a method for manufacturing an MIS type semiconductor device having an SOI structure, which solves the above-mentioned conventional problems.
本発明は絶縁体上に形成された半導体薄膜に
MISトランジスタを形成する方法において、前記
半導体薄膜表面にレジストを塗布し、前記レジス
トがMISトランジスタを作製する素子領域の上に
残るようにパターニングした後、前記レジストを
マスクにして前記半導体薄膜中に酸素をイオン注
入して前記半導体薄膜のうち素子領域以外の半導
体薄膜の下面側に酸化膜を形成し、前記レジスト
を除去して不活性ガス中でアニールし、その後、
前記半導体薄膜を前記酸化膜が露出するまで研磨
し、基板表面を平坦化して素子分離を行うことを
特徴とするMIS型半導体装置製造方法である。
The present invention applies to semiconductor thin films formed on insulators.
In the method for forming an MIS transistor, a resist is applied to the surface of the semiconductor thin film, the resist is patterned so as to remain on the element region where the MIS transistor is to be fabricated, and then oxygen is added to the semiconductor thin film using the resist as a mask. is ion-implanted to form an oxide film on the lower surface side of the semiconductor thin film other than the element region, the resist is removed and annealed in an inert gas, and then,
The MIS type semiconductor device manufacturing method is characterized in that the semiconductor thin film is polished until the oxide film is exposed, the substrate surface is flattened, and elements are isolated.
以下、本発明について実施例を用いて説明す
る。本実施例においては、半導体膜としてSi膜，
絶縁膜としてSiO2膜，MIS型半導体装置として
MOSFETを用いている。
The present invention will be explained below using examples. In this example, the semiconductor film is a Si film,
SiO 2 film as insulating film, as MIS type semiconductor device
It uses MOSFET.
第１図はSOI構造のMOSFETの製造工程を示
す模式的断面図である。SOI構造の基板は第１図
ａに示すようにSi基板１上に膜厚1μｍのSiO2膜
２、膜厚0.5μｍのSi膜８が順次形成されたものを
用いる。このSi膜８上にレジスト９をスピン塗布
する。次に第１図ｂに示すように、レジスト９を
MOSFETの素子領域上に残してパターニングす
る。その後、第１図ｃに示すように、レジスト９
をマスクにしてSi膜中にO+イオンを注入する。
注入条件は加速電圧300KeV，ドーズ量1.07×
1018cm-2である。その後、レジスト９を除去し、
アルゴンガス雰囲気中、1150℃でアニールする。
その結果、素子領域直下以外のSi膜８の底から
0.3μｍの領域がSiO2膜１０となる。次にポリシン
グによりSi膜８を薄膜化する。薄膜化を進めてゆ
き、SiO2膜が露出すると、SiO2のポリシング進
行速度がSiのそれに比べて非常に遅いので、
SiO2膜１０がポリシングのストツパーとなり、
それ以上ポリシングは進まなくなる。その結果、
第１図ｄに示すような基板表面が平坦であり、か
つSi膜８が素子分離されたSOI構造の基板が得ら
れる。 FIG. 1 is a schematic cross-sectional view showing the manufacturing process of a MOSFET having an SOI structure. As shown in FIG. 1A, the SOI structure substrate used is one in which a SiO 2 film 2 with a thickness of 1 μm and a Si film 8 with a thickness of 0.5 μm are sequentially formed on a Si substrate 1. A resist 9 is spin coated onto this Si film 8. Next, as shown in FIG. 1b, the resist 9 is
Pattern it by leaving it on the MOSFET element area. After that, as shown in FIG. 1c, the resist 9
O + ions are implanted into the Si film using a mask.
Implantation conditions are acceleration voltage 300KeV, dose 1.07×
10 18 cm -2 . After that, remove the resist 9,
Anneal at 1150℃ in an argon gas atmosphere.
As a result, from the bottom of the Si film 8 other than directly under the element area,
The 0.3 μm area becomes the SiO 2 film 10. Next, the Si film 8 is made thinner by polishing. When the SiO 2 film is exposed as the film is made thinner, the polishing speed of SiO 2 is much slower than that of Si.
The SiO 2 film 10 acts as a polishing stopper,
Policing will not proceed any further. the result,
A substrate having an SOI structure as shown in FIG. 1d is obtained, the substrate surface is flat and the Si film 8 is separated into elements.
この基板を用い作製したときのSOI型の
MOSFETの模式的断面図を第１図ｅ，ｆに示
す。ここで第１図ｅの断面図において、Ｆ−Ｆ線
の断面を第１図ｆに示す。図中、３はSi膜中のソ
ース・ドレイン拡散層、４はゲートSiO2膜、５
はゲート電極、６は第１のチヤネル領域、７は第
２のチヤネル領域である。 SOI type when fabricated using this substrate
A schematic cross-sectional view of the MOSFET is shown in Figures 1e and 1f. Here, in the sectional view of FIG. 1e, a cross section taken along line FF is shown in FIG. 1f. In the figure, 3 is the source/drain diffusion layer in the Si film, 4 is the gate SiO 2 film, and 5 is the source/drain diffusion layer in the Si film.
is a gate electrode, 6 is a first channel region, and 7 is a second channel region.
本発明のSOI型MOSFETも従来法と同様に、
Si膜８の上面の第１のチヤネル領域に形成される
第１のMOSFETとSi膜８の側壁の第２のチヤネ
ル領域に形成される第２のMOSFETが並列に結
合して構成されている。ただし、本発明の場合に
はSiO2膜１０が存在しているために第２の
MOSFETのゲートSiO2膜は第１のMOSFETの
ゲートSiO2膜よりも厚い。 The SOI MOSFET of the present invention also has the same characteristics as the conventional method.
A first MOSFET formed in a first channel region on the upper surface of the Si film 8 and a second MOSFET formed in a second channel region on the side wall of the Si film 8 are coupled in parallel. However, in the case of the present invention, since the SiO 2 film 10 is present, the second
The gate SiO 2 film of the MOSFET is thicker than the gate SiO 2 film of the first MOSFET.
ここでｎチヤネルMOSFETのVtはSi−SiO2界
面の界面準位が小さいとすると、
VtVFB＋2ΨB＋√4Ksε0qNAΨB／Ci
また
Ci＝Kiε0／ｄ
ここでVFBはフラツトバンド電圧，ΨBはSiのフ
エルミ準位，Ks，Kiはそれぞれシリコン，シリ
コン酸化膜の比誘電率，ε0は誘電率，ｑは電子の
電荷量，NAは単位体積あたりのアクセプタ不純
物の密度，Ciはゲート酸化膜の単位面積あたりの
キヤパシタンス，ｄはゲート酸化膜厚である。 Here , the Vt of the n - channel MOSFET is assuming that the interface state of the Si - SiO 2 interface is small. , Ψ B is the Fermi level of Si, Ks and Ki are the relative dielectric constants of silicon and silicon oxide, respectively, ε 0 is the dielectric constant, q is the amount of electron charge, N A is the density of acceptor impurity per unit volume, Ci is the capacitance per unit area of the gate oxide film, and d is the thickness of the gate oxide film.
ゲート酸化膜が厚くなると前述の式よりVtは
高くなる。本発明の場合、第２のMOSFETのゲ
ート酸化膜は第１のMOSFETのゲート酸化膜よ
り厚くなるので、第１、第２のMOSFETの閾値
電圧Vt1，Vt2の関係はVt1＜Vt2となる。また、
一般に第１のMOSFETのチヤネル幅は第２の
MOSFETのそれより大きい。それゆえ第１，第
２のMOSFETのソース・ドレイン間電流ID1，ID2
の関係は常にID1＞ID2となり、SOI構造の
MOSFETのソース・ドレイン間電流は第１の
MOSFETのソース・ドレイン間電流で近似でき
る。すなわち、SOI構造のMOSFETの静特性は
第１のMOSFETの静特性にほとんど等しくな
る。それゆえ、従来法で問題となつた第２の
MOSFETによるSOI構造のMOSFETのVtの低
下やばらつきは生じない。 As the gate oxide film becomes thicker, Vt increases according to the above equation. In the case of the present invention, the gate oxide film of the second MOSFET is thicker than the gate oxide film of the first MOSFET, so the relationship between the threshold voltages Vt 1 and Vt 2 of the first and second MOSFETs is Vt 1 <Vt 2 becomes. Also,
Generally, the channel width of the first MOSFET is the same as that of the second MOSFET.
It is larger than that of MOSFET. Therefore, the source-drain currents I D1 and I D2 of the first and second MOSFETs
The relationship is always I D1 > I D2 , and the SOI structure
The source-drain current of the MOSFET is the first
It can be approximated by the source-drain current of a MOSFET. That is, the static characteristics of the MOSFET having the SOI structure are almost equal to the static characteristics of the first MOSFET. Therefore, the second problem with the conventional method is
There is no drop or variation in Vt of MOSFETs with SOI structure due to MOSFETs.
以上実施例においては、半導体膜としてSi膜、
絶縁膜としてSiO2膜、MIS型半導体装置として
MOSFETを用いたが、他の半導体膜、絶縁膜、
MIS型半導体装置を用いても問題はない。 In the above embodiments, the semiconductor film is a Si film,
SiO 2 film as insulating film, as MIS type semiconductor device
Although MOSFET was used, other semiconductor films, insulating films,
There is no problem even if an MIS type semiconductor device is used.
以上のように本発明によれば、SOI型
MOSFETにおけるVtの低下やばらつきの増大ま
たリーク電流の増大等を抑制することができる。
As described above, according to the present invention, SOI type
It is possible to suppress a decrease in Vt, an increase in variation, an increase in leakage current, etc. in the MOSFET.
また、ポリシングにより薄膜のSOI型
MOSFETを作製することができる効果を有す
る。 In addition, by polishing, thin film SOI type
It has the effect of making it possible to create MOSFETs.
第１図ａ〜ｅは本発明によるSOI型MOSFET
の製造工程の実施例を工程順に示す模式的断面
図、ｆはｅのＦ−Ｆ線断面図、第２図ａは従来法
で素子分離を行つたSOI型MOSFETの模式的断
面図、ｂはａのＢ−Ｂ線断面図である。
１……Si基板、２，１０……SiO2膜、３……Si
膜中のソース・ドレイン拡散層、４……ゲート
SiO2膜、５……ゲート電極、６……第１のチヤ
ネル領域、７……第２のチヤネル領域、８……Si
膜、９……レジスト。
Figure 1 a to e are SOI type MOSFETs according to the present invention.
Fig. 2 is a schematic cross-sectional view showing an example of the manufacturing process in the order of steps, f is a cross-sectional view taken along the line F-F of e, Fig. 2 a is a schematic cross-sectional view of an SOI MOSFET in which element isolation is performed by the conventional method, and b is a schematic cross-sectional view of It is a sectional view taken along the line BB of FIG. 1...Si substrate, 2,10...SiO 2 film, 3...Si
Source/drain diffusion layer in the film, 4...gate
SiO 2 film, 5...gate electrode, 6...first channel region, 7...second channel region, 8...Si
Film, 9...Resist.
Claims (1)
ンジスタを形成する方法において、前記半導体薄
膜表面にレジストを塗布し、前記レジストがMIS
トランジスタを作製する素子領域の上に残るよう
にパターニングした後、前記レジストをマスクに
して前記半導体薄膜中に酸素をイオン注入して前
記半導体薄膜のうち素子領域以外の半導体薄膜の
下面側に酸化膜を形成し、前記レジストを除去し
て不活性ガス中でアニールし、その後、前記半導
体薄膜を前記酸化膜が露出するまで研磨し、基板
表面を平坦化して素子分離を行うことを特徴とす
るMIS型半導体装置製造方法。1 In a method for forming an MIS transistor on a semiconductor thin film formed on an insulator, a resist is applied to the surface of the semiconductor thin film, and the resist
After patterning so as to remain on the element region where a transistor is to be fabricated, oxygen ions are implanted into the semiconductor thin film using the resist as a mask to form an oxide film on the lower surface of the semiconductor thin film other than the element region. , the resist is removed and annealed in an inert gas, and the semiconductor thin film is then polished until the oxide film is exposed to flatten the substrate surface and perform element isolation. type semiconductor device manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7324787A JPS63237572A (en) | 1987-03-26 | 1987-03-26 | Manufacture of mis semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7324787A JPS63237572A (en) | 1987-03-26 | 1987-03-26 | Manufacture of mis semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63237572A JPS63237572A (en) | 1988-10-04 |
| JPH0569313B2 true JPH0569313B2 (en) | 1993-09-30 |
Family
ID=13512660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7324787A Granted JPS63237572A (en) | 1987-03-26 | 1987-03-26 | Manufacture of mis semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63237572A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2699359B2 (en) * | 1987-11-20 | 1998-01-19 | ソニー株式会社 | Semiconductor substrate manufacturing method |
-
1987
- 1987-03-26 JP JP7324787A patent/JPS63237572A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63237572A (en) | 1988-10-04 |
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