JPS6323661B2 - - Google Patents

Info

Publication number
JPS6323661B2
JPS6323661B2 JP542279A JP542279A JPS6323661B2 JP S6323661 B2 JPS6323661 B2 JP S6323661B2 JP 542279 A JP542279 A JP 542279A JP 542279 A JP542279 A JP 542279A JP S6323661 B2 JPS6323661 B2 JP S6323661B2
Authority
JP
Japan
Prior art keywords
groove
substrate
solder
region
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP542279A
Other languages
English (en)
Other versions
JPS5596666A (en
Inventor
Toshiaki Shinohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP542279A priority Critical patent/JPS5596666A/ja
Publication of JPS5596666A publication Critical patent/JPS5596666A/ja
Publication of JPS6323661B2 publication Critical patent/JPS6323661B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
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    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 この発明は、半導体装置用基板すなわち一般に
リードフレームと称される半導体装置組立部品の
ダイパツド部の製造方法に関するものである。
銀メツキを施したダイパツド部に半導体素子を
半田付けすると共に、上記ダイパツト部の上記半
導体素子に隣接した領域にワイヤボンデイングを
行う必要性のある半導体装置が多くある。
ところが、上記ダイパツド部の上記半田付けと
ワイヤボンデイングを行う面が平面であると、上
記半田付け時に溶融した半田がワイヤボンデイン
グ領域に流れ出し、ワイヤボンデイングができな
い場合がある。
そこで、この半田の流れ出しを防止するため
に、次のような方法が実施されていた。パンチン
グ成形によつてダイパツド部１とリード部２を有
するリードフレームを形成する時に、第１図に示
すように、上記ダイパツド部１の半導体素子半田
付け領域１１とワイヤボンデイング領域１２間に
コイニング溝３を形成した後、第２図に示すよう
に、これに銀メツキ４を一様な厚さに施してリー
ドフレームを完成させる。
その後、半田５によつて半導体素子６を固着し
た後、金線などの金属細線７をボンデイングす
る。
この従来の方法によるときは、銀メツキ４の表
面状態が平滑であれば、流れ出した半田は溝３上
に形成された銀メツキ４面の溝に貯まるので、ワ
イヤボンデイングに何ら支障を来たすことはな
い。
しかし、銀メツキ４の表面状態が悪く、小さな
凹凸があるいわゆるメツキヤケの状態になると、
銀メツキ４の表面を半田５がにじみ出し、第２図
に示すように、溝３上に形成された銀メツキ４面
の溝を越えてボンデイング領域１２に達してしま
うため、依然としてワイヤボンデイングができな
い場合があつた。もちろん、銀メツキ４の表面状
態を平滑にすればかかる問題は発生しないわけで
あるが、表面状態を精度よくコントロールしてメ
ツキすることは、実際上困難である。
この発明はこのような点に鑑みてなされたもの
で、半田濡れ性およびボンデイング性のよい金属
被膜を形成した後、この金属被膜面に表面が平滑
な溝を形成することにより、上記従来の欠点を解
消することができる半導体装置用基板の製造方法
を提供することを目的とする。
以下、図を参照してこの発明の一実施例につい
て説明する。
先ず、例えばパンチング成形によつて、基板を
構成するダイパツド部１とリード部２を有するリ
ードフレームを形成した後、第３図ａに示すよう
に、これに半田濡れ性およびワイヤボンデイング
性のよい金属被膜、例えば銀メツキ４を施し、次
いで、上記ダイパツド部１にコイニング加工を施
して、第３図ｂに示すように、半導体素子６を半
田付け領域１１とワイヤボンデイング領域１２間
の銀メツキ４面に、表面が平滑な溝８を形成す
る。このようにして、この発明による半導体装置
用基板が完成する。これを用いた半導体装置の組
立は、前述の従来方法と同一の方法により、その
組立完了状態を第４図に示す。図から明らかなよ
うに、溶融した半田５は溝８まで流れてくるが、
溝８の表面が平滑になつているので、半田５は溝
８からボンデイング領域１２へにじみ出ることは
なく、溝８内に貯まる。従つて、ワイヤボンデイ
ングに何ら支障を来たすことはない。
以上述べたように、この発明の製法によるもの
によれば、金属被膜の表面状態に何ら影響される
ことなく、ワイヤボンデイング領域への半田の付
着を確実に防止することができ、半導体装置の生
産性および信頼性を著しく向上することができ
る。
【図面の簡単な説明】
第１図および第２図は従来方法を示す断面図、
第３図はこの発明の一実施例を示す断面図、第４
図はこの発明による基板を用いた半導体装置の組
立状態を示す断面図である。 図において、１は基板、４は金属被膜、５は半
田、６は半導体素子、７は金属細線、８は溝、１
１は半田付け領域、１２はワイヤボンデイング領
域である。なお、図中同一符号は同一または相当
部分を示す。

Claims (1)

  1. 【特許請求の範囲】 １ 半導体素子を半田付けする領域と金属細線を
    ボンデイングする領域を同一面に有する基板に半
    田濡れ性およびボンデイング性のよい金属被膜を
    形成した後、上記半田付け領域とボンデイング領
    域間の上記金属被膜面に表面が平滑な溝を形成す
    ることを特徴とする半導体装置用基板の製造方
    法。 ２ 溝はコイニング加工によつて形成されること
    を特徴とする特許請求の範囲第１項記載の半導体
    装置用基板の製造方法。
JP542279A 1979-01-18 1979-01-18 Method of fabricating semiconductor device substrate Granted JPS5596666A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP542279A JPS5596666A (en) 1979-01-18 1979-01-18 Method of fabricating semiconductor device substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP542279A JPS5596666A (en) 1979-01-18 1979-01-18 Method of fabricating semiconductor device substrate

Publications (2)

Publication Number Publication Date
JPS5596666A JPS5596666A (en) 1980-07-23
JPS6323661B2 true JPS6323661B2 (ja) 1988-05-17

Family

ID=11610718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP542279A Granted JPS5596666A (en) 1979-01-18 1979-01-18 Method of fabricating semiconductor device substrate

Country Status (1)

Country Link
JP (1) JPS5596666A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01128166U (ja) * 1988-02-26 1989-09-01
JP2004071898A (ja) * 2002-08-07 2004-03-04 Sanyo Electric Co Ltd 回路装置およびその製造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62178543U (ja) * 1986-04-30 1987-11-12
JPS62178544U (ja) * 1986-04-30 1987-11-12
TWI573235B (zh) 2009-09-11 2017-03-01 羅姆股份有限公司 半導體裝置及其製造方法
WO2015079834A1 (ja) * 2013-11-29 2015-06-04 シャープ株式会社 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01128166U (ja) * 1988-02-26 1989-09-01
JP2004071898A (ja) * 2002-08-07 2004-03-04 Sanyo Electric Co Ltd 回路装置およびその製造方法

Also Published As

Publication number Publication date
JPS5596666A (en) 1980-07-23

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