JPS6322746U - - Google Patents
Info
- Publication number
- JPS6322746U JPS6322746U JP11733086U JP11733086U JPS6322746U JP S6322746 U JPS6322746 U JP S6322746U JP 11733086 U JP11733086 U JP 11733086U JP 11733086 U JP11733086 U JP 11733086U JP S6322746 U JPS6322746 U JP S6322746U
- Authority
- JP
- Japan
- Prior art keywords
- package
- mark
- covered
- storing
- insulating container
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000011247 coating layer Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図は本考案の半導体素子収納用パツケージ
の絶縁基体の平面図、第２図は本考案の半導体素
子収納用パツケージの断面図、第３図は本考案の
半導体素子収納用パツケージに設けられる標識の
部分を説明するための部分拡大断面図、第４図は
従来の半導体素子収納用パツケージの絶縁基体の
平面図、第５図は同じく半導体素子収納用パツケ
ージの断面図である。
１：絶縁基体、２：蓋体、３：絶縁容器、５：
金属層、７：外部リード端子、Ｂ：標識、Ｃ：透
光性被覆層。
FIG. 1 is a plan view of the insulating base of the package for housing semiconductor devices of the present invention, FIG. 2 is a sectional view of the package for housing semiconductor devices of the present invention, and FIG. 3 is a plan view of the insulating base of the package for housing semiconductor devices of the present invention. FIG. 4 is a plan view of an insulating base of a conventional package for housing semiconductor elements, and FIG. 5 is a cross-sectional view of the package for housing semiconductor elements. 1: Insulating base, 2: Lid, 3: Insulating container, 5:
Metal layer, 7: external lead terminal, B: label, C: translucent coating layer.
Claims (1)
外部リード端子が取着されて成る半導体素子収納
用パツケージにおいて、前記絶縁容器の外表面に
標識を設けるとともに該標識を透光性被覆層で覆
つたことを特徴とする半導体素子収納用パツケー
ジ。 In a package for storing a semiconductor element, which has a plurality of external lead terminals attached to an insulating container consisting of an insulating base and a lid, a mark is provided on the outer surface of the insulating container, and the mark is covered with a transparent coating layer. A package for storing semiconductor elements characterized by being covered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11733086U JPS6322746U (en) | 1986-07-29 | 1986-07-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11733086U JPS6322746U (en) | 1986-07-29 | 1986-07-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6322746U true JPS6322746U (en) | 1988-02-15 |
Family
ID=31002740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11733086U Pending JPS6322746U (en) | 1986-07-29 | 1986-07-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6322746U (en) |
-
1986
- 1986-07-29 JP JP11733086U patent/JPS6322746U/ja active Pending