JPS61177459U - - Google Patents
Info
- Publication number
- JPS61177459U JPS61177459U JP6154485U JP6154485U JPS61177459U JP S61177459 U JPS61177459 U JP S61177459U JP 6154485 U JP6154485 U JP 6154485U JP 6154485 U JP6154485 U JP 6154485U JP S61177459 U JPS61177459 U JP S61177459U
- Authority
- JP
- Japan
- Prior art keywords
- insulating base
- lead terminal
- external lead
- terminal extending
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の半導体パツケージの一実施例
を示す断面図、第２図は縦来の半導体パツケージ
の断面図、第３図は本出願人が先に提案した半導
体パツケージの断面図である。
１：絶縁基体、２：蓋体、３：外部リード端子
、７：間隙、１ａ：絶縁基体底面部凹部、９：絶
縁容器。
FIG. 1 is a sectional view showing an embodiment of the semiconductor package of the present invention, FIG. 2 is a sectional view of a conventional semiconductor package, and FIG. 3 is a sectional view of a semiconductor package previously proposed by the applicant. . 1: Insulating base, 2: Lid, 3: External lead terminal, 7: Gap, 1a: Insulating base bottom recess, 9: Insulating container.
Claims (1)
体の上面部から側面部を介して底面部に達するま
で延長され、かつ該側面部との間に間隙を形成す
るように設けられた外部リード端子とから成る半
導体パツケージにおいて、前記絶縁基体の底面部
に凹部を形成し、該凹部内に絶縁基体底面部に延
長された外部リード端子の一部を嵌入させたこと
を特徴とする半導体パツケージ。 An insulating container consisting of an insulating base and a lid, and an external lead terminal extending from the top of the insulating base through the side to the bottom, and provided to form a gap between the side and the side. A semiconductor package comprising: a recess formed in the bottom surface of the insulating base, and a part of an external lead terminal extending to the bottom surface of the insulating base is fitted into the recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6154485U JPS61177459U (en) | 1985-04-23 | 1985-04-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6154485U JPS61177459U (en) | 1985-04-23 | 1985-04-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61177459U true JPS61177459U (en) | 1986-11-05 |
Family
ID=30589919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6154485U Pending JPS61177459U (en) | 1985-04-23 | 1985-04-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61177459U (en) |
-
1985
- 1985-04-23 JP JP6154485U patent/JPS61177459U/ja active Pending