JPS6320471U - - Google Patents

Info

Publication number
JPS6320471U
JPS6320471U JP11273586U JP11273586U JPS6320471U JP S6320471 U JPS6320471 U JP S6320471U JP 11273586 U JP11273586 U JP 11273586U JP 11273586 U JP11273586 U JP 11273586U JP S6320471 U JPS6320471 U JP S6320471U
Authority
JP
Japan
Prior art keywords
circuit component
orthogonal
soldering
mount type
side surfaces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11273586U
Other languages
Japanese (ja)
Other versions
JPH0427183Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986112735U priority Critical patent/JPH0427183Y2/ja
Publication of JPS6320471U publication Critical patent/JPS6320471U/ja
Application granted granted Critical
Publication of JPH0427183Y2 publication Critical patent/JPH0427183Y2/ja
Expired legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本考案の回路部品の取付基板に形成
されたランドパターンの斜視図、第２図は本考案
の他の実施例を示すランドパターンの斜視図、第
３図は余剰半田の分布図、第４図ａ，ｂ，ｃは面
実装部品の具体例を示す斜視図、第５図は面実装
形のランドパターン図、第６図ａ，ｂは半田付の
説明図である。 図中、Ｒはランド、Ｒｃは隣接するランド、Ｐ
は回路部品のパツケージ、Ｆはリードフレーム（
接続端子）を示す。 Fig. 1 is a perspective view of a land pattern formed on a circuit component mounting board of the present invention, Fig. 2 is a perspective view of a land pattern showing another embodiment of the present invention, and Fig. 3 is a distribution of surplus solder. 4A, 4B, and 4C are perspective views showing specific examples of surface mount components, FIG. 5 is a land pattern diagram of the surface mount type, and FIGS. 6A and 6B are explanatory views of soldering. In the figure, R is a land, R c is an adjacent land, and P
is the circuit component package, F is the lead frame (
connection terminal).

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 少なくとも直交する２つの側面に対して複数個
の接続端子を有する面実装形の回路部品をプリン
ト基板に半田付ける際に、前記接続用端子に対応
するプリント基板のランドの中で、前記直交する
２つの側面の隣接ランドの相対する角部を斜めに
カツトしたことを特徴とする回路部品の取付基板
。 When soldering a surface-mount type circuit component having a plurality of connection terminals to at least two orthogonal side surfaces to a printed circuit board, the two orthogonal A circuit component mounting board characterized in that opposing corners of adjacent lands on two sides are cut diagonally.
JP1986112735U 1986-07-24 1986-07-24 Expired JPH0427183Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986112735U JPH0427183Y2 (en) 1986-07-24 1986-07-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986112735U JPH0427183Y2 (en) 1986-07-24 1986-07-24

Publications (2)

Publication Number Publication Date
JPS6320471U true JPS6320471U (en) 1988-02-10
JPH0427183Y2 JPH0427183Y2 (en) 1992-06-30

Family

ID=30993884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986112735U Expired JPH0427183Y2 (en) 1986-07-24 1986-07-24

Country Status (1)

Country Link
JP (1) JPH0427183Y2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109535A (en) * 2008-10-29 2010-05-13 Nippon Dempa Kogyo Co Ltd Method of mounting surface mounting crystal oscillator onto set substrate
JP2015159253A (en) * 2014-02-25 2015-09-03 ファナック株式会社 printed circuit board
JP2016213308A (en) * 2015-05-08 2016-12-15 キヤノン株式会社 Printed circuit board and printed wiring board

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3777221A (en) * 1972-12-18 1973-12-04 Ibm Multi-layer circuit package
JPS55164867U (en) * 1979-05-15 1980-11-27
JPS59145592A (en) * 1984-01-17 1984-08-21 株式会社ケンウッド Method of mounting electronic part on printed circuit board
JPS60182750A (en) * 1984-02-29 1985-09-18 Fujitsu Ltd Mounting substrate
JPS6120078U (en) * 1984-07-11 1986-02-05 日本ビクター株式会社 printed wiring board

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130286A (en) * 1981-02-06 1982-08-12 Fujitsu Ltd Static semiconductor memory

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3777221A (en) * 1972-12-18 1973-12-04 Ibm Multi-layer circuit package
JPS55164867U (en) * 1979-05-15 1980-11-27
JPS59145592A (en) * 1984-01-17 1984-08-21 株式会社ケンウッド Method of mounting electronic part on printed circuit board
JPS60182750A (en) * 1984-02-29 1985-09-18 Fujitsu Ltd Mounting substrate
JPS6120078U (en) * 1984-07-11 1986-02-05 日本ビクター株式会社 printed wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109535A (en) * 2008-10-29 2010-05-13 Nippon Dempa Kogyo Co Ltd Method of mounting surface mounting crystal oscillator onto set substrate
JP2015159253A (en) * 2014-02-25 2015-09-03 ファナック株式会社 printed circuit board
US9872388B2 (en) 2014-02-25 2018-01-16 Fanuc Corporation Printed wiring board
JP2016213308A (en) * 2015-05-08 2016-12-15 キヤノン株式会社 Printed circuit board and printed wiring board

Also Published As

Publication number Publication date
JPH0427183Y2 (en) 1992-06-30

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