JPS6320386B2 - - Google Patents
Info
- Publication number
- JPS6320386B2 JPS6320386B2 JP56122003A JP12200381A JPS6320386B2 JP S6320386 B2 JPS6320386 B2 JP S6320386B2 JP 56122003 A JP56122003 A JP 56122003A JP 12200381 A JP12200381 A JP 12200381A JP S6320386 B2 JPS6320386 B2 JP S6320386B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- nitride film
- film
- manufacturing
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000001947 vapour-phase growth Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000007740 vapor deposition Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 230000007547 defect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
本発明はMNOS不揮発メモリの製造方法に関
する。従来MNOS素子の製造に関しては、シリ
コン酸化膜を50〜100Å形成し、その上にシリコ
ン窒化膜を500Å程度形成し、このシリコン酸化
膜とシリコン窒化膜の界面捕獲準位に、電荷をト
ラツプし、これによりしきい値電圧をシフトさせ
データを記録する不揮発メモリーとしている。と
ころが、実際のシリコン窒化膜には、多くの準位
が、膜内に広く分布するため、シリコン酸化膜を
トンネル効果で通過した、電荷（主に電子）は、
シリコン酸化膜−シリコン窒化膜界面だけでなく
このシリコン窒化膜内の準位に多くトラツプされ
る。このことは、消去時、つまり、、ゲート電極
とシリコン基板層間に、電圧を印加しても、ゲー
ト電極近傍にトラツプされている電子は、基板へ
逃げにくくなり、結果的に、消去特性の悪い不揮
発メモリーとなり、問題となつている。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing MNOS nonvolatile memory. Conventionally, in the production of MNOS devices, a silicon oxide film is formed with a thickness of 50 to 100 Å, a silicon nitride film is formed with a thickness of about 500 Å on top of the silicon oxide film, and charges are trapped in the interface trap level between the silicon oxide film and the silicon nitride film. This creates a nonvolatile memory that records data by shifting the threshold voltage. However, in an actual silicon nitride film, many levels are widely distributed within the film, so the charges (mainly electrons) that pass through the silicon oxide film due to the tunnel effect are
Many traps occur not only at the silicon oxide film-silicon nitride film interface but also at levels within the silicon nitride film. This means that during erasing, even if a voltage is applied between the gate electrode and the silicon substrate layer, the electrons trapped near the gate electrode will have difficulty escaping to the substrate, resulting in poor erasing characteristics. It has become a non-volatile memory and has become a problem.
従来これらの欠点を、除く方法として、シリコ
ン酸化膜一シリコン窒化膜界面に、金属層とか、
金属酸化物層を非常に薄くコーテイングすること
が試みられているが、可動イオン等の混入がさけ
られず、ゲート電極へのリークが生じ易くなり、
信頼性に欠けるものであつた。 Conventionally, as a method to eliminate these drawbacks, a metal layer or
Attempts have been made to coat the metal oxide layer very thinly, but the incorporation of mobile ions is unavoidable and leakage to the gate electrode is likely to occur.
It lacked reliability.
そこで、本発明は、トンネル効果により、侵入
してきた電荷を、効率よくシリコン酸化膜一シリ
コン窒化膜界面に、捕獲し、しかも、従来の方法
にみられる。ゲート電極へのリークなどのない
MNOS不揮発メモリの製造方法を提供するもの
である。 Therefore, the present invention efficiently traps the invading charges at the silicon oxide film-silicon nitride film interface by the tunnel effect, which is different from the conventional method. No leakage to gate electrode
A method for manufacturing MNOS nonvolatile memory is provided.
第１図に、本発明の製造方法の一例としてＮチ
ヤンネルシリコンゲートMNOSの工程断面図を
示す。Ｐ基板１０１に、Ｎ型不純物としてリンを
ドープしてソース、ドレイン１０２を形成する。
次に、シリコン酸化膜を形成後ゲート部のみエツ
チング除去し、もう一度ゲート酸化をして50Åな
いし100Åのシリコン酸化膜１０３を形成する。
（第１図ａ）次に、シリコン窒化膜１０４を100〜
300Å程度形成する。このシリコン窒化膜１０４
は、準位が膜内に多く存在させるため、割と欠陥
の多い形成方法をもつて形成する。本実施例では
気相成長法で、通常の形成方法より、低温でかつ
反応ガス圧を高く形成した。（第１図ｂ）次に、
欠陥が逆に少ないシリコン窒化膜１０５を200Å
〜400Å形成する。本発明では、このシリコン窒
化膜１０５を、プラズマにより形成し、つまりプ
ラズマのアシストを利用したプラズマ気相成長法
によりシリコン窒化膜１０４よりも準位が少ない
状態、すなわち欠陥の少ない状態で形成し、さら
に欠陥を押さえるため形成後、熱処理として水素
シンタを行なつた。さらに、ゲート電極として多
結晶シリコン１０６を形成した。（第１図ｃ）こ
のように、本発明では、形成方法の異なるシリコ
ン窒化膜を二層形成し、しかも、下層のシリコン
窒化膜に、多くの準位をもたせ、上層のシリコン
窒化膜は、逆に準位の少ない緻密な膜を形成する
ことにより、従来みられた、消去特性の悪さや低
信頼性を、簡単な工程の追加により、完全に取り
除けるというすぐれた方法である。 FIG. 1 shows a process cross-sectional view of an N-channel silicon gate MNOS as an example of the manufacturing method of the present invention. A source and a drain 102 are formed by doping a P substrate 101 with phosphorus as an N-type impurity.
Next, after forming a silicon oxide film, only the gate portion is removed by etching, and gate oxidation is performed again to form a silicon oxide film 103 with a thickness of 50 Å to 100 Å.
(Figure 1a) Next, the silicon nitride film 104 is
Forms about 300Å. This silicon nitride film 104
Because many levels exist in the film, they are formed using a method that involves relatively many defects. In this example, the vapor phase growth method was used to form the film at a lower temperature and at a higher reaction gas pressure than in a normal formation method. (Figure 1b) Next,
On the contrary, the silicon nitride film 105 with fewer defects is 200 Å thick.
Forms ~400 Å. In the present invention, this silicon nitride film 105 is formed by plasma, that is, by plasma vapor phase epitaxy using plasma assistance, in a state with fewer levels than the silicon nitride film 104, that is, in a state with fewer defects, Furthermore, in order to suppress defects, hydrogen sintering was performed as a heat treatment after formation. Furthermore, polycrystalline silicon 106 was formed as a gate electrode. (Fig. 1c) In this way, in the present invention, two layers of silicon nitride films are formed using different formation methods, and the lower silicon nitride film has many levels, and the upper silicon nitride film has On the contrary, by forming a dense film with few levels, this is an excellent method that completely eliminates the conventional problems of poor erasing characteristics and low reliability with the addition of a simple process.
第１図が、本発明の製造方法の実施例である。 FIG. 1 shows an embodiment of the manufacturing method of the present invention.
Claims (1)
膜との二層のシリコン窒化膜を有するMNOS素
子をその構成要素とする半導体装置の製造方法に
おいて、前記第一層シリコン窒化膜を気相成長法
により形成する工程、前記第一層シリコン窒化膜
上にプラズマ気相成長法により前記第二層シリコ
ン窒化膜を形成する工程、前記第二層シリコン窒
化膜を形成する工程の後に熱処理をする工程を有
することを特徴とする半導体装置の製造方法。1. In a method for manufacturing a semiconductor device whose component is an MNOS element having two silicon nitride films, a first silicon nitride film and a second silicon nitride film, the first silicon nitride film is grown by vapor phase growth. a step of forming the second layer silicon nitride film on the first layer silicon nitride film by a plasma vapor deposition method; a step of performing heat treatment after the step of forming the second layer silicon nitride film. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12200381A JPS5823482A (en) | 1981-08-04 | 1981-08-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12200381A JPS5823482A (en) | 1981-08-04 | 1981-08-04 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5823482A JPS5823482A (en) | 1983-02-12 |
| JPS6320386B2 true JPS6320386B2 (en) | 1988-04-27 |
Family
ID=14825148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12200381A Granted JPS5823482A (en) | 1981-08-04 | 1981-08-04 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5823482A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2506726B2 (en) * | 1987-02-23 | 1996-06-12 | 松下電子工業株式会社 | Method of manufacturing nonvolatile memory device |
| JP2718931B2 (en) * | 1987-09-29 | 1998-02-25 | 松下電子工業株式会社 | Method for manufacturing semiconductor memory device |
| US5194701A (en) * | 1991-09-11 | 1993-03-16 | N.P.L. Ltd. | Speaker structure |
| JP2004095889A (en) | 2002-08-30 | 2004-03-25 | Fasl Japan Ltd | Semiconductor storage device and its manufacturing method |
| JP2009182211A (en) * | 2008-01-31 | 2009-08-13 | Toshiba Corp | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4913118A (en) * | 1972-06-06 | 1974-02-05 |
-
1981
- 1981-08-04 JP JP12200381A patent/JPS5823482A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4913118A (en) * | 1972-06-06 | 1974-02-05 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5823482A (en) | 1983-02-12 |
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