KR0172272B1 - Method of manufacturing floating gate at semiconductor - Google Patents
Method of manufacturing floating gate at semiconductor Download PDFInfo
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- KR0172272B1 KR0172272B1 KR1019950017273A KR19950017273A KR0172272B1 KR 0172272 B1 KR0172272 B1 KR 0172272B1 KR 1019950017273 A KR1019950017273 A KR 1019950017273A KR 19950017273 A KR19950017273 A KR 19950017273A KR 0172272 B1 KR0172272 B1 KR 0172272B1
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- gate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 63
- 229920005591 polysilicon Polymers 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 6
- 239000011261 inert gas Substances 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 claims 6
- 239000007790 solid phase Substances 0.000 claims 3
- 239000010409 thin film Substances 0.000 claims 2
- 235000014653 Carica parviflora Nutrition 0.000 claims 1
- 241000243321 Cnidaria Species 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000012071 phase Substances 0.000 claims 1
- 239000013078 crystal Substances 0.000 abstract description 43
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 7
- 239000011574 phosphorus Substances 0.000 abstract description 7
- 230000004888 barrier function Effects 0.000 abstract description 3
- 238000010893 electron trap Methods 0.000 abstract description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 2
- 230000000593 degrading effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체 소자의 플로팅게이트 형성방법에 관하여 개시된다.The present invention relates to a method of forming a floating gate of a semiconductor device.
본 발명은 플로팅게이트를 다결정실리콘으로 형성할 때 다결정실리콘을 이중으로 형성하여, 터널 게이트 산화막(Tunnel gate oxide)과 접촉되는 게이트 폴리 실리콘의 결정입자 크기를 크게하고, 결정 홈(Grooving)이 없도록 형성하므로써, 결정입자를 크게하고, 결정계면에서의 게이트 산화벽이 발생되지 않고, 게이트 산화막과 다결정실리콘의 결정입자 사이에서 게이트산화벽이 발생되지 않고, 게이트 산화막과 다결정실리콘의 결정입자 사이에서 발생되는 게이트산화벽의 크기를 미세화 시키면서 이를 균일하게 분산시키며, 국부적으로 열화된 터널 게이트 산화막의 인이 도포된 산화막쪽에 일렉트론 트랩(electron trap)이 감소되고, 높은 장벽(barrier height)이 낮아져서 전류 증가에 의한 순간적인 소거(erase)속도가 빠른 지역을 없애 주므로써, 소거(erase)속도가 순간적으로 빠른지역이 없어지게 되어 과잉소거의 문제점이 해결되고, 소자의 신뢰성을 향상시킬 수 있도록 한 반도체 소자의 플로팅게이트 형성방법에 관한 것이다.According to the present invention, when the floating gate is formed of polycrystalline silicon, polycrystalline silicon is formed in double, thereby increasing the crystal grain size of the gate polysilicon in contact with the tunnel gate oxide and forming no crystal grooves. As a result, the crystal grains are enlarged, no gate oxide walls are generated at the crystal interface, no gate oxide walls are generated between the gate oxide film and the crystal grains of the polycrystalline silicon, and the gate oxide film and the crystal grains of the polycrystalline silicon are not generated. By minimizing the size of the gate oxide wall and distributing it uniformly, the electron trap is reduced on the phosphorus-coated oxide film of the locally deteriorated tunnel gate oxide film, and the high barrier height is lowered to increase the current. By eliminating the area where the instantaneous erase rate is fast, the erase rate is increased The present invention relates to a method of forming a floating gate of a semiconductor device in which a fast area disappears instantaneously, thereby solving the problem of over-erasing and improving the reliability of the device.
Description
제1a 및 1b도는 종래의 반도체 소자의 플로팅게이트 형성방법을 설명하기 위해 도시한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a method of forming a floating gate of a conventional semiconductor device.
제2a 내지 2d도는 본 발명에 따른 반도체 소자의 플로팅게이트 형성방법을 설명하기 위해 도시한 소자의 단면도.2A through 2D are cross-sectional views of a device for explaining a method of forming a floating gate of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘 기판 12 : 게이트 산화막11 silicon substrate 12 gate oxide film
13 : 제1게이트 폴리실리콘 14,14a : 결정입자13: first gate polysilicon 14,14a: crystal grain
14,15a : 결정계면 16 : 제2게이트 폴리실리콘14,15a: Crystalline interface 16: Second gate polysilicon
본 발명은 반도체 소자의 플로팅게이트 형성방법에 관한 것으로, 특히 플로팅게이트를 다결정실리콘으로 형성할 때 다결정실리콘을 이중으로 형성하여, 터널 게이트 산화막(Tunnel gate oxide)과 접촉되는 게이트 폴리실리콘의 결정입자(grain) 크기를 크게 만들고, 결정계면의 홈(Grooving)이 없도록 형성한 반도체 소자의 플로팅게이트 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a floating gate of a semiconductor device. In particular, when the floating gate is formed of polycrystalline silicon, polycrystalline silicon is formed in double, and crystal grains of the gate polysilicon contacting the tunnel gate oxide (Tunnel gate oxide) The present invention relates to a method of forming a floating gate of a semiconductor device having a large grain size and free of grooves in a crystal interface.
일반적으로 반도체 소자의 제조공정에 있어서, 플래쉬 메모리소자의 폴리 실리콘의 결정입자 크기는 소거(erase)특성에 많은 영향을 주게되는 문제점이 제기되고 있다. 즉, 소자 동작에 있어서의 과잉소거가 발생되는데, 이는 소거영역이라고 하는 소오스(source) 및 플로팅게이트와의 오버랩(overlap)지역에서 플로팅게이트의 폴리실리콘의 결정입자 크기와 밀접한 관계가 있다.In general, in the manufacturing process of the semiconductor device, the problem that the crystal grain size of the polysilicon of the flash memory device has a large influence on the erase (erase) has been raised. That is, excessive erasure occurs in the device operation, which is closely related to the crystal grain size of the polysilicon of the floating gate in the overlap region of the source and the floating gate, which is called an erasure region.
제1a도는 실리콘기판(1)상에 게이트 산화막(2)을 형성하고, 게이트 산화막(2)상에 게이트 폴리실리콘(4)을 증착한 후, POCl3 이온을 도핑시켜서 플로팅게이트를 다결정실리콘으로 형성한 상태의 단면도이다. 이때, 상기 게이트 폴리실리콘(4)의 POCl3 도핑공정시 도핑농도에 따라 상기 게이트 폴리실리콘(4)의 결정입자(4A)크기는 차이가 있다. 또한 결정입자(4A)와 결정입자 하부이 게이트 산화막(2)이 리지 업(ridge up)되어 게이트 산화벽(3)이 형성되게 된다.FIG. 1A shows that the gate oxide film 2 is formed on the silicon substrate 1, the gate polysilicon 4 is deposited on the gate oxide film 2, and then the floating gate is formed of polycrystalline silicon by doping POCl 3 ions. It is a cross section of the condition. At this time, the size of the crystal grains 4A of the gate polysilicon 4 is different depending on the doping concentration during the POCl 3 doping process of the gate polysilicon 4. In addition, the gate oxide film 2 is ridged up between the crystal grains 4A and the lower portion of the crystal grains to form the gate oxide wall 3.
제1b도는 상기 도핑공정시 게이트 산화벽(3) 내부로 상기 게이트 폴리실리콘(4)의 결정입자(4A)와, 결정입자 사이의 결정계면(5)을 따라서 인(phoshphorus; 3A)이 하부의 게이트 산화막(3A)쪽으로 확산되어 인(3A)이 파일 업(file up)된 상태의 단면도이다. 이때, 인(3A)의 농도분포는 게이트 산화벽(3) 상층부 쪽으로 이동할수록 높아진다. 또한 상기 게이트 산하벽(3)이 클수록 게이트 산화막(2) 내부에 고농도의 인이 축절될 확률이 커지게 된다. 즉, 플로팅게이트의 도핑농도는 소자의 속도와 관련된 비저항 특성 및 후속공정에서 유전성 폴리 특성을 고려하여 적절한 저항을 가지는 플로팅게이트 폴리실리콘(4)을 형성시킨다. 결국 상기 게이트 산화벽이 커질수록 게이트 산화막 내부에 인이 넓게 확산되어 도포된 산화층은 결정계면을 중심으로 국부적으로 넓게 형성되어 이부분의 하부지역(2B)은 다른지역(2A)에 비해서 두께가 얇아지게 된다. 이와같은 상태에서 바이어스를 걸어줄 때 터널링 게이트 산화막은 정상적으로 두께에 비해서 상대적으로 얇은 산화막이 남게 된다.FIG. 1B shows that the phosphor particles 3A are disposed along the crystal interface 5 between the crystal grains 4A of the gate polysilicon 4 and the crystal grains in the gate oxide wall 3 during the doping process. It is sectional drawing of the state in which phosphorus 3A was piled up filed toward the gate oxide film 3A. At this time, the concentration distribution of phosphorus 3A becomes higher as it moves toward the upper portion of the gate oxide wall 3. In addition, the larger the gate underlayer 3, the greater the probability that a high concentration of phosphorus is condensed inside the gate oxide film 2. That is, the doping concentration of the floating gate forms the floating gate polysilicon 4 having appropriate resistance in consideration of the resistivity characteristic related to the speed of the device and the dielectric poly characteristic in a subsequent process. As a result, as the gate oxide wall grows larger, phosphorus diffuses widely in the gate oxide layer, and the oxide layer applied is locally formed around the crystal interface, so that the lower region 2B of this portion is thinner than other regions 2A. You lose. In this state, when the bias is applied, the tunneling gate oxide film normally has a relatively thin oxide film compared to the thickness.
따라서, 일렉트론 트랩(Electron trap)이 형성되어 전위장벽이 정상적인 부분에 비해 국부적으로 낮아져 순간적으로 과전류가 흐르게 되고, 이로 인해 과잉소거가 되므로 소자의 신뢰성이 저하되는 단점이 있다.Therefore, an electron trap is formed, so that the potential barrier is locally lower than the normal part, so that overcurrent flows instantaneously, and thus, excessive over current flows, thereby degrading reliability of the device.
따라서, 본 발명은 플로팅게이트를 다결정실리콘으로 형성할 때 다결정실리콘을 이중으로 형성하여, 터널 게이트 산화막(Tunnel gate oxide)과 접촉되는 게이트 폴리실리콘의 결정입자 크기를 크게 만들고, 결정계면의 홈이 없도록 형성하므로써, 상기한 단점을 해소할 수 있는 반도체 메모리 소자의 플로팅게이트 형성방법을 제공하는 데 그 목적이 있다.Therefore, in the present invention, when the floating gate is formed of polycrystalline silicon, the polycrystalline silicon is formed in double, thereby increasing the crystal grain size of the gate polysilicon in contact with the tunnel gate oxide and preventing grooves in the crystal interface. It is an object of the present invention to provide a method for forming a floating gate of a semiconductor memory device which can solve the above-described disadvantages.
상술한 목적을 달성하기 위한 본 발명은 실리콘기판으 열산화시켜 게이트산화막을 형성하는 단계와, 상기 게이트 산화막상부에 제1게이트 폴리실리콘을 형성하는 단계와, 상기 제1게이트 폴리실리콘을 고상성장시켜 제1다결정실리콘막을 형성하는 단계와,상기 제1게이트 폴리실리콘 상부에 제2게이트 폴리실리콘을 형성하는 단계와, 상기 제2게이트 폴리실리콘을 2차로 고상성장시켜 다결정실리콘막을 형성하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is to thermally oxidize a silicon substrate to form a gate oxide film, the step of forming a first gate polysilicon on the gate oxide film, and the solid state growth of the first gate polysilicon Forming a first polycrystalline silicon film, forming a second gate polysilicon on the first gate polysilicon, and forming a polycrystalline silicon film by secondly solidifying the second gate polysilicon. It features.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2a 내지 2d도는 본 발명에 따른 반도체 소자의 플로팅게이트 형성방법을 설명하기 위해 도시한 소자의 단면도이다.2A through 2D are cross-sectional views of a device for explaining a method of forming a floating gate of a semiconductor device according to the present invention.
제2a도는 실리콘기판(11)상에 소오스영역(10)을 형성하고, 상기 실리콘기판(11)을 열산화시켜 게이트 산화막(12)을 형성한 후, 상기 게이트 산화막(12)상부에 제1게이트 폴리실리콘(13)을 형성한 상태의 단면도이다. 상기 제1게이트 폴리실리콘(13)의 증착 조건은 LPCVD 방법을 이용하여 인-시튜 도프드 실리콘(in-냐셔 duped silicon)을 이용하고, 두께는 예정된 플로팅게이트의 전체 두께의 10 내지 25%의 두께로 증착시킨다. 즉 폴리실리콘의 결정입자 크기는 두께의 의존성을 가지는 특성을 이용하는 것으로, 이때 상기 제1게이트 폴리실리콘(13)의 증착 조건은 비정질 실리콘막이 형성될 수 있는 조건이면 된다. 상기 증착된 제1게이트 폴리실리콘(13)을 600 내지 700℃ 온도범위에서 1시간이상 불활성 기체분위기에서 형성하면 상기 비정질 실리콘막은 고상성장되어 결정계면(15)에서의 게이트 산화벽(3)이 다결정실리콘막으로 형성되어 제1게이트 폴리실리콘(13)을 형성한 상태를 나타낸다. 이와같은 공정에 의해 결정계면(15)에서의 게리트 산화벽(3)이 작은 제1게이트 폴리실리콘(13)은 결정입자(14)와 결정입자 사이의 결정계면(15)에 게이트 산화벽(3)이 존재하지 않으면서 크기가 큰 결정입자(14)와 평탄한 실리콘막이 형성되어, 게이트 산화벽(3)의 크기를 미세화시키면서, 이를 균일하게 분산시키므로 국부적으로 넓은층의 인(3A)이 도포된 층은 형성되지 않게 된다.2A illustrates a source region 10 formed on the silicon substrate 11, a thermal oxidation of the silicon substrate 11 to form a gate oxide film 12, and a first gate on the gate oxide film 12. It is sectional drawing of the state which formed the polysilicon 13. The deposition conditions of the first gate polysilicon 13 are in-situ doped silicon using LPCVD method, and the thickness is 10 to 25% of the total thickness of the predetermined floating gate. To be deposited. That is, the crystal grain size of the polysilicon uses a characteristic having a dependency of thickness. In this case, the deposition condition of the first gate polysilicon 13 may be a condition under which an amorphous silicon film may be formed. When the deposited first gate polysilicon 13 is formed in an inert gas atmosphere for at least 1 hour in a temperature range of 600 to 700 ° C., the amorphous silicon film is grown in a solid state so that the gate oxide wall 3 at the crystal interface 15 is polycrystalline. The first gate polysilicon 13 is formed by being formed of a silicon film. By this process, the first gate polysilicon 13 having a small amount of the gate oxide 3 on the crystal interface 15 is formed in the gate oxide wall (3) on the crystal interface 15 between the crystal grains 14 and the crystal grains. 3) large crystal grains 14 and a flat silicon film are formed without the presence of 3), thereby minimizing the size of the gate oxide wall 3 and uniformly dispersing them so that a locally wide layer of phosphorus 3A is applied. Layer is not formed.
제2b도는 상기 제1게이트 폴리실리콘(13) 상부에 제2게이트 폴리실리콘(16)을 형성한 상태의 단면도이다. 상기 결정입자(14) 상부에 인-시튜 도프트 실리콘을 이용하여 상기 제2게이트 폴리실리콘(16)을 형성한다.FIG. 2B is a cross-sectional view of the second gate polysilicon 16 formed on the first gate polysilicon 13. The second gate polysilicon 16 is formed on the crystal grains 14 using in-situ doped silicon.
제2c도는 상기 증착된 제2게이트 폴리실리콘(16)을 600 내지 700℃ 온도범위에서 1시간이상 불활성 기체분위기에서 형성하면 상기 비정질 실리콘막은 고상성장 되어 결정입자가 큰 다결정실리콘막으로 형성되고, 상기 제1 및 제2게이트 폴리실리콘(13 및 16)간에 매칭되지 않는 결정구조를 가지는 전기저항이 낮은 폴리실리콘막이 형성된다. 이와 같은 공정에 따라 상기 제1 및 제2게이트 폴리실리콘(13 및 16)간에 미세한 결정계면이 형성되어, 하부에는 결정입자(14) 또는 결정입자 사이의 결정계면(15)에 게이트 산화벽(3)이 존재하지 않으면서 크기가 큰 결정입자(14)와 평탄할 실리콘막이 형성된다. 상부에는 큰 결정입자(14A) 또는 그 결정입나 사이의 결정계면(15A)에 게이트 산화벽(3)이 존재하지 않으면서 크기가 큰 결정입자(14A)와 평탄한 실리콘막이 형성되어, 큰 결정입자(14A)를 가지는 제2게이트 폴리실리콘(16) 형성된다.FIG. 2C shows that the deposited second gate polysilicon 16 is formed in an inert gas atmosphere for at least 1 hour in a temperature range of 600 to 700 ° C., whereby the amorphous silicon film is grown in a solid state to form a polycrystalline silicon film having large crystal grains. A low-resistance polysilicon film having a crystal structure that is not matched between the first and second gate polysilicon 13 and 16 is formed. According to such a process, a fine crystal interface is formed between the first and second gate polysilicon 13 and 16, and a lower portion of the gate oxide wall 3 is formed on the crystal grain 14 or the crystal interface 15 between the crystal grains. ), The large crystal grains 14 and the silicon film to be flat are formed. Large crystal grains 14A and large crystal grains 14A and a flat silicon film are formed without the gate oxide wall 3 present on the crystal grains 14A or the crystal grains 15A therebetween. A second gate polysilicon 16 having 14A) is formed.
제2d도는 이상의 공정기술을 이용하여 형성된 플로팅게이트의 단면을 도시한 것이다.2d shows a cross section of the floating gate formed using the above process technique.
상술한 바와 같이 본 발명은 플로팅게이트를 다결정실리콘으로 형성할 때 다결정실리콘을 이중으로 형성하여, 터널 게이트 산화막(Tunnel gate oxide)과 접촉되는 플로팅게이트 폴리실리콘의 결정입자 크기를 크게하고, 결정립 홍이 없도로 형성하므로써, 결정입자 크기가 크고, 결정계면에서의 게이트산화막의 장벽현상이 발생되지 않고, 게이트산화막과 다결정실리콘의 결정입자 사이에서 발생되는 게이트산화벽의 크기를 미세화 시키면서 이를 균일하게 분산시키며, 국부적으로 열화된 터널 게이트 산화막의 인이 도포된 산화막 쪽에 일렉트론 트랩(electron trap)이 감소되고, 높은 장벽(barrier height)이 낮아져서 전류증가에 의한 순간적은 소거 속도가 빠른 지역을 없애주므로써, 과잉 소거의 문제점이 히결되어 소자의 신뢰성을 향상시킬 수 있는 탁월한 효과가 있다.As described above, in the present invention, when the floating gate is formed of polycrystalline silicon, the polycrystalline silicon is formed twice, thereby increasing the crystal grain size of the floating gate polysilicon in contact with the tunnel gate oxide and increasing the grain size. As a result, the size of the crystal grains is large, the barrier phenomenon of the gate oxide film does not occur at the crystal interface, and the size of the gate oxide wall generated between the gate oxide film and the crystal grains of the polycrystalline silicon is finely dispersed, Over-erasing is eliminated by reducing the electron traps on the phosphorus-coated oxide layer of the locally deteriorated tunnel gate oxide layer and reducing the high barrier height, thereby eliminating the areas of instantaneous erase speed due to current increase. Excellent effect that can improve the reliability of device There is.
Claims (5)
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| KR1019950017273A KR0172272B1 (en) | 1995-06-24 | 1995-06-24 | Method of manufacturing floating gate at semiconductor |
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| KR1019950017273A KR0172272B1 (en) | 1995-06-24 | 1995-06-24 | Method of manufacturing floating gate at semiconductor |
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