JPS624375A - Semiconductor device - Google Patents

Abstract

PURPOSE:To level a floating gate electrode and to improve the function of retaining memory by forming the floating gate electrode in a MOS semiconductor device for memory out of a polysilicon semiconductor layer including oxygen. CONSTITUTION:After forming an insulating film 3 and an element isolation region 2 on a substrate 1, a polysilicon layer 4 which will become a floating gate electrode 4a is spread over the whole surface. By ion implantation, oxygen is introduced by a rate of 2-10atom%. After that, the layer 4 is annealed and subjected to patterning to form an electrode 4a. Then, an interlaminar insulating layer 5 is formed and a polysilicon layer is spread to form a control gate electrode 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a floating electrode.

[Summary of the invention]

In a MOS type memory semiconductor device having a floating electrode, the present invention flattens and shapes the gate electrode and improves memory retention characteristics by forming the gate electrode with a polycrystalline semiconductor layer containing oxygen. It is something that

[Conventional technology]

-jBk, BPROM (erasable programmable read only memory) and EIIZPRO
In nonvolatile memories such as M (Electrically Erasable Programmable Read Only Memory), so-called FAMO3 (floating gate electrode) has a floating gate electrode.
Semiconductor devices having a structure called a gate avalanche injection MOS (gate avalanche injection MOS) memory element or a SAMO3 (stacked gate avalanche injection MOS) memory element are known.

A semiconductor device having such a floating gate electrode operates as a nonvolatile memory by accumulating charges in the floating gate electrode due to electron tunneling. Generally, a control gate electrode is formed on the floating gate electrode, and this control gate electrode controls the charge of the floating gate electrode and functions as a unidirectional select electrode. Polysilicon doped with phosphorus is used as the material for the floating gate electrode, and is manufactured by thermally oxidizing the polysilicon to form an insulating film. An example of a semiconductor device having such a floating gate electrode will be briefly described in accordance with the manufacturing process of the semiconductor device, with reference to FIGS. 2a and 2m.

In the conventional semiconductor device having a floating gate electrode, as shown in FIG. 2a, first, an insulating film 103 and an element isolation region 102 are formed on a semiconductor substrate 101 made of silicon or the like by selective oxidation or the like.

Polysilicon, which is an electrode material for a floating gate electrode, is deposited on the main surface of the substrate 101 on which the element isolation regions 102 and the like are formed, doped with phosphorus as an impurity, and patterned into a predetermined pattern. On this patterned floating gate electrode 104, as shown in FIG.
is formed by thermally oxidizing the floating gate electrode 104, and further a control gate electrode 107 is deposited.

(Problems to be Solved by the Invention) The above-described conventional semiconductor device having a floating gate electrode has a problem in that asperities (protrusions) 105 occur. There is a minute asperity, and when the floating gate electrode 104 is thermally oxidized to form the glabellar insulating film 106, the asperity 105 becomes large.
The electric field of both the floating gate electrode 104 and the control gate electrode 107 is concentrated in the area where the floating gate electrode 104 exists, so that the charge accumulated in the floating gate electrode 104 is extracted to the control gate electrode 107. Become.

If the charges accumulated in the floating gate electrode 104 are discharged to the control gate electrode 107 in this way, the retention function as a nonvolatile memory will deteriorate.

Asperity 105, which deteriorates the retention function of memory, occurs particularly when low-temperature thermal oxidation (approximately 950 degrees Celsius) is performed. Floating Day 1 - Electrode 104 and interlayer insulation I! Asperity 105 will be noticeably generated at the interface 1106.

On the other hand, when thermal oxidation is performed at a high temperature instead of at a low temperature, the occurrence of the asperity 105 can be suppressed. However, as a pre-process to the thermal oxidation step, impurities are introduced into a predetermined region of the substrate IO1 by ion implantation, etc., and the substrate 101 having such a predetermined profile region is thermally oxidized at high temperature. If this is done, the profile of impurities introduced by the ion implantation or the like will be disrupted. Therefore, in order to manufacture devices with excellent controllability, thermal oxidation at high temperatures is necessary.
This defeats the purpose, and in order to form high-precision devices, thermal oxidation must be performed at low temperatures.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a semiconductor device that prevents the occurrence of asperities and the like, flattens a floating gate electrode, and improves a memory retention function.

[Means for solving problems]

In a MOS type memory semiconductor device having a floating gate electrode, the above-mentioned problems are solved by a semiconductor device in which the gate electrode is formed of a polycrystalline semiconductor layer containing oxygen.

[Effect]

A gate electrode is formed from a polycrystalline semiconductor layer containing oxygen to prevent asperities and the like from occurring.

That is, oxygen is introduced into the gate electrode by ion implantation or the like to make the gate electrode amorphous and suppress the growth of grains, thereby forming a flat film. Moreover, the effect can be achieved by setting the concentration of introduced oxygen to 2 to 10 atomic %.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

This embodiment is an example of a semiconductor device in which a floating gate electrode is formed of polysilicon and oxygen is introduced into the polysilicon floating gate electrode using ion implantation.

First, as shown in FIG. 1a, an insulating film 3 and an element isolation region 2 are formed on a substrate 1 made of a material such as silicon.

Polysilicon N4, which will later become the floating gate electrode 4a, is deposited on the entire surface on which the element isolation region 2 and the like are formed by CVD or the like, and oxygen is introduced into the polysilicon IW4 by ion implantation.

Here, suitable results can be obtained by introducing oxygen into the polysilicon M4 at a rate of 2 to 10 atomic %, and even more preferably at a rate of 2 to 3 atomic %. First, when the polysilicon layer 4 formed by the above-mentioned CVD method is deposited at a temperature of, for example, about 650°C, its grain size is 200 to 300°C.
It is about the size of a person. When such polysilicon N4 is doped with oxygen at a rate of 2 to 10 atomic percent, the polysilicon layer 4 becomes amorphous. 2 oxygen
When doping is done at a ratio of less than atomic percent, it becomes difficult to obtain the effect of introducing oxygen, and it is difficult to prevent the occurrence of asperities and the like. On the other hand, when oxygen is doped at a ratio of 10 atomic % or more, charges are trapped in the oxygen portion, which makes it difficult to discharge and has an adverse effect. Therefore, as mentioned above, 2
When doped at a ratio of ~IO atomic percent, it is possible to prevent the occurrence of asperities, etc., and to maintain a flat film without irregularities by suppressing grain growth during annealing performed in a later process. . Furthermore, since oxygen is introduced by ion implantation, it is possible to control the ratio of such introduction.

After forming the polysilicon layer 4, oxygen is introduced into the polysilicon ii4 by ion implantation. In this case, not only oxygen but also phosphorus, arsenic, antimony, etc. can be doped with oxygen.

Even when phosphorus, arsenic, antimony, etc. are doped together with oxygen in this way, it is possible to similarly prevent the generation of asperities and maintain a flat film by suppressing the growth of grains during annealing.

After introducing oxygen or oxygen together with phosphorus, arsenic, 7-inch, etc. into the polysilicon layer 4, the polysilicon N4 is annealed. This annealing is, for example, 9
This process is carried out at approximately 00°C and is necessary for activating impurities and for reacting polysilicon and oxygen in advance. The polysilicon layer 4 into which oxygen has been introduced can suppress grain growth during this annealing, and therefore can maintain flatness even during the oxidation process.

After the above-mentioned annealing, as shown in FIG. 1, the polysilicon N4 is patterned by photolithography to form a floating gate electrode 4a. After forming the floating gate electrode 4a, the glabellar insulating layer 5 is formed by an oxidation process. This glabellar insulating layer 5 is formed by performing low-temperature thermal oxidation on the floating gate electrode 4a into which oxygen has been introduced. This thermal oxidation is a low-temperature thermal oxidation (approximately 95%
(about 0° C.), and can be performed using, for example, a pyrogenic material. When performing this thermal oxidation, since the floating gate electrode 4a is made amorphous and the growth of grains is suppressed, phenomena such as generation and enhancement of asperities do not occur on the surface of the electrode 4a. Therefore, a flat electrode surface without irregularities can be maintained.

Glabella insulation M'j by low temperature oxidation process! After formation of polysilicon layer 5, a polysilicon layer forming a control gate electrode is deposited, and after doping with impurities, the polysilicon layer is patterned to form a control gate electrode 6.

Thereafter, the semiconductor device of this example is obtained through predetermined steps such as forming a covering insulating film and a wiring layer.

Next, the operation of the semiconductor device of this example will be briefly explained with reference to FIG. 1C. Incidentally, FIG. 1C schematically shows a semiconductor device corresponding to the sectional view taken along line I-1 in FIG.

A semiconductor device having the structure described above is a normal MO
Similar to the S memory, it has a source 8 and a drain 9 region, and when the control gate 1- is operated by the pole 6, electrons from the channel 10 are tunneled and accumulated in the floating gate electrode 4a, so that it can be used as a non-volatile memory. Operate. Here, in the past, asperities occurred in the portion of the floating gate electrode 4a, and the asperities caused electric field concentration, deteriorating the memory retention function. However, in the semiconductor device of this embodiment, oxygen is introduced into the floating gate electrode 4a and the growth of grains is suppressed, so that asperities etc. can be prevented from occurring, and the surface of the floating gate electrode 4a is A flat film with no unevenness is formed. Therefore, local electric field concentration does not occur, it is possible to prevent leakage of charges from the floating gate electrode 4a, and it is possible to improve the retention function of the memory.

〔Effect of the invention〕

In the semiconductor device of the present invention, since oxygen is introduced into the polysilicon layer forming the floating gate electrode, grain growth is suppressed and the occurrence of asperities etc. can be prevented, and a flat electrode without unevenness can be formed. can do. Therefore, local electric field concentration does not occur, and it has an excellent memory retention function without charge leakage.

[Brief explanation of the drawing]

1st I! 1A and 1A are schematic cross-sectional views during the manufacturing process of a semiconductor device according to the present invention, FIG. 1C is a schematic diagram of a semiconductor device according to the present invention, and FIGS. 1 is a schematic cross-sectional view of a conventional semiconductor device during a manufacturing process. l...Substrate 4...Polysilicon layer 4a...Floating gate electrode 5...Interlayer insulating film 6...Control gate electrode Patent Applicant Sony Corporation Representative Patent Attorney Koike Miki Tamura Sakae - Flow'Tindecate electric carving = yK Figure 2a Asyari 1/) Existence/existence. Figure 2b

Claims (1)

[Scope of Claims] A MOS type memory semiconductor device having a floating gate electrode, wherein the gate electrode is formed of a polycrystalline semiconductor layer containing oxygen.