JPS63195750U - - Google Patents

Info

Publication number
JPS63195750U
JPS63195750U JP8653987U JP8653987U JPS63195750U JP S63195750 U JPS63195750 U JP S63195750U JP 8653987 U JP8653987 U JP 8653987U JP 8653987 U JP8653987 U JP 8653987U JP S63195750 U JPS63195750 U JP S63195750U
Authority
JP
Japan
Prior art keywords
lead frame
board
wiring board
divided
dividing groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8653987U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8653987U priority Critical patent/JPS63195750U/ja
Publication of JPS63195750U publication Critical patent/JPS63195750U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案実施例による2連形リードフレ
ームの外形斜視図、第2図、第3図はそれぞれ第
1図に示したリードフレームの製作法を示す展開
図、および屈曲加工図、第4図、第5図は多数個
取り配線基板への2連形リードフレームの装着状
態を示す側面図、および裏面図、第6図は2連形
リードフレームを用いて組立てた混成集積回路の
製品図、第7図は多数個取り配線基板の平面図、
第8図は従来における差込形リードフレームの装
着工程図、第9図は第7図によるリードフレーム
装着状態の側面図である。各図において、 1:多数個取り配線基板、1a:分割基板領域
、1b:分割溝、1c:リード端子挿入孔、20
:2連形リードフレーム、2a:先端挿入部、2
d,2e:リード端子列、2f:連結片、2g:
分割用切込み溝、3:外付け回路素子。
FIG. 1 is an external perspective view of a double lead frame according to an embodiment of the present invention, and FIGS. Figures 4 and 5 are side and back views showing how the double lead frame is attached to a multi-chip wiring board, and Figure 6 is a hybrid integrated circuit product assembled using the double lead frame. Figure 7 is a plan view of a multi-chip wiring board.
FIG. 8 is a process diagram for attaching a conventional plug-in lead frame, and FIG. 9 is a side view of the lead frame attached according to FIG. 7. In each figure, 1: Multi-chip wiring board, 1a: Divided board area, 1b: Divided groove, 1c: Lead terminal insertion hole, 20
: Double lead frame, 2a: Tip insertion part, 2
d, 2e: Lead terminal row, 2f: Connection piece, 2g:
Dividing groove, 3: External circuit element.

Claims (1)

【実用新案登録請求の範囲】 1 多数個取り配線基板に対し、各個の分割基板
領域毎にその分割溝に沿う側縁部に穿孔されたリ
ード端子挿入孔列へ起立挿入して基板にはんだ付
けされるリードフレームであつて、基板の分割溝
を隔てて隣り合う分割基板領域の各リード端子挿
入孔列に挿入される左右列のリードフレーム部が
挿入状態で双方の分割基板領域にまたがり基板上
面に担持される連結片を介して相互一体に連結さ
れた2連形構造体として成ることを特徴とする多
数個取り配線基板用のリードフレーム。 2 実用新案登録請求の範囲第1項記載のリード
フレームにおいて、連結片の中央部に配線基板側
の分割溝と合致する分割用の切込み溝が形成され
ていることを特徴とする多数個取り配線基板用の
リードフレーム。
[Scope of Claim for Utility Model Registration] 1. In a multi-chip wiring board, each divided board area is inserted vertically into a row of lead terminal insertion holes drilled at the side edge along the dividing groove, and soldered to the board. The lead frame portions of the left and right rows inserted into the respective lead terminal insertion hole rows of the divided board regions adjacent to each other across the dividing groove of the board extend over both divided board regions in the inserted state. 1. A lead frame for a multi-chip wiring board, characterized in that the lead frame is formed as a double structure integrally connected to each other via a connecting piece carried by the lead frame. 2. Multi-piece wiring in the lead frame described in claim 1 of the utility model registration claim, characterized in that a cutting groove for dividing is formed in the center of the connecting piece to match the dividing groove on the wiring board side. Lead frame for circuit boards.
JP8653987U 1987-06-03 1987-06-03 Pending JPS63195750U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8653987U JPS63195750U (en) 1987-06-03 1987-06-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8653987U JPS63195750U (en) 1987-06-03 1987-06-03

Publications (1)

Publication Number Publication Date
JPS63195750U true JPS63195750U (en) 1988-12-16

Family

ID=30942933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8653987U Pending JPS63195750U (en) 1987-06-03 1987-06-03

Country Status (1)

Country Link
JP (1) JPS63195750U (en)

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