JPS63191783U - - Google Patents
Info
- Publication number
- JPS63191783U JPS63191783U JP8202487U JP8202487U JPS63191783U JP S63191783 U JPS63191783 U JP S63191783U JP 8202487 U JP8202487 U JP 8202487U JP 8202487 U JP8202487 U JP 8202487U JP S63191783 U JPS63191783 U JP S63191783U
- Authority
- JP
- Japan
- Prior art keywords
- converter
- converts
- pulse
- latch
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims description 2
- 230000001360 synchronised effect Effects 0.000 claims 2
- 238000006243 chemical reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 1
Landscapes
- Digital Computer Display Output (AREA)
- Television Signal Processing For Recording (AREA)
Description
第1図は本考案の一実施例のブロツク図、第2
図は本考案の技術分野であるCRTハードコピー
装置の全体図、第3図は本実施例の装置のタイミ
ング図、第4図は水平同期と画素との関係を示す
説明図、第5図は本考案の他の実施例を示すブロ
ツク図である。
1……水晶発振器、2……積分回路、3……A
/Dコンバータ、4……ラツチ、5……D/Aコ
ンバータ、6……コンパレータ、7……加算器、
11……ホストコンピユータ、12……CRT、
13……A/Dコンバータ、14……サンプリン
グパルス発生部、15……フレームメモリ、16
……画像処理部、17……プリンタエンジン、1
9……操作パネル。
Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is an overall view of a CRT hard copy device, which is the technical field of the present invention, FIG. 3 is a timing diagram of the device of this embodiment, FIG. 4 is an explanatory diagram showing the relationship between horizontal synchronization and pixels, and FIG. FIG. 3 is a block diagram showing another embodiment of the present invention. 1...Crystal oscillator, 2...Integrator circuit, 3...A
/D converter, 4...Latch, 5...D/A converter, 6...Comparator, 7...Adder,
11...Host computer, 12...CRT,
13...A/D converter, 14...Sampling pulse generator, 15...Frame memory, 16
...Image processing unit, 17...Printer engine, 1
9...Operation panel.
Claims (1)
を持つクロツクパルスを発生する発振器と、前記
クロツクパルスを単調増加のパルス波に変換する
変換手段と、前記パルス波を変換するA/Dコン
バータと、前記A/Dコンバータの出力をラツチ
するnビツトラツチ、前記ラツチに格納されたデ
ータをD/Aコンバータを通した出力と前記単調
増加のパルス波とを入力してサンプリングパルス
を出力するコンパレータを備えた位相同期回路。 2 前記ラツチに格納されたデータを補正用デー
タを加える加算器を通して前記D/Aコンバータ
に送ることを特徴とする実用新案登録請求の範囲
第1項記載の位相同期回路。 3 前記変換手段が前記クロツクパルスを鋸歯状
波に変換する積分回路であることを特徴とする実
用新案登録請求の範囲第1項および第2項記載の
位相同期回路。[Claims for Utility Model Registration] 1. An oscillator that generates a clock pulse that has an arbitrary phase relationship with a synchronization signal and has a stable period, a conversion means that converts the clock pulse into a monotonically increasing pulse wave, and converts the pulse wave. an n-bit latch that latches the output of the A/D converter, and inputs the output of the data stored in the latch through the D/A converter and the monotonically increasing pulse wave to generate a sampling pulse. A phase-locked circuit equipped with a comparator that outputs. 2. The phase synchronized circuit according to claim 1, wherein the data stored in the latch is sent to the D/A converter through an adder that adds correction data. 3. The phase synchronized circuit according to claims 1 and 2, wherein the converting means is an integrating circuit that converts the clock pulse into a sawtooth wave.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8202487U JPS63191783U (en) | 1987-05-28 | 1987-05-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8202487U JPS63191783U (en) | 1987-05-28 | 1987-05-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63191783U true JPS63191783U (en) | 1988-12-09 |
Family
ID=30934303
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8202487U Pending JPS63191783U (en) | 1987-05-28 | 1987-05-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63191783U (en) |
-
1987
- 1987-05-28 JP JP8202487U patent/JPS63191783U/ja active Pending
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