JPH0722937Y2 - Image signal memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to an image signal storage circuit capable of converting an analog image signal into a digital signal and storing the digital signal.

[Prior art]

Conventionally, in general, an image signal storage circuit inputs an input analog image signal and a sampling clock signal created inside the image signal storage circuit into an analog / digital converter to digitally convert the analog image signal. It has a basic structure in which it is converted into a signal and the digital signal is stored in the memory of the memory circuit. Further, as the sampling clock signal, only one fixed to a specific frequency is used.

However, as in the above-described conventional case, when the image processing is performed so that the enlargement or reduction of the image is realized by using only the sampling clock signal fixed to the specific frequency, special software, an arithmetic circuit, or the like is used. Must be done using the above hardware. For this reason, in the conventional image signal storage circuit, since the special software or the hardware such as the arithmetic circuit is used, it is impossible to immediately store the enlarged or reduced image signal in the memory. Had.

[Purpose of device]

The present invention has been made in consideration of the above-mentioned conventional problems. The present invention digitizes an analog image signal by sampling for enlarging or reducing and stores the digitized analog image signal in a memory circuit immediately, and also displays an enlarged or reduced screen. It is an object of the present invention to provide an image signal storage circuit capable of controlling the timing of storing a digital image signal in a memory circuit so that it can be displayed at an optimum portion.

[Constitution of device]

In order to achieve the above-mentioned object, the image signal storage circuit according to the present invention is provided with an analog / digital converter for digitizing an analog image signal, and the digitized image signal is supplied with a constant data per horizontal video period. In a video signal storage circuit that can be stored by a memory circuit by a number, a clock frequency conversion circuit that can constantly generate a clock signal for sampling an analog image signal in an analog / digital converter and can change the frequency of the clock signal And a memory storage start signal generating circuit for storing the sampled digital image signal in the memory circuit according to the change of the frequency of the clock signal, the memory storage start signal generating circuit being capable of changing the storage start time in the horizontal video period. To enlarge or reduce the analog image signal and immediately Manner, characterized by being configured so that it can be stored in the memory.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

The image signal storage circuit uses an analog image signal which is a television video signal as an image signal to be stored, and 512 × 458
It has a pixel memory circuit 11. As shown in FIG. 1, the image signal storage circuit includes a CR oscillator 1, an oscillator circuit (hereinafter referred to as an OSC circuit) 2, a central processing unit (hereinafter referred to as a CPU) 4, and a counter circuit 5. A clock frequency conversion circuit 3 including a latch circuit 7, a comparator 8 and a phase comparison circuit 9 is provided. CR so that the clock signal generated by oscillating with CR oscillator 1 is input.
A CPU 4 is connected to the oscillator 1 and provided. A clock signal f is generated by the OSC circuit 2, and a counter circuit 5 and an analog / digital converter 6 are provided in the OSC circuit 2 so that the clock signal f is input. A latch circuit 7 is connected to the CPU 4 so that the H level period of the clock signal output from the CR oscillator 1 can be counted by software and the data by this count can be latched. Output via this latch circuit 7
A comparator 8 for inputting and comparing the data from the CPU 4 and the divided output obtained by dividing the clock signal f by the counter circuit 5 is connected to the latch circuit 7 and the counter circuit 5. A phase comparison circuit 9 is connected to the comparator 8 for phase comparison between the coincidence output from the comparator 8 and the falling edge of the horizontal synchronizing signal of the television image signal. The OSC circuit 2 is connected to the phase comparison circuit 9 so that the frequency control signal, which is an output signal from the phase comparison circuit 9, controls the oscillation frequency of the OSC circuit 2.
Further, the CPU 4 is provided with a timing circuit so that the counter data and the horizontal synchronizing signal which are counted and output by the CPU 4 according to the output of the CR oscillator 1 are input to the timing circuit 10.
10 are connected. The CR oscillator 1, the CPU 4, and the timing circuit 10 are used to generate a memory storage start signal generation circuit.
Twelve are made up. Then, the memory storage start signal output from the timing circuit 10 is input to the memory circuit 11, and the data signal obtained by converting the analog image signal output from the analog / digital converter 6 into a digital signal is input to the memory circuit 11. As described above, the memory circuit 11 is provided so as to be connected to the timing circuit 10 and the analog / digital converter 6.

In the above configuration, the analog image signal is stored in the memory circuit 11
The movement of the signal in the image signal storage circuit when it is stored in the memory will be described. The clock signal output from the CR oscillator 1 provided with the variable resistor R in the internal oscillation circuit so that the oscillation frequency can be changed steplessly is counted by the CPU 4 during the H level period of the clock signal by software. It The counted number is sent to the latch circuit 7 as frequency division data described later, and latched by the latch circuit 7 so that the same frequency division data can be output until it is released. In the OSC circuit 2, a clock signal f having a reference frequency is output according to a frequency control signal output from a phase comparison circuit 9 described later and input to the OSC circuit 2.
Is made. The clock signal f is input to the counter circuit 5 and divided. The frequency-divided output of the counter circuit 5 and the frequency-divided data are input to the comparator 8 as input signals A and B to the comparator 8, respectively. When the input signals A and B match, the coincidence output signal output from the comparator 8 and the horizontal synchronizing signal are input to the phase comparison circuit 9,
The phase of the coincidence output signal and the falling edge of the horizontal synchronizing signal are compared. The phase output resulting from this phase comparison is input to the OSC circuit 2 as a frequency control signal. Based on this frequency control signal, the OSC circuit 2 changes the oscillation frequency of the clock signal f which is an output signal. Finally, this clock signal f has a frequency corresponding to the clock signal output from the CR oscillator 1, and a horizontal clock signal is input as a sampling clock signal to the analog / digital converter 6 in order to sample the analog image signal. It is output from the OSC circuit 2 in a state where the timing matches the synchronization signal. As described above, when the resistance value of the variable resistor R of the CR oscillator 1 is changed, the frequency of the clock signal f of the OSC circuit 2, that is, the sampling clock signal is also changed according to the resistance value. The analog / digital converter 6 digitizes the analog image signal on the basis of the input sampling clock signal and the analog image signal, and outputs the memory circuit.
Outputs the digital signal sent to 11. And CR
Memory storage for inputting the counter data counted by the CPU 4 according to the clock signal output from the oscillator 1 and the horizontal synchronizing signal to the timing circuit 10 so that the memory circuit 11 starts storing the digital signal. A start signal is sent from the timing circuit 10 to the memory circuit 11.
As shown in FIG. 2, during the period between one horizontal synchronizing signal and the next horizontal synchronizing signal, the storage of digital data is started from the time when the memory storage start signal is input to the memory circuit 11. The time t from the fall of the horizontal synchronizing signal to the start of storing the digital data in the memory circuit can be freely changed according to the clock signal output from the CR oscillator 1. By the above,
Changing the resistance value of the variable resistor R of the CR oscillator 1 changes the frequency of the sampling clock signal. Specifically, for example, if the resistance value of the variable resistor R of the CR oscillator 1 is increased and the frequency of the sampling clock signal is decreased, the analog image signal is roughly sampled, so that the image is reduced in size. Will be stored in the memory circuit 11. At this time, the width of sampling of the analog image signal in the horizontal video period increases, so that in order to store a fixed number of digital data in the memory circuit 11, it is necessary to start the storage immediately from the horizontal synchronizing signal. Therefore, in this case, the time t is set to be short. On the contrary, if the resistance value of the variable resistor R is decreased and the frequency of the sampling clock signal is increased, the analog image signal is sampled finely, so that it is stored in the memory circuit 11 in an enlarged form as an image. become. At this time, the sampling interval is narrowed and the area where the analog image signal is sampled in the horizontal video period is narrowed. Therefore, if t is short as in the above case, only the first half of the horizontal video period in the analog image signal can be sampled. It may disappear. Therefore, in order to store a fixed number of digital data in the memory circuit 11 in the central portion of the horizontal video period, it is necessary to start the storage with some delay from the horizontal synchronizing signal. In this case, the time t is set to be long. It Here, in the memory circuit 11, one line is completed when 512 digital data are stored. The same applies when reducing the size.

[Effect of device]

As described above, the image signal storage circuit of the present invention is provided with the analog / digital converter which digitizes the analog image signal with a constant number of data per horizontal video period, and the digitized image signal is stored in the memory circuit. An image signal storage circuit capable of storing is provided with a clock frequency conversion circuit capable of constantly generating a clock signal for sampling an analog image signal by an analog / digital converter and changing the frequency of the clock signal. A memory storage start signal generating circuit for storing the sampled digital image signal in the memory circuit in accordance with the change of the frequency of the clock signal and capable of changing the storage start time in the horizontal video period is provided. Thus, when the analog image signal is enlarged or reduced and stored in the memory circuit, it is not necessary to use special software or hardware such as an arithmetic circuit, and the analog image signal can be immediately stored in the memory circuit. Play. Further, by changing the storage start time in the horizontal video period for storing the digital image signal in the memory circuit according to the change of the frequency of the clock signal, for example, the frequency of the clock signal is increased and the sampling interval is narrowed. If the storage start time is set to be late when it becomes, it is possible to store the digital image signal corresponding to the central portion of the image.

[Brief description of drawings]

1 and 2 show an embodiment of the present invention. FIG. 1 is a block diagram showing an image signal storage circuit, and FIG.
The figure is a timing chart showing the relationship between the horizontal synchronizing signal and the digital signal when the digital signal is stored in the memory circuit. 1 is a CR oscillator, 2 is an OSC circuit, 3 is a clock frequency conversion circuit, 4 is a CPU, 5 is a counter circuit, and 6 is analog /
Digital converter, 7 is a latch circuit, 8 is a comparator, 9 is a phase comparison circuit, 10 is a timing circuit, 11 is a memory circuit,
Reference numeral 12 is a memory storage start signal generation circuit.

Claims (1)

[Scope of utility model registration request] 1. An image signal storage circuit provided with an analog / digital converter for digitizing an analog image signal and capable of storing the digitized image signal with a constant number of data per horizontal video period by a memory circuit. In the above, there is provided a clock frequency conversion circuit capable of constantly generating a clock signal for sampling an analog image signal by an analog / digital converter and changing the frequency of the clock signal, and changing the frequency of the clock signal. Accordingly, an image signal storage circuit is provided which is provided with a memory storage start signal generation circuit for changing the storage start time in the horizontal video period for storing the sampled digital image signal in the memory circuit.