JPH02269056A - Video signal printer - Google Patents

Abstract

PURPOSE:To eliminate the noise of a synchronizing signal and fetching errors due to the distortion of a period by fixing the frequency of a fetched clock until the fetching of video signals is completed after printing start information is input from an operation panel. CONSTITUTION:An operator inputs a printing start instruction to an operation panel 4, which converts printing start into digital data and outputs it to a control part 3. When the digital data is input, the control part 3 outputs data fetching start information to a video signal converting part 2, synchronizes with internal synchronization 20, and instructs a switching circuit 17 to bring a switching signal 16 into the level at which the internal synchronization 20 is selected. When the switching circuit 17 brings the switching signal 16 into the level to select the internal synchronization 20, a PLL circuit 6 does not change the oscillation frequency of the fetched clock 13 even if a period of the internal synchronization 20 varies. Consequently, noise carrying on the synchronizing signal and fetching errors due to the distortion of the period of the synchronizing signal can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal printing device that generates a video signal capture clock based on a synchronization signal and the number of horizontal clocks.

[Summary of the invention]

Since the video signal printing device of the present invention fixes the capture clock at the video signal capture interval, there is no capture error and no printing noise even if there is noise or period disturbance in the synchronization signal.

Furthermore, since the capture clock is fixed only during the video signal capture period, no adverse effects occur due to the fixation of the capture clock.

[Conventional technology]

Conventionally, in a video signal printing device, an internal synchronization period is divided by the number of horizontal clocks, a capture clock is generated in accordance with this, and a video signal is captured.

[Problem to be solved by the invention]

For this reason, in conventional circuits, if the noise or period of the synchronization signal becomes unstable, a video signal capture error occurs, resulting in noise in printing.

In addition, in the case of a short back pouch, if equalizing pulses or serration pulses are input during the blanking section of the synchronization signal, the synchronization will be disrupted, causing the acquisition clock to change, taking time to stabilize again, and causing noise at the top of the print. There has occurred.

SUMMARY OF THE INVENTION An object of the present invention is to provide a video signal printing device having a PLL section that can fix a capture clock in any interval.

[Means to solve the problem]

In order to solve the above problems, there is a host device 1 that outputs a video signal and a synchronization signal, and a video signal that captures the video signal with a capture clock 13 and sends print data and a print synchronization signal to the printing unit 5 based on a control signal 14. a conversion unit 2, a printing unit 5 that prints the print data according to a print synchronization signal, and a level conversion unit 1 that converts the input synchronization signal to an internal level.
1, an operation panel 4 that converts information input by an operator into digital data, and converts and outputs the digital data from the operation panel 4 as a horizontal clock number of 15, synchronizing with the output of the level converter 11. a control unit 3 that outputs a sudden change signal 16 and a control signal 14; an SC circuit 9 that divides the input clock 13 by a set number of horizontal clocks 15; ICI, IC2, and IC3. , IC4, the outputs of the level converter 11 and the SC circuit 9 are human powered, and the switching circuit 17 outputs one of the two human powered outputs according to the sudden change signal 16, and the input and output of the switching circuit 17 is A delay circuit 12 that outputs a signal obtained by delaying the output of the level converter 11 by the same amount as the delay amount, and the outputs of the delay circuit 12 and the switching circuit 17 are input, the phases of these two signals are compared, and the difference is determined. 20 circuits that change the output voltage level 7
and a vCO which uses the output of the 20 circuits 7 manually and outputs an input clock 13 with a frequency corresponding to the input voltage level.
It is constructed from a PLL section 6 consisting of a 00 circuit 8.

[Effect]

According to the present invention, since the video signal capture clock is fixed during the video signal capture interval, a video signal printing device that does not generate noise during printing even if there is only synchronization signal noise or synchronization signal period can be achieved. You can get it.

〔Example〕

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

As shown in the block diagram of FIG. 1, this device is a host device 1.
・Video signal conversion section 2, printing section 5, level conversion section 11, control section 3, operation panel 4, V
It is composed of a PLL section 6 consisting of a CO00 circuit 8, an SC circuit 9, a PC circuit 7, a delay circuit 12, and a switching circuit 17 composed of ICI, IC2, IC3, and IC4.

In the circuit of FIG. 1, the amount of delay of the delay circuit 12 is:
It is set to be equal to the input/output delay amount of the switching circuit 17.

Further, IC1 to IC4 use ECL.

The SC circuit 9 is a swallow counter.

Further, the 20 circuit 7 has a down etch trigger phase comparison type phase characteristic.

Next, the operation will be explained.

The operator inputs the horizontal clock value from the operation panel 4 in advance.

The operation panel 4 outputs a signal obtained by converting the horizontal clock value into digital data to the control section 3.

The control unit 5 converts the digital data into a horizontal clock number that can be normally divided by the SC circuit 9, and sets the value in the SC circuit 9.

The host device 1 sends the video signal to the video signal converter 2,
A synchronizing signal is output to the level converter 11.

The level conversion section 11 converts the synchronization signal into an internal synchronization signal 20 and outputs it to the control section 3, the delay circuit 12, and the switching circuit 17.

Initially, the control section 3 is at a level at which the switching signal 16 is selected, and the switching circuit 17 is at a level at which the frequency-divided signal 18 is selected.

The PC circuit 7 receives the frequency-divided signal 1 passing through the switching circuit 17.
8 and the internal synchronization signal 20 passing through the delay circuit 12, and outputs a voltage corresponding to the difference from the vCO00 circuit.

The VCO circuit 8 oscillates at a frequency matching the input voltage and generates a capture clock 13.

The SC circuit 9 divides the frequency of the capture clock 13 by the horizontal clock value and outputs a frequency-divided signal 18.

The PLL section 6 changes the oscillation frequency of the acquisition clock 13 until the phase difference between the internal synchronization 20 and the frequency-divided signal 18 becomes zero.

An operator inputs a command to start printing into the operation panel 4.

The operation panel 4 converts the print start into digital data and outputs it to the control section 3.

When the digital data is input, the control section 3 outputs information to start data acquisition to the video signal conversion section 2, synchronizes with the internal synchronization 20, and sends the switching signal 16 to the switching circuit 17, which starts the internal synchronization 20. to the level of your choice.

When the switching signal 16 is at a level that selects the switching circuit 17 and the internal synchronization 20, the PLL circuit 6 does not change the oscillation frequency of the acquisition clock 13 even if the cycle of the internal synchronization 20 changes. .

When the video signal converter 2 receives the information to start capturing from the control unit 3 as a control signal 14, it captures the video signal output from the host device using the capture clock 13, and outputs the print data and print synchronization signal. is output to the printing section 5.

The printing unit 5 starts printing the print data according to the print synchronization signal.

After counting a predetermined number, the control unit 3 returns to the initial level.

〔Effect of the invention〕

As described above, according to the present invention, changes in the oscillation frequency of the PLL circuit can be suppressed for a certain period of time, so there is no noise on the synchronization signal or changes in the input clock due to disturbances in the period of the synchronization signal, and the video signal conversion section It is possible to eliminate printing errors due to printing errors and printing noise without causing any errors in importing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the present invention, and FIG. 2 is a timing chart of FIG. 1. 1...Host device 2...Video signal conversion unit 3...Control unit 4...φ operation panel 5...Printing unit 6...PLL unit 7...20 circuits 8...100 circuits 9...SC circuit 12...Delay circuit 17...Switching circuit diagram

Claims (1)

[Claims] In a device that receives a video signal as an output of image data and prints and records the image data, there is a host device that outputs a video signal and a synchronization signal, and a host device that outputs print data and a print synchronization signal based on the input video signal. a video signal converter; a print unit that prints and records print data in synchronization with the print synchronization signal; a level conversion unit that converts the print synchronization signal into internal synchronization; A PLL circuit selects whether to output a frequency capture clock or fix the current frequency of the capture clock using a switching signal, an operation panel converts input information into digital data, and print information is input. , a control unit that counts internal synchronization by a specified number, switches the switching signal, and converts the horizontal clock number into an input value to the PLL unit.When print start information is input from the operation panel, the video signal is A video signal printing device characterized in that the frequency of a capture clock is fixed until capture is completed.