JP3125910B2 - Synchronous capture circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video processing technique, and more particularly to a circuit for capturing an external synchronization signal in a digital video processing device.

[0002]

2. Description of the Related Art FIG.
As shown in FIG. 5, a PLL circuit 1 for generating a clock signal S2 and an internal HD signal S3 in synchronization with an external HD signal S1 input from the outside, and an external VD signal S5 input from the outside, the clock signal S2 and the internal HD signal Internal VD generation means 4 latching by S3 to generate internal VD signal S6
And an internal HD signal S in phase with the internal VD signal S6
7 and an internal HD generation circuit 8 for generating
The signal 7 and the internal VD signal 6 were produced. However, in such a configuration, the clock signal S2 gated by the internal HD signal 3, as shown in the timing chart of FIG.
If the changing portion (rising or falling) of the external HD signal S5 happens to be in the vicinity of the rising phase of the external VD signal S5, the external VD signal S5 is taken in or out of this phase, so that the pulse width of the generated internal VD signal S6 is generated. However, there is a problem that the width becomes narrower or wider by 1H.

[0003]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and is capable of generating an internal VD signal having a stable pulse width regardless of the phase relationship between an external HD signal and an internal clock. It is an object of the present invention to provide a synchronizing circuit that can be used.

[0004]

According to the present invention, there is provided a PLL circuit for generating a clock signal and an internal HD signal in synchronization with an externally input HD signal.
A one-clock delay circuit for delaying the internal HD by one clock, switching means for switching between an internal HD signal from the PLL circuit and a delayed HD signal from the one-clock delay circuit, and an external VD signal input from the outside to the clock signal And an internal VD signal generating means for generating an internal VD signal in response to an HD signal from the switching means, a pulse width detecting means for detecting a pulse width of the internal VD signal, and storing the detected pulse width every time. A pulse width change detecting means for detecting a change in the pulse width; and a count means for counting the number of changes and inverting an output signal when a predetermined number of changes are counted. To control.

[0005]

According to the structure described above, according to the synchronous capture circuit of the present invention, a change in the pulse width of the internal VD signal generated by latching the external VD signal with the internal HD signal and the clock signal is detected. When there are many changes, the internal HD
The signal is switched to the internal HD signal delayed by one clock, and the external VD signal is synchronized with the clock gated by the internal HD.
I try to capture the signal.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a synchronous fetch circuit according to the present invention; FIG. 1 is a main block diagram showing an embodiment of a synchronization acquisition circuit according to the present invention. In the figure, reference numeral 1 denotes a PLL circuit, which is an external H input from the outside.
A clock signal and an internal HD signal are generated in synchronization with the D signal. Reference numeral 2 denotes a one-clock delay circuit, which latches the internal HDD signal generated by the PLL circuit once and reads it with the next clock to delay the internal HDD signal by one clock. Reference numeral 3 denotes switching means, which is an internal HDD signal from the PLL circuit and a delay H from the one-clock delay circuit.
D signal. 4 is an internal VD generating means,
An internal VD signal is generated by latching an external VD signal input from the outside with a clock signal gated by an HD signal input from the switching means. Numeral 5 is a pulse width detecting means, which comprises a differentiating circuit 5a for differentiating the signal from the internal VD generating means and an HD counting means 5b for counting the HD signal from the switching means 3;
The pulse width of the internal VD signal is detected by setting and resetting the HD counting means 5b with the differentiated pulse from a and counting the number of HDs in the VD signal from the internal VD generation means. 6 is a pulse width change detecting means,
A width latch circuit 6a for latching a pulse width detection signal of the VD signal from the pulse width detection means 5, a VD pulse width detection signal from the pulse width detection means 5, and a VD of 1V before the width latch circuit 6a. It comprises a pulse width comparison means for comparing the pulse width detection signal and a change latch circuit 6c for storing the comparison result, and detects a change in the VD pulse width. Numeral 7 denotes a counting means, which is constituted by, for example, a 4-bit counter, receives the change detection signal from the pulse width change detecting means 6, counts the number of changes, and inverts the output signal of the maximum bit when the number reaches eight. I have. Reference numeral 8 denotes an internal HD generating means for delaying the HD signal from the switching means 3 to VD
And the internal HD signal is used as the internal HD signal. When the input external drive signal (HD, VD signal) is an interlace signal, the internal HD signal from the PLL circuit 1 has a double frequency. This is supported by dividing the frequency.

Next, the operation of the above configuration will be described. FIG. 2 is a timing chart showing the signal timing of each part of the synchronous acquisition circuit according to the present invention. The operation will be described with reference to FIG. S1 is PL from outside
The PLL circuit 1 generates a clock signal S2 synchronized with the external HDS1 and an internal HD signal S3. The clock signal S2 is input to the internal VD generation means 4, and the external HD signal is input to the L circuit 1. S3 is input to the one-clock delay circuit 2 and the switching means 3. The one-clock delay circuit 2 generates a delayed HD signal S4 for delaying the internal HD signal S3 by one clock, and
Is being entered. The switching means 3 switches between the internal HD signal S3 and the delayed HD signal S4 and switches the HD.
The signal (S3 or S4) is input to the internal VD generation means 4 and the pulse width detection means 5. Internal VD generation means 4
Then, the clock signal S2 is gated by the HD signal (S3 or S4) to be switched, and the externally input external VD signal S5 is latched with the gated clock signal S2g as a trigger to generate the internal VD signal S6. The internal VD signal S6 is used for internal signal processing, and is input to the pulse width detection means 5. In the pulse width detecting means 5, a differentiating circuit 5a differentiates the internal VD signal S6 to generate a falling pulse and a rising pulse, resets the HD counting means 5b with the falling pulse, and switches the input HD signal (S3). Or, start counting S4) and set the HD counting means 5b with the rising pulse to set the HD included in the pulse width of the internal VD signal S6.
The signal (S3 or S4) is counted, and the HD number N is input to the pulse width change detecting means 6. The pulse width change detection means 6 inputs the number N of HDs to the width latch circuit 6a, latches them at the timing of the falling pulse, and compares the number N of HDs to be latched with the number N of HDs input 1V later.
b, the change in the number of HDs is detected, the result is stored in the change latch 6c, and the change latch signal S9 is input to the counting means 7. The counting means 7 counts the number of inversions of the change latch signal S9, and inputs a maximum bit signal S10 to a control input terminal of the switching means to control switching. For example, if the external VD signal is
When the phase of the external HD signal is shifted like S5a and S5b shown in the timing chart of FIG. 2, the internal HD of S3 is used in the case of S5a, and the delayed HD of S4 is used in the case of S5b. Since the control is performed to generate the internal VD signal S6a or S6b, the pulse width of the internal VD signal does not change by 1H unlike the related art. The HD used internally inputs the switching HD signal (S3 or S4) to the internal HD generation circuit 8 and generates the internal HD signal S7 in phase with the internal VD signal.

[0008]

As described above, according to the synchronization capturing circuit of the present invention, the change in the pulse width of the internal VD signal generated by latching the external VD signal by the internal HD signal and the clock signal is detected. When the change is large, the internal HD signal is switched to the internal HD signal delayed by one clock, and the external VD signal is taken in synchronization with the clock gated by the internal HD. No matter what the phase relationship is, an internal VD signal having a stable pulse width can be generated.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing an embodiment of a synchronization acquisition circuit according to the present invention.

FIG. 2 is a timing chart showing one embodiment of a synchronization acquisition circuit according to the present invention.

FIG. 3 is a main block diagram showing a conventional synchronous capture circuit.

FIG. 4 is a timing chart of a conventional synchronous capture circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 PLL circuit 2 1 clock delay circuit 3 switching means 4 internal VD generation means 5 pulse width detection means 5 a differentiation circuit 5 b HD counting means 6 pulse width change detection means 6 a width latch circuit 6 b comparison means 6 c change latch circuit 7 counting means 8 internal HD Generating means

Claims (5)

(57) [Claims] 1. A PLL circuit for generating a clock signal and an internal HD signal in synchronization with an external HD signal input from the outside, a one-clock delay circuit for delaying the internal HD by one clock, and an internal part of the PLL circuit. Switching means for switching between an HD signal and a delayed HD signal from a one-clock delay circuit; internal VD generating means for generating an internal VD signal from an external VD signal input from the outside in accordance with the clock signal and the HD signal from the switching means; Pulse width detection means for detecting the pulse width of the internal VD signal, pulse width change detection means for storing the detected pulse width each time and detecting a change from the previous pulse width of VD, and counting the number of times of the change ,
A synchronous capturing circuit, comprising: counting means for inverting an output signal when a predetermined number of changes are counted, wherein the switching means is controlled by an output signal of the counter and the means. 2. The synchronous capture circuit according to claim 1, wherein the internal HD generated by the PLL is input to the internal VD generation means as a frequency twice as high as that of the external HD. 3. The pulse width detecting means includes a differentiating circuit for differentiating an internal VD signal, and an HD counting means for counting the number of internal HDs in the width of the internal VD. 2. The synchronous acquisition circuit according to claim 1, wherein the synchronization is detected. 4. The pulse width change detection means includes: a latch circuit for latching a pulse width from the pulse width detection means every time; and a comparison means for comparing an output of the latch circuit with an output of the pulse width detection means. And a change latch circuit that stores the comparison signal, and detects a change in the pulse width. 5. The apparatus according to claim 1, wherein said counting means uses a maximum bit output for controlling said switching means as a counter circuit for counting a change detection signal from said pulse width change detecting means. 2. The synchronous capture circuit according to 1.