JPH04240972A - Horizontal synchronizing signal detector - Google Patents

Abstract

PURPOSE:To prevent production of counter noise in the horizontal synchronizing signal detector of an external synchronization system. CONSTITUTION:A counter circuit consists of n-bit J-K flip-flops 315-322 (FF), a Q output of a (K-1(3<K<n))th-bit FF and Q output of FF of (K-2)th bit or below are inputted to an AND gate and the gate output is coupled with the input of a K-th bit FF and then the processing is repeated to form a 1H counter in which simultaneous change number of FFs is uniformized with respect to the clock input. Thus, production of counter noise is suppressed to minimize or prevent the effect onto an analog signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal synchronization signal detection device for an external synchronization system such as a TV camera.

0002

2. Description of the Related Art Currently, in the field of factory automation and monitoring systems, a method is common in which a plurality of TV cameras are externally synchronized and the cameras are switched according to conditions. As an external synchronization method,
A method is adopted in which a composite synchronization signal SYNC is given to each TV camera, and a horizontal synchronization signal and a vertical synchronization signal are separated within each TV camera to achieve horizontal and vertical synchronization.

FIG. 5 shows a schematic diagram of a horizontal synchronization section in the external synchronization method. 51 is a horizontal synchronizing signal separation circuit, 52 is a phase comparator, 53 is a VCO, and 54 is an internal pulse generation circuit, which generates various pulses necessary for camera signal processing. In FIG. 5, first, the input composite synchronization signal SYNC
The horizontal separation circuit 51 separates the horizontal synchronizing signal HD'. This horizontal synchronization signal HD' is input to the phase comparator 52 together with the horizontal synchronization signal HD obtained by frequency-dividing the clock CK oscillated by the VCO 53 by the internal pulse generation circuit 54, and controls the VCO 53 according to the phase shift. It is possible to obtain a horizontal synchronization signal that is synchronized with the external composite synchronization signal SYNC.

FIG. 6 is a block diagram of a horizontal synchronization signal separation circuit in the horizontal synchronization signal detection device of FIG. is a counter reset control circuit; 63 is a counter; the counter reset control circuit 62 determines the operating period of the counter 63 based on the output of the edge detection circuit 61 and the output of the counter 63; Reference numeral 64 denotes a horizontal synchronization signal generation circuit which receives the output of the edge detection circuit 61 and the reset output of the counter reset control circuit 62 and generates the horizontal synchronization signal HD'.

FIG. 7 is a waveform diagram showing the pulse timing of each circuit in FIG. 71 is external composite synchronization signal S
YNC, 72 is the output waveform of the edge detection circuit 61 in FIG. 6, which in this case detects the falling edge of the input pulse. Reference numeral 73 is a counter start pulse outputted from the counter reset control circuit 62 in FIG. 76 is output from the counter reset control circuit 62 in FIG.
This is a counter reset pulse for resetting the . 74 is a clock input to the counter 63 in FIG. 75 indicates the operating period of the counter 63 in FIG. 6, and the counter 63 is operating only during the hatched period. 77 is a horizontal synchronizing signal HD' output from the horizontal synchronizing signal generating circuit 64 in FIG.

[0006] The operation of the horizontal synchronizing signal detecting device constructed as described above will be explained below. First, the external composite synchronization signal SYNC71 of FIG. 7 is applied to the edge detection circuit 61 of FIG.
is input, and a falling edge of the external composite synchronization signal SYNC as shown at 72 in FIG. 7 is detected. When the output of the edge detection circuit 61 is input to the counter reset control circuit 62 in FIG.
starts counting. and external composite synchronization signal SYN
Of C, the time (1/2
After two or more horizontal scanning periods have elapsed, the counter reset control circuit 62 generates a counter reset pulse shown at 76 in FIG. 7 based on the output of the counter 63, and resets the counter 63. With the edge detection circuit output 72 and counter reset pulse 76 as input, the horizontal synchronization signal generation circuit 64 generates an external horizontal synchronization signal HD' shown at 77 in FIG.

[0007]

However, in the conventional horizontal synchronizing signal separation circuit described above, there are periods in which the counter operates and periods in which it stops within the video scanning period. In some binary counters, the number of simultaneous changes in flip-flops is non-uniform with respect to the clock input. If such a horizontal synchronization signal detection circuit is placed on the same chip as the drive circuit of a device that handles analog signals such as an image sensor, the uneven number of simultaneous changes will generate counter noise and affect the analog signal. There was a problem with the impact.

The present invention solves the above-mentioned problems by providing a horizontal synchronization signal detection device that can constantly operate a counter within a video scanning period and can equalize the number of simultaneous changes in flip-flops with respect to a clock input. The purpose is to

[0009]

[Means for Solving the Problems] In order to solve the above problems, the horizontal synchronization signal detection device of the present invention includes a detection circuit for detecting a falling edge or a rising edge of a composite synchronization signal, and a counting stage having an n-bit configuration. Among them, the output of an AND circuit to which the positive logic output of the counting stage of bit K-1 (K is a natural number from 3 to n) and the negative logic output of the counting stage of bit K-2 and below is input, or K-1 A counting circuit in which the output of an OR circuit into which the negative logic output of the bit-th counting stage and the positive logic output of the K-2th bit and below is input is coupled to the K-th counting stage, and the output of the detection circuit. and a control circuit for the counting circuit that starts counting in the counting circuit and stops counting by the counting circuit after counting a number of clocks corresponding to about one horizontal scanning period.

0010

[Function] With this configuration, the counter can always operate within the video scanning period, and the number of simultaneous changes in flip-flops with respect to the clock input can be made uniform with respect to the clock input, suppressing the occurrence of counter noise and The influence on the signal can be minimized or prevented.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a horizontal synchronization signal detection device in one embodiment of the present invention. In FIG. 1, 1 is an edge detection circuit which receives an external composite synchronization signal SYNC and detects its fall or rise, 2 is a counter reset control circuit, and 3 is a 1H counter. The counter reset control circuit 2 determines the operating period of the 1H counter 3 based on the output of the edge detection circuit 1 and the output of the 1H counter 3. Reference numeral 4 denotes a horizontal synchronization signal generation circuit which receives the output of the edge detection circuit 1 and the reset output of the counter reset control circuit 2 as inputs and generates an external horizontal synchronization signal HD'.

FIG. 2 is a waveform diagram showing the pulse timing of each circuit in FIG. 1. 20 is a horizontal blanking pulse. 21 is the external composite synchronization signal SYNC, 22 is Fig. 1
This is the output waveform of the edge detection circuit 1 in this case, and in this case, the falling edge of the input pulse is detected. 23 is a counter start pulse outputted from the counter reset control circuit 2 in FIG. 1 and used to put the 1H counter 3 into operation. 26 is a counter reset pulse output from the counter reset control circuit 2 in FIG. 1 for resetting the 1H counter 3. 24 is a clock input to the 1H counter 3 in FIG. 25 indicates the operating period of the 1H counter 3 in FIG.
H counter 3 is operating. 27 is an external horizontal synchronization signal H output from the horizontal synchronization signal generation circuit 4 in FIG.
D'.

The operation of the horizontal synchronizing signal detecting device constructed as described above will be explained below. First, the external composite synchronization signal SYNC21 of FIG. 2 is input to the edge detection circuit 1 of FIG. 1, and a falling edge of the external composite synchronization signal SYNC as shown at 22 in FIG. 2 is detected. When the output of the edge detection circuit 1 is input to the counter reset control circuit 2 in FIG. 1, the 1H counter 3 starts counting as shown at 25 in FIG. Then, from the start of the horizontal retrace period after counting the number of clocks equivalent to about one horizontal scanning period to the fall of the external composite synchronization signal SYNC21, 1
The counter reset control circuit 2 is activated by the output of the H counter 3.
Create the counter reset pulse shown in 26 in Figure 2,
1H counter 3 is reset. With the edge detection circuit output 22 and counter reset pulse 26 as inputs, the horizontal synchronization signal generation circuit 4 generates an external horizontal synchronization signal HD' shown at 27 in FIG.

Next, the basic configuration and operation of the 1H counter 3 shown in FIG. 1 will be explained using FIGS. 3 and 4. In FIG. 3, 311 is a clock input terminal, 312 is an input terminal for the counter start pulse output from the counter reset control circuit 2 in FIG. 1, and 313 is an input terminal in FIG.
The input terminal 314 for the counter reset pulse outputted from the counter reset control circuit 2 in FIG. 1 is a counter output terminal for inputting to the counter reset control circuit 2 in FIG. 315 to 322 are J-K flip-flops, 323 is R-S flip-flop, 3
24 to 329 are logic gates for the logic decoder section, respectively.

Here, the JK flip-flop 315
.about.322 counts the clock input from the clock input terminal 311, starts operating and is reset by the start pulse and reset pulse from the input terminals 312 and 313. In addition, J-K flip-flops 315 to 322
is composed of n bits, and the J-K flip-flop (for example, 3
The output of an AND gate (for example, 324), which is a logic gate for the logic decoder section, into which the Q output of It is coupled to the J,K inputs of a JK flip-flop (eg 317).

FIG. 4 is a time chart of FIG. 3. Figure 4
411 is the horizontal blanking pulse, 412 is the external composite synchronization signal SYNC, 413 is the clock input waveform, 414 to 421 are the output waveforms of the J-K flip-flops 315 to 322 shown in FIG. 3, and 422
is the counter start pulse input terminal 31 shown in FIG.
2, the input waveform 423 is the input waveform of the counter reset pulse input terminal 313 shown in FIG.

The operation of the 1H counter configured as described above will be explained below. First, when the counter start pulse 422 of FIG. 4 is input to the counter start pulse input terminal 312 of FIG. 3, the J-K flip-flops 315 to 322 of FIG. When input, J-
K flip-flop 315 inverts the Q output at the falling edge of its clock. Therefore, when the clock input waveform 413 of FIG. 4 is input from the clock input terminal 311 of FIG. 3, the Q output waveform of the JK flip-flop 315 becomes the output waveform 414 of FIG.

Next, the input of the JK flip-flop 316 decodes the Q output of the JK flip-flop 315. That is, the J-K flip-flop 31
The Q output of 6 is the Q output of the J-K flip-flop 315.
When the output is at H level, it is inverted at the rising edge of the clock. Therefore, the Q output waveform of flip-flop 316 becomes as shown at 415 in FIG.

Next, the JK flip-flop 31 in FIG.
The input of 7 is the AN of the Q output of the J-K flip-flop 316 and the NQ output of the J-K flip-flop 315.
The output of D gate 324 is decoded. That is, the Q output of the JK flip-flop 317 is JK
When the Q output of flip-flop 316 is at H level and the NQ output of flip-flop 315 is at H level, it is inverted at the rising edge of the clock. Therefore, the Q output waveform of flip-flop 317 becomes as shown at 416 in FIG.

Thereafter, by repeating the above steps, the Q output waveforms of the JK flip-flops 318 to 322 in FIG. 3 are changed to 4 in FIG.
17 to 421. Therefore, J in Figure 3
The Q outputs of the -K flip-flops 315 to 322 are Gray code outputs in which the number of simultaneous changes is 1 from the results of 414 to 421 in FIG.

The Q output of the JK flip-flop 322 in FIG. 3 is as shown at 421 in FIG. 4, from the rise of the horizontal blanking pulse 411 in FIG. standing between. This is used as a counter output at counter output terminal 3 in Figure 3.
14 and input to the counter control circuit 2 of FIG. 1, the counter control circuit 2 of FIG. 1 outputs the counter reset pulse 423 of FIG. When the counter reset pulse 423 of FIG. 4 is input to the counter reset pulse input terminal 313 of FIG. 3, the JK flip-flops 315 to 322 of FIG. 3 are reset.

As described above, according to this embodiment, the counter always remains in an operating state during the video scanning period, and furthermore, the number of simultaneous changes in the logic circuits constituting the counting circuit is uniform with respect to the rising or falling edge of the clock input. By being
Counter noise that affects analog signals can be minimized or prevented.

In this embodiment, the 1H counter may be constructed of any bits that are constructed of a 6-bit counting circuit. In addition, although the Q output of the J-K flip-flop indicating the most significant bit is used as the counter output, the output of each J-K flip-flop is The decoded data may be output as a counter output. When the counter reset pulse is input, all of the JK flip-flops are cleared, but at this time, the state of each JK flip-flop may be set to H or L level.

Furthermore, the logic circuit of the counting stage of the counting circuit is J-
The positive logic output of the J-K flip-flop, which is a counting stage of the K-1 (K is a natural number from 3 to n) bit, is composed of a K flip-flop and an AND gate which is a logic circuit for the logic decoder section. - J which is the counting stage below the 2nd bit
-The negative logic output of the K flip-flop is input to an AND gate, which is an AND circuit, and the output of this AND circuit is coupled to the input of the J-K flip-flop, which is the K-th counting stage. The logic circuit of the counting stage is composed of a D flip-flop and an exclusive logic sum circuit. The positive logic output of the D flip-flop may be input to an exclusive OR circuit, and the output of this exclusive OR circuit may be coupled to the input of the D flip-flop which is the K-th counting stage. Furthermore, the logic circuit for the logic decoder section may be replaced with another gate that is logically equivalent when viewed from the counting stage side.

[0025]

As described above, according to the present invention, there is provided a detection circuit for detecting a falling edge or a rising edge of a composite synchronization signal, and a detection circuit for detecting a falling edge or a rising edge of a composite synchronization signal,
Is it equivalent to the product of the positive logic output of the counting stage of the K-th bit and the negative logic output of the counting stage of the K-2th bit and the negative logic output of the counting stage of the K-1th bit and the K-2 A counting circuit in which a logic circuit equivalent to the sum of positive logic outputs below the bit bit is coupled to a counting stage of the K-th bit, and counting in the counting circuit is started by the output of the detection circuit, which corresponds to about one horizontal scanning period. By including a control circuit for the counting circuit that stops counting by the counting circuit after counting the number of clocks, the counter is constantly operated within the video scanning period, and the number of simultaneous changes in the flip-flops with respect to the clock input can be controlled. Since the clock input can be made uniform, the generation of counter noise can be suppressed and the influence on analog signals can be minimized or prevented, and its practical effects are tremendous.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a horizontal synchronization signal detection device in an embodiment of the present invention.

FIG. 2 is a pulse timing diagram of each circuit configuring the horizontal synchronization signal detection device shown in FIG. 1;

FIG. 3 is a circuit diagram showing the basic configuration of a 1H counter in the horizontal synchronization signal detection device of FIG. 1;

FIG. 4 is a time chart of the counter shown in FIG. 3;

FIG. 5 is a schematic diagram of a horizontal synchronization section in an external synchronization method.

FIG. 6 is a block diagram of a conventional horizontal synchronization signal detection device.

FIG. 7 is a pulse timing diagram of each circuit constituting a conventional horizontal synchronization signal detection device.

[Explanation of symbols]

1 Edge detection circuit 2
Counter reset control circuit 3
1H counter 4
Horizontal synchronization signal generation circuit 311
Clock input terminal 312 Counter start pulse input terminal 313
Counter reset pulse input terminals 315 to 322
J-K flip-flop (counting stage) 323
R-S flip-flop 324
~329 Logic gate for logic decoder section (AND circuit)

Claims (1)

[Claims] 1. A detection circuit that detects a falling edge or a rising edge of a composite synchronization signal, and a positive logic output of a counting stage consisting of n bits, where K-1 (K is a natural number from 3 to n) bit. and the output of an AND circuit to which the negative logic output of the counting stage from the K-2th bit onwards is input, or the negative logic output of the counting stage from the K-1st bit and the positive logic output from the K-2nd bit onwards. a counting circuit in which the output of the logical sum circuit is coupled to the K-th bit counting stage; and a counting circuit arranged between the detection circuit and the counting circuit, and counting operation of the counting circuit in response to the output of the detection circuit. Horizontal synchronization signal detection device equipped with a control circuit that controls the period.